A reconfigurable logic element (LE) is developed for use in constructing a NULL Convention Logic (NCL) FPGA. It can be configured as any of the 27 fundamental NCL gates, including resettable and inverting variations, ...
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ISBN:
(纸本)9781595936004
A reconfigurable logic element (LE) is developed for use in constructing a NULL Convention Logic (NCL) FPGA. It can be configured as any of the 27 fundamental NCL gates, including resettable and inverting variations, and can utilize embedded registration for gates withthree or fewer inputs. the developed LE is compared with a previous NCL LE, showing that the one developed herein yields a more area efficient NCL circuit implementation. the NCL FPGA logic element is simulated at the transistor level using the 1.8V, 180nm TSMC CMOS process.
this paper describes a technique that reduces dynamic power in FPGAs by reducing the number of glitches in the global routing resources. the technique involves adding programmable delay elements within the logic block...
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ISBN:
(纸本)9781595936004
this paper describes a technique that reduces dynamic power in FPGAs by reducing the number of glitches in the global routing resources. the technique involves adding programmable delay elements within the logic blocks of an FPGA to programmably align the arrival times of early-arriving signals to the inputs of the lookup tables and to filter out glitches generated by earlier circuitry. On average, the proposed technique eliminates 91% of the glitching, which reduces overall FPGA power by 18%. the added circuitry increases overall area by 5% and critical-path delay by less than 1%. Furthermore, since it is applied after routing, the proposed technique requires no modifications to the existing FPGA routing architecture or CAD flow.
We present an architecture for a synthesizable datapath-oriented fieldprogrammablegate Array (FPGA) core which can be used to provide post-fabrication flexibility to a System-on-Chip (SoC). Our architecture is optim...
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ISBN:
(纸本)9781595936004
We present an architecture for a synthesizable datapath-oriented fieldprogrammablegate Array (FPGA) core which can be used to provide post-fabrication flexibility to a System-on-Chip (SoC). Our architecture is optimized for bus-based operations that are common in signal processing and computation intensive applications. It employs a directional routing architecture, which allows it to be synthesized using standard ASIC design tools and flows. We also describe a proof-of-concept layout of our core. It is shown that the proposed architecture is significantly more area efficient than the best previously reported synthesizable programmable logic core.
Reconfigurable computing can provide a significant speed-up factor to cryptographic and error correcting code algorithms. Finite field arithmetic is essential to both, but is difficult to implement efficiently. Finite...
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ISBN:
(纸本)9781595936004
Reconfigurable computing can provide a significant speed-up factor to cryptographic and error correcting code algorithms. Finite field arithmetic is essential to both, but is difficult to implement efficiently. Finite field instruction set extensions and a reconfiguration framework have been constructed to enable a finite field multiplier to be regenerated via software control. A performance evaluation has been created by generating a Finite field Extensions Unit with MicroBlaze processor in a Xilinx Virtex(2)Pro FPGA. By utilizing the in-system partial reconfiguration capability, the finite field multiplier can be customized to a particular size and definition. With a customized GF(2(163)) multiplier, a speed-up factor of 1530x has been demonstrated versus execution of the same algorithm on the MicroBlaze processor alone.
the third international Workshop on Overlay Architectures for FPGAs (OLAF) is held in Monterey, California, USA, on Feburary 22, 2017 and co-located with FPGA 2017: the 25thacm/sigdainternationalsymposium on field ...
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ISBN:
(纸本)9781450343541
the third international Workshop on Overlay Architectures for FPGAs (OLAF) is held in Monterey, California, USA, on Feburary 22, 2017 and co-located with FPGA 2017: the 25thacm/sigdainternationalsymposium on fieldprogrammablegatearrays. the main objective of the workshop is to address how overlay architectures can help address the challenges and opportunites provided by FPGA-based reconfigurable computing. the workshop provides a venue for researchers to present and discuss the latest developments in FPGA overlay architecture and related areas. We have assembled a program of six refereed papers with panel discussions with prominent experts in the field.
the Second international Workshop on Overlay Architectures for FPGAs is held in Monterey, California, USA, on February 21, 2016 and co-located with FPGA 2016: the 24thacm/sigdainternationalsymposium on field Progra...
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ISBN:
(纸本)9781450338561
the Second international Workshop on Overlay Architectures for FPGAs is held in Monterey, California, USA, on February 21, 2016 and co-located with FPGA 2016: the 24thacm/sigdainternationalsymposium on fieldprogrammablegatearrays. the main objective of the workshop is to address how overlay architectures can help address the challenges and opportunities provided by FPGA-based reconfigurable computing. the workshop provides a venue for researchers to present and discuss the latest developments in FPGA overlay architecture and related areas. We have assembled a program of six refereed papers and a panel discussion with prominent experts in the field.
In this paper we propose new techniques for thermal and power characterization of fieldprogrammablegatearrays (FPGAs) using infrared imaging techniques. For thermal characterization, we capture the thermal emission...
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ISBN:
(纸本)9781450305549
In this paper we propose new techniques for thermal and power characterization of fieldprogrammablegatearrays (FPGAs) using infrared imaging techniques. For thermal characterization, we capture the thermal emissions from the backside of an FPGA chip during operation. We analyze the captured emissions and quantify the extent of thermal gradients and hot spots in FPGAs. Given that FPGAs are fabricated with no knowledge of the potential field designs, we propose soft sensing techniques that can combine the measurements of hard sensors to accurately estimate the temperatures where no sensors are embedded. For power characterization, we propose algorithmic techniques to invert the thermal emissions from FPGAs into spatial power estimates. We demonstrate how this technique can be used to produce spatial power maps of soft processors during operation.
this paper describes a bus mastering implementation of the PCI Express protocol using a Xilinx FPGA. While the theoretical peak performance of PCI Express is quite high, attaining that performance is a complex endeavo...
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ISBN:
(纸本)9781605584102
this paper describes a bus mastering implementation of the PCI Express protocol using a Xilinx FPGA. While the theoretical peak performance of PCI Express is quite high, attaining that performance is a complex endeavor on top of an already complex protocol. the implementation is described and its performance is analyzed. Source code is offered for free download via the web. Copyright 2009 acm.
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