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检索条件"任意字段=15th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays"

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PyXEL: An Integrated Environment for the Analysis of Fault Effects in SRAM-Based FPGA Routing 29

PyXEL: An Integrated Environment for the Analysis of Fault E...

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29th international symposium on Rapid System Prototyping, RSP 2018

作者： Bozzoli, Ludovica De Sio, Corrado Sterpone, Luca Bernardeschi, Cinzia Dipartimento di Automatica e Informatica Politecnico di Torino Torino Italy Department of Information Engineering University of Pisa Pisa Italy

ISBN: (纸本)9781538675571

In the last decades, FPGAs have been increasingly used in many different mission critical applications, such as the avionics and aerospace ones. thus, research interest in studying faults in FPGAs has seen a sharp increase, especially for those applications that require high dependability and must operate in harsh environments. the increase of resources available in FPGA devices has caused a huge growth in routing complexity. Nowadays, more than 80% of transistors in modern FPGAs are related to the routing infrastructure. the analysis of faults related to routing structure of FPGA devices is a hard task due to the lack of tools working at low-level, limited information availability about interconnection structure from vendors and, above all, no automated testing workflow for such kind of resources. In this paper, we introduce PyXEL, an integrated environment realized to automatize the analysis of fault effects in FPGAs routing structure. PyXEL is a Python-based framework that allows to easily manipulate FPGAs bitstreams in order to inject specific faults and to analyze their behavior. Moreover, PyXEL provides an easy way to build and run experimental workflow interacting directly with Xilinx Vivado and ISE allowing to select routing resources to test and logically analyze results. We demonstrated the feasibility and the advantages of our approach exploiting PyXEL to gain insight into the electrical effects of faults in the routing interconnections of the Xilinx Artix-7. © 2018 IEEE.

关键词： field programmable gate arrays (FPGA)

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Implementation and Optimization of the Accelerator Based on FPGA Hardware for LSTM Network 15

Implementation and Optimization of the Accelerator Based on ...

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15th IEEE international symposium on Parallel and Distributed Processing with Applications (ISPA) / 16th IEEE international Conference on Ubiquitous Computing and Communications (IUCC)

作者： Zhang, Yiwei Wang, Chao Gong, Lei Lu, Yuntao Sun, Fan Xu, Chongchong Li, Xi Zhou, Xuehai USTC Dept Comp Sci & Technol Hefei 230027 Anhui Peoples R China USTC Suzhou Inst Adv Study Suzhou Peoples R China

ISBN: (纸本)9781538637906

Today, artificial neural networks (ANNs) are important machine learning methods which are widely used in a variety of applications. As the emerging field of ANNs, recurrent neural networks (RNNs) are often used for sequence-related applications. And Long Short-Term Memory (LSTM) is an improved RNN which contains complex computational logic. To achieve high accuracy, researchers always build large-scale LSTM networks which are time-consuming and power-consuming. thus the acceleration of LSTM networks, low power & energy consumption become the hot issues in today's research. In this paper, we present a hardware accelerator for the LSTM neural network layer based on FPGA Zedboard and use pipeline methods to parallelize the forward computing process. To optimize our implementation, we also use multiple methods including tiled matrix-vector multiplication, binary adder tree, and overlap of computation and data access. through the acceleration and optimization methods, our accelerator is power-efficient and has a better performance than ARM Cortex A9 processor and Intel Core i5 processor.

关键词： field programmable gate arrays Adders Pipelines Vegetation Hardware Acceleration Computer architecture

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Prototyping dynamic task migration on heterogeneous reconfigurable systems 28

Prototyping dynamic task migration on heterogeneous reconfig...

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2017 28th international symposium on Rapid System Prototyping: Shortening the Path from Specification to Prototype, RSP 2017

作者： Wicaksana, Arief Bourge, Alban Muller, Olivier Sasongko, Arif Rousseau, Frédéric Univ. Grenoble Alpes TIMA CNRS Grenoble France Institut Teknologi Bandung Bandung Indonesia

ISBN: (纸本)9781450354189

Reconfigurable devices, such as FPGAs, have been known to offer an excellent performance and a high efficiency in computation. Due to their improving capacity and more efficient architecture recently, there are growing interests in using FPGAs as coprocessors in reconfigurable systems. However, FPGAs still lack the support in dynamic scheduling, e.g. to manage multiple tasks or users in a system. Performing runtime task relocation or load distribution is not possible unless the reconfigurable system supports dynamic task migration. Such ability requires the automation of configuration and context management in reconfigurable architecture, which is not available in the existing solutions. In this paper, we propose a framework for prototyping dynamic task migration between heterogeneous FPGAs. A task running on one FPGA can be suspended and resumed on another FPGA with different architecture. the extraction and restoration of FPGA registers and memory values are possible due to the task-specific extraction mechanism provided by the tasks. the proposed framework exploits a high-performance embedded processor tightly-coupled to an FPGA to automatically manage the configuration and context. It utilizes two popular heterogeneous reconfigurable systems in the implementation, Xilinx Zynq ZC706 and Altera Arria V SoC. Tests are performed using graphical and non-graphical benchmark applications and performance results are presented. © 2017 acm.

关键词： field programmable gate arrays (FPGA)

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Session details: New directions for programmable devices 05

Session details: New directions for programmable devices

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Proceedings of the 2005 acm/sigda 13th international symposium on field-programmable gate arrays

作者： Steve Trimberger Xilinx

No abstract available.

ISBN: (纸本)9781595930293

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Rapid Prototyping of Parameterized Rotated and Cyclic Q Delayed Constellations Demapper 29

Rapid Prototyping of Parameterized Rotated and Cyclic Q Dela...

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29th international symposium on Rapid System Prototyping, RSP 2018

作者： Waqas, Muhammad Jafri, Atif Raza Baghdadi, Amer Najam-Ul-Islam, M. Bahria University Islamabad Pakistan Lab-STICC laboratory IMT Atlantique Brest France

ISBN: (纸本)9781538675571

Rotated and Cyclic Q Delayed (RCQD) modulation is one of the signal processing schemes which, once used on the transmitter side, provides performance improvement on receiver side in case of fading channel conditions with erasures. However, an efficient hardware solution in terms of low area and high throughput is mandatory to get benefit from this modulation technique. In this paper we have implemented a parameterized hardware architecture of most recent RCQD demapping technique supporting different constellations. In addition to the description of the proposed hardware architecture, rapid prototyping flow based on LabVIEW FPGA is described which is useful to explore different design schemes in short period of time. the implementation results are achieved by FPGA prototyping while targeting NI-USRP RIO hardware equipment. By comparing our rapidly prototyped parameterized RCQD demapper with other state-of-the-art implementation schemes, it is shown that our prototyped demapper consumed lesser hardware resources and achieved higher throughput with very short design time. © 2018 IEEE.

关键词： field programmable gate arrays (FPGA)

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SEU-Mitigation placement and routing algorithms and their impact in SRAM-based FPGAs

SEU-Mitigation placement and routing algorithms and their im...

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8th international symposium on Quality Electronic Design

作者： Zarandi, Hamid R. Miremadi, Seyed G. Pradhan, Dhiraj K. Mathew, Jimson Sharif Univ Technol Dept Comp Engn Tehran Iran Univ Bristol Dept Comp Sci Bristol Avon England

ISBN: (纸本)9780769527956

In this paper, we propose a new SEU-mitigative placement and routing of circuits in the FPGAs which is based on the popular VPR tool. the VPR tool is modified so that during placement and routing, decisions are taken with awareness of SEU-mitigation. Moreover, no redundancies during the placement and routing are used but the algorithms are based on the SEU avoidance. Using the modified tool, i.e., S-VPR, the role of placement and routing algorithms on the fault-tolerance of circuits implemented on FPGAs is achieved. the secondary propose of this paper is to find which of placement or routing is more suited for decreasing SEU sensibility of circuits and to find whether these SEU sensibility reductions are cumulative or not when they applied in sequence. We have investigated the effect of S-VPR on several MCNC benchmarks and the results of the placement and routing have been compared to the traditional one. the evaluations of results show that placement and routing can decrease the SEU rate of circuits implemented on FPGAs about 18% and 12%, respectively. However, it increases critical path delay and power consumptions of the circuits up to 5% and 8%, respectively. this means that without any redundancies, just by means of fault-avoidance method, mitigation of SEU effects would decrease up to 22% significantly and this method is notable compared to previous TMR and DWC mechanisms.

关键词： field programmable gate arrays (FPGA)

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Design and FPGA Implementation of Lite Convolutional Neural Network Based Hardware Accelerator for Ocular Biometrics Recognition Technology 15

Design and FPGA Implementation of Lite Convolutional Neural ...

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15th IEEE international symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2022

作者： Sun, Wei-Che Fan, Chih-Peng Wu, Chung-Bin National Chung Hsing University Department of Electrical Engineering Taichung city Taiwan

ISBN: (纸本)9781665464994

In this study, the effective low-complexity Convolutional Neural Network (CNN) inference network is implemented by the FPGA-based hardware accelerator for the biometric authentications. After the labeling processes, the eye images with partial iris and sclera zones are used to train and test the LeNet-based Lite-CNN model. then the lightweight CNN classifier is rapidly prototyped via FPGA for hardware acceleration. through testing, the proposed Lite-CNN model achieves up to 98% recognition accuracy with the eye images. Compared with the software-based implementation, the proposed Lite-CNN hardware accelerator provides similar detection accuracy, and the inference time of 0.0246 seconds is accelerated about 377 times on the Xilinx ZCU102 FPGA platform. Besides, compared with the previous FPGA implementation by the high level synthesis design, the proposed hardware acceleration design performs the computing speed more than about 92 times. © 2022 IEEE.

关键词： field programmable gate arrays (FPGA)

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A Resource Reduced Application-Specific FPGA Switch 15th

A Resource Reduced Application-Specific FPGA Switch

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15th international symposium on Applied Reconfigurable Computing

作者： Zhao, Qian Ohnishi, Yoshimasa Iida, Masahiro Yoshida, Takaichi Kyushu Inst Technol 680-4 Kawazu Iizuka Japan Kumamoto Univ Chuo Ku 2-39-1 Kurokami Kumamoto Japan

ISBN: (纸本)9783030172268;9783030172275

Public cloud providers are employing more and more FPGAs as hardware accelerators in data centers. For large applications that requiring cooperation among multiple FPGAs, a network for connecting these accelerators is necessary. Most high-performance commercial switches are designed for general purpose networks, so that have high costs. On the other hand, FPGA-based programmable switches can be customized with minimum necessary functions, but the high-performance full-crossbar design requires too many resources to implement a many-port switch on them. In this work, based on the fact that network topologies of a specific type of applications commonly follow a particular pattern, we show a method of designing and implementing an application-specific switch with reduced resources on FPGAs. Our case studies show that such resource reduced switches can implement a high-performance network with low-cost commercial FPGAs.

关键词： field programmable gate arrays (FPGA)

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Digital Realization for Ca2+ Waves Stimulated by the (mGlu5) Receptors 15

Digital Realization for Ca2+ Waves Stimulated by the (mGlu5)...

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15th international symposium on Signals, Circuits and Systems, ISSCS 2021

作者： Seyedbarhagh, Mahsasadat Ahmadi, Arash Ahmadi, Majid University of Windsor Department of Electrical and Computer Engineering WindsorONN9B 3P4 Canada

ISBN: (纸本)9781665449427

Astrocytes are known as electrically non-excitable cells, responsible for information processing and ubiquitously expressed through mammalian Central Nervous System (CNS). Any disruption on astrocytic Ca2+ signalling can lead to neurodegenerative disorders like Alzheimer's Disease (AD). A digital hardware design for astrocyte model with metabotropic Glu receptor 5 (mGluR5)-induced Ca2+ oscillations is presented here. In this paper, a set of piecewise linear functions is presented for this model to reduce the hardware resources and digital design complexity. Hardware synthesis and numerical simulation validate that the designed circuit can mimic the biophysical Ca2+ behavior with lower hardware cost. this model can be utilized for large-scale neurophysiological system of astrocytic Ca2+ excitability. © 2021 IEEE.

关键词： field programmable gate arrays (FPGA)

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(ReCo)Fuse Your PRC or Lose Security: Finally Reliable Reconfiguration-Based Countermeasures on FPGAs 15th

(ReCo)Fuse Your PRC or Lose Security: Finally Reliable Recon...

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15th international symposium on Applied Reconfigurable Computing

作者： Schmitz, Kenneth Ustaoglu, Buse Grosse, Daniel Drechsler, Rolf DFKI GmbH Cyber Phys Syst D-28359 Bremen Germany Univ Bremen Inst Comp Architecture D-28359 Bremen Germany

ISBN: (纸本)9783030172268;9783030172275

Partial reconfiguration is a powerful technique to adapt the functionality of field programmable gate arrays (FPGAs) at run time. When performing partial reconfiguration a dedicated Intellectual Property (IP) component of the FPGA vendor, i.e. the Partial Reconfiguration Controller (PRC), among a wide range of IP components has to be used. While ensuring the functional safety of FPGA designs is well understood, ensuring hardware security is still very challenging. this applies in particular to reconfiguration-based countermeasures which are intensively used to form a moving target for the attacker. However, from the system security perspective a critical component is the above mentioned PRC as noticed by many papers implementing reconfiguration-based countermeasures against SCA/DPA attacks. In this work, we leverage a new proposed safety mechanism which creates a container around an IP, to encapsulate and thereby to protect and observe the PRC of an FPGA. the proposed encapsulation scheme results in an architecture consisting of so-called ReCoFuses (RCFs), each capturing a specific protective goal which have to be fulfilled at any time during PRC operation. the terminology follows the classical electric installation including a fuse box. In our scheme we employ formal verification to guarantee the correctness in detecting a security violation. Only after successful verification, the RCFs are integrated into the ReCoFuse Container. Experimental results demonstrate the advantage of our approach by preventing attacks on the PRC of a system secured by reconfiguration.

关键词： field programmable gate arrays (FPGA)

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