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Minimax Optimal Estimators for Additive Scalar Functionals of Discrete Distributions

Minimax Optimal Estimators for Additive Scalar Functionals o...

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IEEE international symposium on Information theory (ISIT)

作者： Fukuchi, Kazuto Sakuma, Jun Univ Tsukuba Grad Sch SIE Dept Comp Sci 1-1-1 Tennodai Tsukuba Ibaraki 3058577 Japan Japan Soc Promot Sci Chiyoda Ku Kojimachi Business Ctr Bldg5-3-1 Kojimachi Tokyo 1020083 Japan JST CREST Chiyoda Ku Ks Gobancho 6F7 Gobancho Tokyo 1020076 Japan RIKEN Ctr Adv Intelligence Project Chuo Ku Nihonbashi 1 Chome Mitsui Bldg15th Floor Tokyo 1030027 Japan

ISBN: (纸本)9781509040964

In this paper, we consider estimators for an additive functional of phi, which is defined as theta(P;phi) = Sigma(k)(i=1) phi(p(i)), from n i.i.d. random samples drawn from a discrete distribution P = (p(1),...,p(k)) with alphabet size k. We propose a minimax optimal estimator for the estimation problem of the additive functional. We reveal that the minimax optimal rate is characterized by the divergence speed of the fourth derivative of phi if the divergence speed is high. As a result, we show there is no consistent estimator if the divergence speed of the fourth derivative of phi is larger than p(-4). Furthermore, if the divergence speed of the fourth derivative of phi is p(4-alpha) for alpha is an element of(0,1), the minimax optimal rate is obtained within a universal multiplicative constant as k(2)/(n vertical bar nn)(2 alpha) + k(2-2 alpha)/n.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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FPGA-Based Prototype of a Quantum Annealing Simulator for Sparse Ising Model 15

FPGA-Based Prototype of a Quantum Annealing Simulator for Sp...

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15th IEEE international symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2022

作者： Waidyasooriya, Hasitha Muthumala Ohma, Yuta Hariyama, Masanori Tohoku University Graduate School of Information Sciences Sendai Miyagi980-8579 Japan

ISBN: (纸本)9781665464994

Quantum annealing (QA) is a probabilistic approx-imation method to find the global optimum of a combinatorial optimization problem. QA is done on quantum annealers such as D-wave using quantum properties. Since the number of qubits in quantum annealers is limited, it is difficult to use those to solve large-scale real-world problems. therefore, quantum annealing simulation on digital computers is necessary. In this paper, we discuss an FPGA based quantum annealing simulator for sparse Ising model. Unlike a fully-connected Ising model, the number of connections among spins in sparse model is limited. Highly sparse Ising models require significantly low amount of computations while allowing more parallel operations. One the other hand, sparsity and the connections among spins are not the same for different Ising models, and it is difficult to propose one specific accelerator architecture for all. We propose a method to automatically generate an application specific accelerator archi-tecture for a given sparse Ising model. the proposed accelerator fully exploits the parallelism to increase the processing speed. We design an FPGA prototype of the proposed accelerator and confirmed the correct behavior. In future, we expect to extend the proposed method to execute large quantum annealing simulations using multiple FPGAs. © 2022 IEEE.

关键词： field programmable gate arrays (FPGA)

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Hardwired-clusters partial-crossbar: A hierarchical routing architecture for multi-FPGA systems 13th

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13th international Parallel Processing symposium, IPPS 1999 Held in Conjunction with the 10th symposium on Parallel and Distributed Processing, SPDP 1999

作者： Khalid, Mohammed A.S. Rose, Jonathan Quicktum Design Systems 55 West Trimble Road San JoseCA95131-1013 Canada Department of Electrical and Computer Engineering University of Toronto TorontoONM5S 3G4 Canada

ISBN: (纸本)3540658319

Multi-FPGA systems (MFSs) are used as custom computing machines, logic emulators and rapid prototyping vehicles. A key aspect of these systems is their programmable routing architecture which is the manner in which wires, FPGAs and field-programmable Interconnect Devices (FPIDs) are connected. Several routing architectures for MFSs have been proposed [Amo92] [Butt92] [Hauc94] [Apti96] [Vui196] [Babb97] and previous research has shown that the partial crossbar is one of the best existing architectures [Kim96] [Kha197]. Recently, the Hybrid Complete-Graph Partial-Crossbar Architecture (HCGP) was proposed [Kha198], which was shown to be superior to the Partial Crossbar. In this paper we propose a new routing architecture, called the Hardwired-Clusters Partial-Crossbar (HWCP) which is better suited for large MFSs implemented using multiple boards. the HWCP architecture is compared to the HCGP and Partial Crossbar and we show that it gives substantially better manufacturability. We compare the performance and cost of the HWCP, HCGP and Partial Crossbar architectures experimentally, by mapping a set of 15 large benchmark circuits into each architecture. We show that the HWCP architecture gives reasonably good cost and speed compared to the HCGP and Partial Crossbar architectures. © Springer-Verlag Berlin Heidelberg 1999.

关键词： field programmable gate arrays (FPGA)

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CReconfigurable finite field instruction set architecture 07

CReconfigurable finite field instruction set architecture

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Proceedings of the 2007 acm/sigda 15th international symposium on field programmable gate arrays

作者： Nathan Jachimie Fernando Martinez-Vallin Jafar Saniie Illinois Institute of Technology Chicago Illinois

ISBN: (纸本)9781595936004

Reconfigurable computing can provide a significant speed-up factor to cryptographic and error correcting code algorithms. Finite field arithmetic is essential to both, but is difficult to implement efficiently. Finite field instruction set extensions and a reconfiguration framework have been constructed to enable a finite field multiplier to be regenerated via software control. A performance evaluation has been created by generating a Finite field Extensions Unit with MicroBlaze processor in a Xilinx Virtex2Pro FPGA. By utilizing the in-system partial reconfiguration capability, the finite field multiplier can be customized to a particular size and definition. With a customized GF(2163 ) multiplier, a speed-up factor of 1530X has been demonstrated versus execution of the same algorithm on the MicroBlaze processor alone.

关键词： FSL instruction set extensions Xilinx fast simplex links galois fields MicroBlaze embedded development partial reconfiguration finite field arithmetic

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Accelerating Non-Negative Matrix Factorization on Embedded FPGA with Hybrid Logarithmic Dot-Product Approximation 15

Accelerating Non-Negative Matrix Factorization on Embedded F...

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15th IEEE international symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2022

作者： Chen, Yizhi Nevarez, Yarib Lu, Zhonghai Garcia-Ortiz, Alberto Kth Royal Institute of Technology School of Electrical Engineering and Computer Science Stockholm Sweden Bremen Germany

ISBN: (纸本)9781665464994

Non-negative matrix factorization (NMF) is an ef-fective method for dimensionality reduction and sparse decom-position. this method has been of great interest to the scien-tific community in applications including signal processing, data mining, compression, and pattern recognition. However, NMF implies elevated computational costs in terms of performance and energy consumption, which is inadequate for embedded applications. To overcome this limitation, we implement the vector dot-product with hybrid logarithmic approximation as a hardware optimization approach. this technique accelerates floating-point computation, reduces energy consumption, and preserves accuracy. To demonstrate our approach, we employ a design exploration flow using high-level synthesis on an embedded FPGA. Compared with software solutions on ARM CPU, this hardware implementation accelerates the overall computation to decompose matrix by 5.597 × and reduces energy consumption by 69.323×. Log approximation NMF combined with KNN(k-nearest neighbors) has only 2.38% decreasing accuracy compared with the result of KNN processing the matrix after floating-point NMF on MNIST. Further on, compared with a dedicated floating-point accelerator, the logarithmic approximation approach achieves 3.718× acceleration and 8.345× energy reduction. Compared with the fixed-point approach, our approach has an accuracy degradation of 1.93% on MNIST and an accuracy amelioration of 28.2% on the FASHION MNIST data set without pre-knowledge of the data range. thus, our approach has better compatibility with the input data range. © 2022 IEEE.

关键词： field programmable gate arrays (FPGA)

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HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond 24

HLSFactory: A Framework Empowering High-Level Synthesis Data...

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6th international symposium on Machine Learning for CAD (MLCAD)

作者： Abi-Karam, Stefan Sarkar, Rishov Seigler, Allison Lowe, Sean Wei, Zhigang Chen, Hanqiu Rao, Nanditha John, Lizy Arora, Aman Hao, Cong Georgia Inst Technol Atlanta GA 30332 USA Georgia Tech Res Inst Atlanta GA 30332 USA Univ Texas Austin Austin TX USA Arizona State Univ Tempe AZ USA Int Inst Informat Technol Bangalore Bangalore Karnataka India

ISBN: (数字)9798350363562

ISBN: (纸本)9798400706998

Machine learning (ML) techniques have been applied to high-level synthesis (HLS) flows for quality-of-result (QoR) prediction and design space exploration (DSE). Nevertheless, the scarcity of accessible highquality HLS datasets and the complexity of building such datasets present great challenges to FPGA and ML researchers. Existing datasets either cover only a subset of previously published benchmarks, provide no way to enumerate optimization design spaces, are limited to a specific vendor, or have no reproducible and extensible software for dataset construction. Many works also lack user-friendly ways to add more designs to existing datasets, limiting wider adoption and sustainability of such datasets. In response to these challenges, we introduce HLSFactory, a comprehensive framework designed to facilitate the curation and generation of high-quality HLS design datasets. HLSFactory has three main stages: 1) a design space expansion stage to elaborate single HLS designs into large design spaces using various optimization directives across multiple vendor tools, 2) a design synthesis stage to execute HLS and FPGA tool flows concurrently across designs, and 3) a data aggregation stage for extracting standardized data into packaged datasets for ML usage. this tripartite architecture not only ensures broad coverage of data points via design space expansion but also supports interoperability with tools from multiple vendors. Users can contribute to each stage easily by submitting their own HLS designs or synthesis results via provided user APIs. the framework is also flexible, allowing extensions at every step via user APIs with custom frontends, synthesis tools, and scripts. To demonstrate the framework functionality, we include an initial set of built-in base designs from PolyBench, MachSuite, Rosetta, CHStone, Kastner et al.'s Parallel Programming for FPGAs, and curated kernels from existing open-source HLS designs. We report the statistical analyses and design space

关键词： Solid modeling Statistical analysis Buildings Machine learning Benchmark testing Software Space exploration Sustainable development field programmable gate arrays Optimization

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Energy/power estimation of regular processor arrays

Energy/power estimation of regular processor arrays

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international symposium on System Synthesis

作者： S. Derrien S. Rajopadhye IRISA France Colorado State University USA

We propose a high-level analytical model for estimating the energy and/or power dissipation in VLSI processor (systolic) array implementations of loop programs, particularly for implementations on FPGA based CO-processors. We focus on the respective impact of the array design parameters on the overall off-chip I/O traffic and the number and sizes of the local memories in the array. the model is validated experimentally and shows good results (12.7% RMS error in the predictions).

关键词： Power system modeling Very large scale integration Analytical models programmable logic arrays Energy consumption Kernel field programmable gate arrays Logic design Embedded system Power dissipation

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Worst-Case Latency Analysis for the Versal NoC Network Packet Switch

Worst-Case Latency Analysis for the Versal NoC Network Packe...

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international symposium on Networks-on-Chip (NOCS)

作者： Ian Lang Nachiket Kapre Rodolfo Pellizzoni University of Waterloo Waterloo Canada

ISBN: (纸本)9781665417228

the recent line of Versal FPGA devices from Xilinx Inc. includes a hard Network-On-Chip (NoC) embedded in the programmable logic, designed to be a high-performance system-level interconnect. While the target markets for Versal devices include applications with real-time constraints, such as automotive driver assist, the associated development tools only provide figures for “structural latencies” of data packets, which assume that the network is otherwise idle. In a realistic setting, this information is not enough to ensure deadlines are met, as different packets can contend for NoC switch outputs, which causes packet contents to be buffered while in transit, increasing their latency. In this work, we present a formal description of the NPS switches that compose the Versal NoC from a flit (or packet) scheduling perspective, based on the available cycle-accurate switch simulation code. We then analyze a scenario where network clients transfer data periodically over a single switch, and propose a method for calculating worst-case communication times in this scenario.

关键词： Codes Scheduling algorithms Switches Network-on-chip Tools Real-time systems field programmable gate arrays

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programmable Logic Controller based on reconfigurable logic

Programmable Logic Controller based on reconfigurable logic

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international symposium for Design and Technology of Electronics Packages (SIITME)

作者： Edward Hrynkiewicz Adam Milik Dariusz Polok Institute of Electronics Silesian University of Technology in Gliwice Gliwice Poland

the paper presents an idea of a programmable Logic Controller for binary control implemented in an FPGA device with use of custom designed implementation tools. It is an extension of previously proposed architecture that is mainly limited by hardwired connection. Based on connection resources available in FPGA the new architecture is proposed. Possible computation capabilities of FPGA devices are discussed. the research task is continued and looking for nonmultiplexed solution with extended usage of programmable connections and better exploit of logic resources.

关键词： programmable control Reconfigurable logic field programmable gate arrays Hardware Logic devices Centralized control Circuits Signal processing Paper technology Electronics packaging

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Towards 5ps resolution TDC on a dynamically reconfigurable FPGA (abstract only) 10

Towards 5ps resolution TDC on a dynamically reconfigurable F...

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Proceedings of the 18th annual acm/sigda international symposium on field programmable gate arrays

作者： Marc-Andre Daigneault Jean Pierre David École Polytechnique de Montréal Montreal PQ Canada

ISBN: (纸本)9781605589114

this paper presents the implementation of a high resolution time-to-digital converter (TDC) on a dynamically reconfigurable FPGA. the TDC architecture is based on the Vernier method using two ring oscillators with slightly different frequencies. the proposed oscillators can be calibrated with picoseconds resolution by taking advantage of partial reconfiguration, and moreover recalibrated over time. the results obtained on a Xilinx Virtex-II Pro FPGA show that the proposed TDC implementation can achieve unprecedented resolutions (on FPGA) as low as 5ps and precisions up to 25ps.

关键词： field programmable gate array time-to-digital converter vernier method dynamic reconfiguration

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