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Design and simulation of a three-phase generator for use with smart systems in medical microinstrumentation

Design and simulation of a three-phase generator for use wit...

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IEEE international symposium on Consumer Electronics (ISCE)

作者： Jesús García-Guzmán Hugo R. Morales-Andrade Alfredo Ramírez-Ramírez Jorge A. Vélez-Enríquez Facultad de Ingeniería Mecánica y Eléctrica Universidad Veracruzana Veracruz Mexico

In this paper, we report on the design of a digital three-phase micro-generator of voltage that is going to be part of a lab-on-chip system based on smart sensors for medical diagnosis and instrumentation. the digital generator is implemented on a field-programmable gate array (FPGA) and it will deliver three voltage waveforms with equal magnitudes and phase shifted 120° one of each other. the benefits of this power source are mainly related to the ability of balanced three phase systems to deliver constant instantaneous power to the loads, thus eliminating vibrations and other disturbances produced by oscillation in the output waveforms of typical mono phase systems. It is expected that the resulting three phase digital generator will serve as a very reliable power source for driving micromechanical actuators used in sophisticated medical applications.

关键词： Generators Actuators field programmable gate arrays Band pass filters Integrated circuit modeling Instruments Radiation detectors

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From high-level deep neural models to FPGAS 49

From high-level deep neural models to FPGAS

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49th Annual IEEE/acm international symposium on Microarchitecture, MICRO 2016

作者： Sharma, Hardik Park, Jongse Mahajan, Divya Amaro, Emmanuel Kim, Joon Kyung Shao, Chenkai Mishra, Asit Esmaeilzadeh, Hadi Lab School of Computer Science Georgia Institute of Technology United States Intel Corporation United States

ISBN: (纸本)9781509035083

Deep Neural Networks (DNNs) are compute-intensive learning models with growing applicability in a wide range of domains. FPGAS are an attractive choice for DNNs since they offer a programmable substrate for acceleration and are becoming available across different market segments. However, obtaining both performance and energy efficiency with FPGAS is a laborious task even for expert hardware designers. Furthermore, the large memory footprint of DNNs, coupled with the FPGAS' limited on-chip storage makes DNN acceleration using FPGAS more challenging. this work tackles these challenges by devising DnnWeaver, a framework that automatically generates a synthesizable accelerator for a given (DNN, FPGA) pair from a high-level specification in Caffe [1]. To achieve large benefits while preserving automation, DNNWEAVER generates accelerators using hand-optimized design templates. First, DnnWeaver translates a given high-level DNN specification to its novel ISA that represents a macro dataflow graph of the DNN. the DnnWeaver compiler is equipped with our optimization algorithm that tiles, schedules, and batches DNN operations to maximize data reuse and best utilize target FPGA's memory and other resources. the final result is a custom synthesizable accelerator that best matches the needs of the DNN while providing high performance and efficiency gains for the target FPGA. We use DnnWeaver to generate accelerators for a set of eight different DNN models and three different FPGAS, Xilinx Zynq, Altera Stratix V, and Altera Arria 10. We use hardware measurements to compare the generated accelerators to both multicore CPUs (ARM Cortex A15 and Xeon E3) and many-core GPUs (Tegra K1, GTX 650Ti, and Tesla K40). In comparison, the generated accelerators deliver superior performance and efficiency without requiring the programmers to participate in the arduous task of hardware design. © 2016 IEEE.

关键词： field programmable gate arrays (FPGA)

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Implementation of motor controller using Zynq EPP

Implementation of motor controller using Zynq EPP

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international symposium on Soft Computing and Intelligent Systems (SCIS)

作者： HuangLin Yun Young Pil Lee Yong Seon Moon Youngchul Bae Department of Biomedical and Electronic Engineering Chonnam National Univ. Jeonnam Korea Department of Electronic Engineering Sunchon National Univ. Sunchon Jeonnam Korea REDONE TECHNOLOGIES CO. LTD. Gwangju Korea Division of Electrical• Electronic Communication and Computer Engineering Chonnam National Univ. Jeonnam Korea

ISBN: (纸本)9781479959563

In this paper, in order to control motor, we apply latest All programmable SoC technologies that fuse FPGA technologies and embedded processor technologies. We also propose to apply method that the structure of motor controller decentralizes into FPGA and level of embedded processor. We verify the possibility of application of motor controllers through design, implementation and experiment for multi-axis motor controller using Zynq EPP(Extensible Processing Platform) which is one of All programmable SoC by made Xilinx.

关键词： Motor drives field programmable gate arrays Process control Position control Velocity control System-on-chip

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the design of a low energy FPGA 99

The design of a low energy FPGA

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international symposium on Low Power Electronics and Design (ISLPED)

作者： V. George Hui Zhang J. Rabaey Berkeley Wireless Research Center University of California Berkeley CA USA

ISBN: (纸本)9781581131338

this work presents the design of an energy efficient FPGA architecture. Significant reduction in the energy consumption is achieved by tackling both circuit design and architecture optimization issues concurrently. A hybrid interconnect structure incorporating nearest neighbor connections, symmetric mesh architecture, and hierarchical connectivity is used. the energy of the interconnect is also reduced by employing low-swing circuit techniques. these techniques have been employed to design and fabricate an FPGA. Preliminary analysis show energy improvement of more than an order of magnitude when compared to existing commercial architectures.

关键词： field programmable gate arrays Integrated circuit interconnections Computer architecture Power dissipation Energy efficiency Energy consumption Clocks Frequency Logic Switches

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FPGA implementation of highly parallelized decoder logic for network coding (abstract only) 10

FPGA implementation of highly parallelized decoder logic for...

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Proceedings of the 18th annual acm/sigda international symposium on field programmable gate arrays

作者： Sunwoo Kim Won W. Ro Yonsei University Seoul South Korea

ISBN: (纸本)9781605589114

Decoding operation is one of the major performance bottlenecks in network coding applications. To address the problem caused by decoding delay, this paper proposes high-performance decoding logic on the field-programmable gate-array (FPGA). A Galois field arithmetic logic unit (GF ALU) is implemented with a full parallelization. We claim that the complexity of hardware is reduced by use of the log and anti-log tables. In addition, the fast arithmetic operation is achieved by the parallelized GF ALU architecture, which allows one-row-calculations of a matrix to be performed concurrently. the decoders for four different sizes of the coefficient matrix have been implemented while the degree of parallelism is preserved for each size. the performance is evaluated by comparing with the performance of the decoding operation both on the ARM processor emulator and a real ARM processor. Using a modern Xilinx Virtex-5 device, the decoding time of 3.5 ms for the size 16 x 16 and 190.5 ms for 128 x 128 has been achieved at the operating frequency of 50MHz, which is equal to 12.7 and 21.7 in terms of speedup.

关键词： network coding fpga fpga implementation galois field arithmetic

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A programmable majority logic array using molecular scale electronics 06

A programmable majority logic array using molecular scale el...

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Proceedings of the 2006 acm/sigda 14th international symposium on field programmable gate arrays

作者： Garrett S. Rose Mircea R. Stan University of Virginia Charlottesville VA

ISBN: (纸本)9781595932921

We present a computer architecture design that utilizes molecular electronic devices fabricated from self-assembled monolayers (SAM) of molecules. this architecture has been designed for a process being developed at the University of Virginia where molecules are assembled via vapor phase deposition. As this process lends itself nicely to developing multiple layers of devices on a single substrate, the circuit and architectural designs presented here exist in three dimensions. through this work we show how molecular electronics naturally allows for 3D integration at the *** design consists of two types of molecular devices: switches with memory and resonant tunneling diodes (RTD). these switching molecules are patterned between layers of metal to form a uniform crossbar array that can behave similar to a programmable logic array (PLA). In this design, the crossbar arrays drive rows of circuits, referred to as Goto pairs, consisting of two stacked molecular RTDs. As described in previous work, a Goto pair with only one resistor driving its input functions as a latch whereas the circuit acts as a majority gate when driven by multiple resistors. Since the crossbar arrays can be programmed such that the various Goto pairs are driven by different numbers of inputs, the overall circuit has the ability to implement logic as networks of latches and majority gates. Using crossbar arrays in this way is somewhat different from other approaches in that logic is not simply implemented in the array but is a product of both the array and the Goto pair functionality.

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Porting transputer application to multi-processors strongARM system

Porting transputer application to multi-processors strongARM...

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international symposium on Parallel and Distributed Processing (IPDPS)

作者： E.W.K. Liew B.C. O'Neill S. Clark A. Cawley Department of Electrical & Electronic Engineering Nottingham Trent University Nottingham UK Quantel Limited Newbury Berkshire UK

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FPGA implementation of stochastic flash A-to-D converter and its evaluation

FPGA implementation of stochastic flash A-to-D converter and...

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international symposium on Communications and Information Technologies (ISCIT)

作者： Hisato Takehata Toshiki Sugimoto Hiroshi Tanimoto Shingo Yoshizawa Department of Electrical and Electronic Engineering Kitami Institute of Technology Kitami Japan

We report a hardware implementation of stochastic flash A-to-D converter (SFADC) with dynamic element matching (DEM) technique. For fast prototyping, the SFADC hardware was implemented on an FPGA board with 64 on-chip inverters using as comparators. the DEM circuit is implemented by analog multiplexer, which is put in front of the main SFADC. Measured histogram of comparator offset voltage resembles the normal distribution, but actually it is not, according to χ 2 test result for 5% p-value. However, the linearization and DEM works nicely and SFDR is improved more than 5 dB by proposed SFADC with DEM, even for non-normal distribution.

关键词： field programmable gate arrays Voltage measurement Gaussian distribution Standards Hardware Signal to noise ratio Information and communication technology

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FPGA-based fine-grain parallel computing (abstract only) 11

FPGA-based fine-grain parallel computing (abstract only)

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Proceedings of the 19th acm/sigda international symposium on field programmable gate arrays

作者： Andrew W. Hill Andrea Di Blas Richard Hughey University of California Santa Cruz Santa Cruz CA USA

ISBN: (纸本)9781450305549

FPGAs are increasing in computing power at a significant rate while the non-recurring engineering costs and time-to-market remain significant lower than those for application-specific integrated circuits (ASICs), encouraging FPGAs to be used in areas previous dominated by ASICs. In this study, we examine the appropriateness of FPGAs for high-performance, low-volume prodution parallel computing by mapping an existing ASIC-based massively parallel single-instruction, multiple data (SIMD) computer, the UCSC Kestrel, to a variety of FPGAs. the design has a raw peak performance of over 187 billion 8-bit operations per second (OPS), 48 times faster than the original ASIC-based Kestrel, using a Xilinx Virtex-6, and a cost efficiency of up to 81 MOPS/$ using a Xilinx Spartan-3. We also show that we can implement the entire original Kestrel (512 processing elements) as a system on a single programmable chip.

关键词： system on a programmable chip simd parallel computing

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Smart sensor platform for image processing applications

Smart sensor platform for image processing applications

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MECHATRONIKA international symposium

作者： Mathias Schellhorn Maik Rosenberger André Göpfert Steffen Lerm Gerhard Linss Department of Quality Assurance and Industrial Image Processing Ilmenau University of Technology Ilmenau Germany

For the use of image processing systems as fast but accurate measuring equipment, the precision of the image capture is a crucial feature. In addition, larger amounts of data must be processed as achievable sensor resolutions and frame rates increase steadily. the Department of Quality Assurance and Industrial Image Processing of the Ilmenau University of Technology has developed a sensor platform that supports these requirements in the industrial and metrological field. the hardware was designed in terms of modularity and the use of distributed algorithms. the aim of this development was to combine the integrated intelligence of the individual components of the system to create new applications possibilities on hardware-level and to make them usable over a central interface. this publication describes the hardware structure and discusses the possible applications of the sensor platform.

关键词： field programmable gate arrays Lighting Hardware Cameras Image edge detection Intelligent sensors

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