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A NetFPGA-based network monitoring system with multi-layer timestamping: Rnetprobe

A NetFPGA-based network monitoring system with multi-layer t...

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NETWORKS international Telecommunications Network Strategy and Planning symposium

作者： Peter Orosz Tamas Skopko Jozsef Imrek Faculty of Informatics University of Debrecen Debrecen Hungary

In this work, we are about to introduce a high performance NetFPGA based network measurement system, called Rnetprobe that implements a dual, multi-layer timestamping method for QoS analysis. the multi-layer timestamping idea came from the demand to perform end-to-end active measurements that enable improved cross-layer analysis to evaluate QoS for time sensitive services. Accordingly, for each captured packet one timestamp is generated at MAC level, which is provided by our FPGA hardware module, while another timestamp is tagged to the packet on its processing path as soon as it becomes available to the OS kernel's network stack. this second timestamp is software based and therefore reflects to the packet processing characteristics of the OS kernel. In this paper, we are introducing the mentioned multi-layer timestamping method and are evaluating its performance.

关键词： Hardware Clocks field programmable gate arrays Kernel Monitoring Delay

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Scalable architecture for programmable quantum gate array (abstract only) 10

Scalable architecture for programmable quantum gate array (a...

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Proceedings of the 18th annual acm/sigda international symposium on field programmable gate arrays

作者： Mingjie Lin Yaling Ma UC Berkeley Berkeley CA USA UC Berkeley Berkeley USA

ISBN: (纸本)9781605589114

this work explores architectural ideas to build a scalable programmable quantum gate array (PQGA) by exploiting unique quantum effects such as superposition and entanglement/teleportation. In contrast to prior studies, in which a quantum computing machine is implemented either as an ASIC-like special-purpose chip tailored for specific algorithm or as a general-purpose processor based on the Von-Neumann model, we propose a PQGA architecture that is reconfigurable for different domain-specific applications with high logic density. the PQGA architecture is novel in several aspects, among which its interconnect work is built with "virtual wires" implemented with quantum entanglement. In this work, we propose various designs for logic block, interconnect network, and design strategies to construct large designs in PQGA. Our goal is to investigate new architectural ideas based on reconfigurable computing method in order to overcome the primary scalability challenges of reliability, communication, and quantum resource distribution that plague current proposals for large-scale quantum comput- ing. Leveraging the extensive groundwork in quantum computing and algorithm design, we provide estimation results to show that our proposed PQGA architecture can achieve not only high performance but also scalability. Finally, we benchmark our proposed PQGA architecture against previous quantum computer architecture and illustrate on average a 3x improvement in terms of logic density for the well-known Shor's quantum factoring algorithm.

关键词： reconfigurable computing quantum

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Quantification and round influence on FPGA implemented algorithms for an OFDM radio interface

Quantification and round influence on FPGA implemented algor...

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IEEE international symposium on Personal, Indoor and Mobile Radio Communications (PIMRC)

作者： J.M. Vazquez B. Castan L.M. Campoy Telefónica Moviles Pozuelo de Alarcon Spain Telefònica I D Madrid Spain

OFDM is widely used as the physical radio layer in an increasingly high number of standards due to its ability to manage time and frequency SNR variations on the radio channels. First described by Chang in 1966, the high digital processing resources required for its implementation have delayed its commercialization until the 1990s. In order to speed up the algorithms implementations for real time transmission, the fixed point implementation is needed (based on ASIC, FPGA or DSP). As a drawback, fixed point implementation leads to quantification and round errors that needs to be taken into consideration in the algorithm design.

关键词： field programmable gate arrays OFDM Digital signal processing Signal processing Signal processing algorithms Web pages Application specific integrated circuits Ethernet networks Web server Linux

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Situated learning on FPGA for superscalar microprocessor design education 03

Situated learning on FPGA for superscalar microprocessor des...

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symposium on Integrated Circuits and Systems Design (SBCCI)

作者： R. Takahashi H. Ohiwa Faculty of Information Sciences Hiroshima City University Hiroshima Japan Shonan-Fujisawa Campus Keio University Fujisawa Japan

ISBN: (纸本)9780769520094

Microprocessor design education is acquiring critical importance, since highly sophisticated functions are supported by microprocessors in many products which cannot lose market windows. In our educational environment City-1, 7 out of 39 junior students had succeeded in implementing superscalar RISC processors on FPGAs, guided by an example hardware description language (HDL) description, within 15 weeks in 2001. With another example HDL description, 14 out of 47 junior students had succeeded in implementing superscalar CISC/RISC processors within the same weeks in 2002, featuring devices such as out-of-order completion, multiple-path execution, etc. We noticed that this could be regarded as an excellent illustration of situated learning on FPGAs which can be applied prior to on the job training (OJT) in companies. the most important thing is the choice of the tasks given as the way in for the beginners.

关键词： field programmable gate arrays Microprocessors

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FPGA-based testing strategy for cryptographic chips: A case study on Elliptic Curve Processor for RFID tags

FPGA-based testing strategy for cryptographic chips: A case ...

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IEEE symposium on On-Line Testing (IOLTS)

作者： Junfeng Fan Miroslav Knezevic Dusko Karaklajic Roel Maes Vladimir Rozic Lejla Batina Ingrid Verbauwhede ESAT/SCD-COSIC Katholieke Universiteit Leuven Leuven Belgium

Testing of cryptographic chips or components has one extra dimension: physical security. the chip designers should improve the design if it leaks too much information through side-channels, such as timing, power consumption, electric-magnetic radiation, and so on. this requires an evaluation of the security level of the chip under different side-channel attacks before it is manufactured. this paper presents an FPGA-based testing strategy for cryptographic chips. Using a block-based architecture, a testing bus and a shadow FPGA, we are able to check information leakage of each block. We describe this strategy with an Elliptic Curve Cryptosystem (ECC) for RFID tags.

关键词： Elliptic curve cryptography Elliptic curves RFID tags Circuit testing Public key cryptography Information security Manufacturing field programmable gate arrays Timing Energy consumption

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FPGA implementation of 4/spl times/4 MIMO test-bed for spatial multiplexing systems

FPGA implementation of 4/spl times/4 MIMO test-bed for spati...

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IEEE international symposium on Personal, Indoor and Mobile Radio Communications (PIMRC)

作者： M. Cui H. Murata K. Araki Graduate School of Science and Engineering Tokyo Institute of Technology Meguro Tokyo Japan

Multiple input multiple output (MIMO) transmission techniques hold the potential of dramatically increasing the data rates and spectral efficiency of wireless communication systems. However, since multiple transmitters and receivers are required, a large number of channel emulators are also required for in-lab experiments, resulting in an increase in equipment cost. this paper describes an implementation of received signal generator for a 4/spl times/4 MIMO transmission in one FPGA chip which can be utilized as a real-time MIMO spatial multiplexing system test-bed. Our experimental results demonstrate that the CDF and channel correlations of emulated Rayleigh fading under this fading channel approach the theoretical values.

关键词： field programmable gate arrays MIMO System testing Wireless communication Transmitters Costs Signal generators Real time systems Rayleigh channels Fading

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Memory based computing: reshaping the fine-grained logic in a reconfigurable framework (abstract only) 11

Memory based computing: reshaping the fine-grained logic in ...

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Proceedings of the 19th acm/sigda international symposium on field programmable gate arrays

作者： Somnath Paul Swarup Bhunia Case Western Reserve University Cleveland OH USA

ISBN: (纸本)9781450305549

Conventional field programmable gate Array (FPGA) architectures leverage on the purely spatial computing model where a design is realized in the form of a small multiple-input single-output lookup tables (LUTs) connected through programmable interconnect switches. However, such a model incorporates an elaborate programmable interconnect network which becomes a major performance bottleneck and leads to poor scalability across process technology nodes. In this paper we evaluate an alternative two-dimensional static random access memory (SRAM) array based reconfigurable computing fabric, referred to as "Memory Based Computing" (MBC) that departs from a purely spatial architecture by advocating multi-cycle evaluation at each computational element. Within a computational element, it uses a dense two-dimensional SRAM array to map large multi-input multi-output functions as LUT and evaluate them in time-multiplexed topological fashion. Multi-cycle execution at each computing node is accomplished using a local interconnect architecture. the proposed framework substantially reduces the requirement for global interconnects by folding computational resources onto a single computational element. We explore the design space for MBC to optimize the major design parameters and compare the performance, power dissipation and energy-delay product for benchmark applications between MBC and conventional SRAM-based FPGA. Simulation results show that compared to a clustered FPGA model, the proposed framework achieves 57% improvement in performance, 30% improvement in Energy Delay Product (EDP) and 10% improvement in technological scalability of performance for standard benchmark circuits. Finally, we validate the functionality of MBC framework and timing of different operations by mapping several small applications on a Cyclone III FPGA platform from Altera.

关键词： memory based computation field programmable gate array (fpga) recongurable hardware

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Rapid prototyping of AES encryption for wireless communication system on FPGA

Rapid prototyping of AES encryption for wireless communicati...

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IEEE international symposium on Consumer Electronics (ISCE)

作者： Anurag Gupta Afandi Ahmad Mhd Saeed Sharif Abbes Amira School of Engineering and Design Brunei University West London UK JEC Faculty of. Electrical and Electronic Engineering Universiti Tun Hussein Onn Malaysia Johor Malaysia Nanotechnology and Integrated Bio-Engineering Centre University of Ulster UK

this paper proposes a wireless communication system for secure transmission of data. Bluetooth is used as the wireless communication medium due to its low-cost and low-power consumption features. Advanced encryption standard (AES) protocol is implemented for the security reason over Bluetooth stack. RC10 prototyping board with Xilinx XC3S1500L-4-FG320 device has been used for the hardware evaluation of the system design. the system is configured to capture frames in real-time from the on-board OminiVision 9650 CMOS camera and transmit these frames securely via Bluetooth's connectivity. On reception, the images are decrypted and displayed on the external monitor. the design has also been demonstrated for edge detection over the wireless communication channel. the overall design is evaluated in terms of resource utilisation and maximum operating frequency.

关键词： field programmable gate arrays Encryption Table lookup Receivers Pixel Bluetooth arrays

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Design space exploration of throughput-optimized arrays from recurrence abstractions (abstract only) 10

Design space exploration of throughput-optimized arrays from...

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Proceedings of the 18th annual acm/sigda international symposium on field programmable gate arrays

作者： Arpith C. Jacob Jeremy D. Buhler Roger D. Chamberlain Washington University in St. Louis St. Louis MO USA

ISBN: (纸本)9781605589114

Many compute-bound software applications have seen order-of-magnitude speedups using application-specific accelerators built on specialized architectures such as field-programmable gate arrays. these architectures are particularly good at implementing systems of recurrence equations realized as systolic arrays. We pursue high-level synthesis tools for recurrence equations that can search the space of possible parallel array designs to optimize various design criteria. Most existing approaches produce an array that is latency-space optimal. We target applications that operate on a large collection of small inputs, e.g. a database of biological sequences. For these applications, overall throughput, rather than latency per input, is the most important measure of *** this work we introduce a new design space exploration procedure to optimize throughput of a systolic array subject to area and bandwidth constraints of an FPGA device. We show that the throughput of an array is dependent on the maximum number of lattice points executed by any processor in the array, which is determined solely by the array's projection vector. We describe a bounded search process to find throughput-optimized projection vectors, discovering a range of array designs that are optimal for inputs of various *** have written a tool in C++ that accepts recurrence descriptions and produces throughput-optimized array mappings. We have applied our technique to the banded Smith-Waterman and Nussinov RNA folding algorithms, and present novel arrays that are 4-33x and 2-14x faster, respectively, than the currently-used latency-optimized array.

关键词： dynamic programming systolic array throughput optimization fpga recurrences

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A Generic VHDL Template for 2D Stencil Code Applications on FPGAs

A Generic VHDL Template for 2D Stencil Code Applications on ...

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IEEE international symposium on Object/Component/Service-Oriented Real-Time Distributed Computing Workshops (ISORCW)

作者： Michael Schmidt Marc Reichenbach Dietmar Fey Department Computer Science Chair of Computer Architecture Friedrich-Alexander-Universitat Erlangen-Nuremberg Erlangen-Nuremberg Germany

the efficient realization of self-organizing systems based on 2D stencil code applications, like our developed Marching Pixel algorithms, is a great challenge. they are data-intensive and also computational-intensive, because often a high number of iterations is required. FPGAs are predestined for the realization of these algorithms. they are very flexible, allow a scalable parallel processing and have a moderate power consumption, even in high-performance versions. therefore, FPGAs are highly qualified to make these applications also real-time capable. Our goal was to implement an efficient parameterizable buffering and parallel processing scheme for such operations in FPGAs, to process them as fast as possible. We developed a generic VHDL template which allows a scalable parallelization and pipelining of 2D stencil code applications in relation to application and hardware constraints.

关键词： Computer architecture Microprocessors field programmable gate arrays Pipeline processing Clocks Bandwidth Real time systems

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