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A run-time word-level reconfigurable coarse-grain functional unit for a VLIW processor

A run-time word-level reconfigurable coarse-grain functional...

引用

international symposium on System Synthesis

作者： N.G. Busa C.R. Sala Philips Research Laboratories Eindhoven Netherlands S.A. Design Division Sony Espana Barcelona Spain

Nowadays, new DSP applications are offering combined and flexible multimedia and telecom services. VLIW processor architectures, which include dedicated but inflexible functional units, are usually tuned to a single specific application. In order to accelerate a wide range of applications, we propose a VLIW processor containing a novel run-time reconfigurable functional unit (RC-FU). Only a few hundred bits and few cycles are necessary to configure a new coarse-grain operation on the RC-FU unit. After reconfiguring its internal datapath and microprogram, the RC-FU can execute a number of look-alike DSP functions, such as 8-point DCT or 4-point FFT. the RC-FU itself is a VLIW processor and the configuration contexts are generated using a high-level synthesis tool. the proposed RC-FU provides high processing power and can be efficiently tuned to the requirements of a variety of DSP applications.

关键词： Runtime VLIW Computer architecture Acceleration Digital signal processing Delay Computer applications field programmable gate arrays Adders Hardware

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System-level design of IEEE1394 bus segment bridge

System-level design of IEEE1394 bus segment bridge

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international symposium on System Synthesis

作者： H. Yamamoto K. Chikamura A. Shigiya K. Tsujino T. Izumi T. Onoye Y. Nakamura Department Communications and Computer Engineering Kyoto University Kyoto Japan Kyoto Daigaku Kyoto JP Dept. Commun. & Comput. Eng. Kyoto Univ. Japan

A system simulation environment is constructed dedicatedly for IEEE1394 high-speed digital communication. In this environment, various network transactions inherent in communication systems are taken into account for system simulation, which is indispensable to enable IP (Intellectual Property)-based design of the systems. By using the proposed environment, system-level design of IEEE1394 link layer controller and bus segment bridge is achieved with great ability of network transactions as well as connectivities with physical layer chips. Functionalities of the designed bus segment bridge has been verified according to its FPGA implementation.

关键词： System-level design Bridges Physical layer Hardware design languages Network interfaces Protocols Discrete event simulation Control systems field programmable gate arrays System-on-a-chip

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Building management system based on image sensor

Building management system based on image sensor

引用

international symposium for Design and Technology of Electronics Packages (SIITME)

作者： Septimiu Pop Dan Pitica Ioan Ciascai Applied Electronics Department Technical University of Cluj Napoca Cluj-Napoca Romania

Physical parameters measures in activity of building management have slow variations. Some of parameters measures are temperature, pressure, movement of some building element. Taking in consideration this hypothesis the measurement system rate acquisition is low. the central unit can be a low speed programmable integrated circuit (IC) like a microcontroller. the low cost and low power consumption of image sensors and the possibility to be ease handled in measurements circuits, recommends the image sensors to be used in building managements. the linear image sensor is high speed device and is used for position detecting. To explore such application in this paper is designed and prototyped an experimental system measurement. the central unit of experimental measurement device is used a FPGA. Image sensor output is an analog voltage; this is easy interconnected with a high speed ADC. the operation frequency of acquisition frequency is established by light integration time. the expose time is computed in concordance with light intensity. the usual operation frequency of FPGA is 50MHz, implementing a soft clock divider the work frequency can be adjusted in same way to not saturate de sensor. the soft application for data acquisition and data analyze are developed in LabView FPGA and, LabView.

关键词： Image sensors Integrated circuit measurements field programmable gate arrays Power system management Temperature measurement Frequency conversion Pressure measurement Temperature sensors Microcontrollers Costs

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Implementations of real-time data intensive applications on PIM-based multiprocessor systems

Implementations of real-time data intensive applications on ...

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international symposium on Parallel and Distributed Processing (IPDPS)

作者： Jinwoo Suh Ming Zhu Changping Li S.P. Crago S.F. Shank R.H. Chau W.J. Mazur R. Pancoast Information Sciences Institute University of Southern California Arlington VA USA George Mason University Fairfax VA USA Lockheed Martin Naval Electronics and Surveillance Systems-Moorestown Moorestown NJ USA

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the cost of an abstraction layer on FPGA devices for software radio applications

The cost of an abstraction layer on FPGA devices for softwar...

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IEEE international symposium on Personal, Indoor and Mobile Radio Communications (PIMRC)

作者： X. Reves V. Marojevic A. Gelonch R. Ferrus Universitat Politecnica de Catalunya Barcelona Spain

Software radio applications require a framework to develop and deploy applications, especially those related to radio infrastructure. It is interesting that a given application may be executed on any software radio. But, since hardware platforms used in this context will have multiple architectures and devices, a software layer to make applications independent from hardware is mandatory. Ad-hoc software for a given hardware platform may produce the best software performance. Conversely, when software is not targeted to any concrete platform the lost of performance may be excessive and the overhead introduced by any platform-dependent library could become intolerable. In this paper the resource utilization of a software radio application using a simple hardware abstraction layer is studied and compared to an ad-hoc implementation to make an assessment of the introduced overhead. the particularity of the hardware abstraction layer is that it runs on a platform which only processors are FPGA devices.

关键词： Costs field programmable gate arrays Software radio Application software Hardware Software performance Computer architecture Concrete Software libraries Resource management

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Application-oriented SEU sensitiveness analysis of Atmel rad-hard FPGAs

Application-oriented SEU sensitiveness analysis of Atmel rad...

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IEEE symposium on On-Line Testing (IOLTS)

作者： N. Battezzati F. Decuzzi M. Violante M. Briet Politecnico di Turino Italy Atmel Corporation USA

Radiation-hardened-by-design (RHBD) SRAM-based FPGAs will play a crucial role in providing new generations of satellites with reliable in-flight reconfiguration ability, which is mandatory to enable the successful use of configurable computing in space. RHBD SRAM-based FPGAs sensitiveness against ionizing radiation is normally evaluated resorting to radiation testing, which provides the device cross-section. However, as a matter of fact, applications implemented on such devices use only a portion of the available resources, and the corresponding configuration memory. As a result, application-oriented sensitiveness analysis tools are needed that, by analyzing how the FPGA resources are actually used by a given application, produce application cross-section that is a reliability figure more accurate than device cross section. this paper presents a novel application-oriented sensitiveness analysis tool we are developing for the new generation of SRAM-based FPGAs from Atmel: the ATF280E.

关键词： Radiation hardening field programmable gate arrays Robustness Aerospace electronics Redundancy Ionizing radiation Space technology Costs Satellites Testing

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On-line characterization and reconfiguration for single event upset variations

On-line characterization and reconfiguration for single even...

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IEEE symposium on On-Line Testing (IOLTS)

作者： Kenneth M. Zick John P. Hayes Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI USA

the amount of physical variation among electronic components on a die is increasing rapidly. there is a need for a better understanding of variations in transient fault susceptibility, and for methods of on-line adaptation to such variations. We address three key research questions in this area. First, we investigate accelerated characterization of individual latch susceptibilities. We find that on the order of 10 upsets per latch must be observed for variations to be adequately characterized. Second, we propose a method of on-line hardware reconfiguration using incremental place-and-route on FPGAs. Surprisingly, we find that highly localized place-and-route changes (e.g. restricted to groups of 8 flip-flops) are sufficient for realizing most of the possible benefits. Lastly, we quantify potential improvements in system-level soft error rates via Monte Carlo simulation experiments. the study highlights both what is required for and what can be gained by on-line adaptation.

关键词： Single event upset Hardware field programmable gate arrays Latches Flip-flops Error analysis threshold voltage Single event transient Computer architecture Laboratories

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Evaluating large grain TMR and selective partial reconfiguration for soft error mitigation in SRAM-based FPGAs

Evaluating large grain TMR and selective partial reconfigura...

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IEEE symposium on On-Line Testing (IOLTS)

作者： Jose Rodrigo Azambuja Fernando Sousa Lucas Rosa Fernanda Lima Kastensmidt Instituto de Informática Universidade Federal do Rio Grande do Sul Porto Alegre Rio Grande do Sul Brazil

this paper presents an innovative method that allows the use of dynamic partial reconfiguration combined with triple modular redundancy (TMR) in SRAM-based FPGAs fault-tolerant designs. the method combines large grain TMR with special voters capable of signalizing the faulty module and check point states that allow the sequential synchronization of the recovered module with the Xilinx TMR (XTMR) approach. As a result, only the faulty domain is reconfigured, minimizing time and energy spent in the process. In addition, the use of checkpoint states avoids system downtime, since the synchronization of the recovered module is performed while the others are kept running. Experimental results show that the method has a reduced fault recovery time compared to the standard TMR implementation, maintaining the compatible area overhead and performance.

关键词： field programmable gate arrays Circuit faults Integrated circuit reliability Routing Redundancy Frequency synchronization Voltage Protection Helium Electronics industry

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Hardware/software Co-design of NLMS adaptive filters on FPGA

Hardware/software Co-design of NLMS adaptive filters on FPGA

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IEEE international symposium on Consumer Electronics (ISCE)

作者： De-Sheng Chen Po-Yu Chen Yi-Wen Wang Department of Computer Science and Information Engineering Feng Chia University FCU Taichung Taiwan

the NLMS adaptive filter is an important component of many DSP systems including acoustic echo cancellers and channel equalizers. In real-time applications, such filters often require dedicated hardware to meet the timing requirements. Modern FPGAs fulfill the above demand for its excellent flexibility and performance. this paper proposes two different architectures for implementing an NLMS adaptive filtering algorithm, using a 32 bit fixed-point arithmetic representation, on FPGA. these architectures are implemented using the Altera Cyclone II FPGA DE2-70 development board. A pure software implementation of the algorithm is first proposed using NIOS II embedded RISC processor. An FIR filter core is then proposed to implement a HW/SW Co-design architecture with the existing embedded processor. A comparison is made between the two alternative architectures for performance and area usage. Results show a significant improvement in execution time required when implementing with HW/SW Co-design over a pure software implementation.

关键词： Adaptive filters field programmable gate arrays Software Finite impulse response filter Computer architecture Hardware Filtering algorithms

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A mm Wave solution to provide wireless Augmented Reality in classrooms

A mm Wave solution to provide wireless Augmented Reality in ...

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international symposium on Wireless Communication Systems (ISWCS)

作者： Rodolfo Gomes Luís Sismeiro Carlos Ribeiro Manuel G. Sanchéz Akram Hammoudeh Rafael F. S. Caldeirinha University of South Wales School of Engineering Treforest United Kingdom Dept. Teoria do Sinal e Comunicacions Universidade de Vigo Vigo Spain Polytechnic Institute of Leiria Leiria Portugal

this paper presents a very high throughput wireless data transmission solution for Augmented Reality (AR) Head Mounted Devices (HMDs) in the 60 GHz band. Its feasibility is assessed in an Orthogonal Frequency Division Multiplexing (OFDM) downlink communication towards five User Equipment (UE) devices, placed at different locations inside an indoor classroom environment scenario. Key Performance Indicators (KPIs) as Error Vector Magnitude (EVM), Signal-to-Noise Ratio (SNR), and path loss are considered for Quality of Service (QoS) assessment. Experimental results demonstrate the reliability of the proposed mmWave system, where a data rate of 312.5 Mbps is achieved over distances of 1, 2.4 and 4.1 m, regardless the UE position.

关键词： Wireless communication OFDM Baseband field programmable gate arrays Signal to noise ratio Quality of service Prototypes

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