检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

265 篇 会议
28 篇 期刊文献

馆藏范围

293 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

229 篇 工学
- 218 篇 计算机科学与技术...
- 126 篇 软件工程
- 100 篇 电子科学与技术（可...
- 70 篇 电气工程
- 31 篇 信息与通信工程
- 12 篇 动力工程及工程热...
- 11 篇 机械工程
- 11 篇 控制科学与工程
- 6 篇 土木工程
- 6 篇 生物工程
- 5 篇 建筑学
- 4 篇 仪器科学与技术
- 4 篇 冶金工程
- 4 篇 生物医学工程（可授...
- 2 篇 材料科学与工程（可...
- 2 篇 化学工程与技术
- 1 篇 纺织科学与工程
- 1 篇 农业工程
93 篇 理学
- 74 篇 数学
- 13 篇 物理学
- 9 篇 统计学（可授理学、...
- 7 篇 生物学
- 5 篇 系统科学
- 1 篇 化学
18 篇 管理学
- 15 篇 管理科学与工程(可...
- 8 篇 工商管理
- 3 篇 图书情报与档案管...
4 篇 经济学
- 4 篇 应用经济学
3 篇 教育学
- 3 篇 教育学
1 篇 法学
- 1 篇 社会学
1 篇 农学
1 篇 医学

主题

155 篇 field programmab...
79 篇 field programmab...
22 篇 hardware
13 篇 computer archite...
7 篇 routing
7 篇 costs
7 篇 clocks
7 篇 delay
6 篇 fpga
5 篇 real time system...
5 篇 switches
5 篇 circuit testing
5 篇 circuits
5 篇 field-programmab...
4 篇 table lookup
4 篇 programmable log...
4 篇 fpgas
4 篇 application soft...
4 篇 signal processin...
4 篇 reconfigurable l...

机构

4 篇 univ british col...
4 篇 univ of toronto
3 篇 univ of toronto ...
3 篇 northwestern uni...
3 篇 computer science...
3 篇 altera corporati...
3 篇 intel corporatio...
2 篇 department of ee...
2 篇 politecn torino ...
2 篇 department of el...
2 篇 microsemi corp s...
2 篇 imperial college...
2 篇 university of br...
2 篇 ustc dept comp s...
2 篇 univ hong kong d...
2 篇 univ of californ...
2 篇 information scie...
2 篇 univ calif berke...
2 篇 edward s. rogers...
2 篇 univ of californ...

作者

11 篇 rose jonathan
8 篇 wawrzynek john
7 篇 cong jason
6 篇 hauck scott
5 篇 wilton steven j....
5 篇 betz vaughn
4 篇 dehon andre
4 篇 wilton steven j....
3 篇 ienne paolo
3 篇 wong d.f.
3 篇 kent kenneth b.
3 篇 li fei
3 篇 prasanna viktor ...
3 篇 mishchenko alan
3 篇 brayton robert
3 篇 chow paul
3 篇 brisk philip
3 篇 parandeh-afshar ...
2 篇 li xi
2 篇 sun fan

语言

293 篇 英文

检索条件"任意字段=15th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays"

共 293 条记录，以下是281-290 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Controller estimation for FPGA target architectures during high-level synthesis

Controller estimation for FPGA target architectures during h...

引用

international symposium on System Synthesis

作者： C. Menn O. Bringmann W. Rosenstiel FZI Forschungszentrum informatik Karlsruhe Germany Universität Tubingen Tubingen Germany

In existing synthesis systems, the influence of the area and delay of the controller is not or not sufficiently taken into account. But the controller can have a big influence, especially, if a certain data-path realization requires a huge number of states and/or control signals. this paper presents a new approach on controller estimation during high-level synthesis for FPGA-based target architectures. the estimator, presented in this paper can be invoked after or during every synthesis-step, i.e. allocation, scheduling and binding, respectively. By considering the controller influence on the overall area of a design, design space exploration can be made more accurate and less error prone. We present an approach for estimating area of the controller based on information which are easily accessible during each step of highlevel synthesis, so no explicit description of the controller, which usually will be generated after the binding, is necessary. this is particularly valuable in the allocation phase, where intensive design space explorations have to be done, based on fast and accurate estimates.

关键词： field programmable gate arrays High level synthesis Delay Signal synthesis Control system synthesis Error correction Space exploration Phase estimation Hardware Design engineering

来源：评论

学校读者我要写书评

暂无评论

Electrical Design and Characterization Methodologies Applied in the Development of FlexBench, a Rapid Prototyping Equipment

Electrical Design and Characterization Methodologies Applied...

引用

15th international Zurich symposium and Technical Exposition on Electromagnetic Compatibility

作者： Fabio De Pieri Mauro Ferloni Roberto Gaio Riccardo Gemelli Maurizio Grassi Claudio Meani Marco Pavesi Viscardo Costa (Italtel S.p.A.) Via R. Romoli 20019 Settimo Milanese (MI) Italy

ISBN: (纸本)9781509031979

this paper will address the methodology followed in Italtel to design a Rapid Prototype Equipment (RPE), named FlexBench™, well suitable to perform modular register transfer level (RTL) prototyping. this technique is used to verify System on Chip (SoC) netlist with high operating clock frequencies, near enough to the real clock frequency of the design to be verified. At Italtel SpA, in the frame of an IST program, we and our partners have developed a method to improve the system verification confidence through high-speed register transfer level (RTL) prototyping using FPGA components (Virtex™ family from Xilinx was mainly used) to implement custom logic ([1], [2], [3], and [4]). Here we will discuss mainly the Physical Design and Signal Integrity issues we had to face to guarantee the high performances required by the system.

关键词： field programmable gate arrays Register transfer level Topology Resistors Layout Connectors Receivers Clocks Sockets Reflection

来源：评论

学校读者我要写书评

暂无评论

A common FPGA based synchronizer architecture for Hiperlan/2 and IEEE 802.11a WLAN systems

A common FPGA based synchronizer architecture for Hiperlan/2...

引用

IEEE international symposium on Personal, Indoor and Mobile Radio Communications (PIMRC)

作者： M.J. Canet F. Vicedo V. Almenar J. Valls E.R. De Lima Dpto Electronica Universitat Politécnica de Valéncia Gandia Spain Departmento Física y Arquitectura Computadores Universitat Miguel Hernández Elche Spain Departmento Comunicaciones Universitat Politécnica de Valéncia Gandia Spain

this paper deals with the design and implementation of a frame, time and frequency synchronizer for both Hiperlan/2 and IEEE 802.11a WLAN standards. In a packet oriented system, to perform a quick and correct synchronization it is critical to avoid severe bit error rate degradation. So, the design of this subsystem is one of the most challenging tasks to be done in the implementation of a transceiver. In this paper we give practical solutions to the hardware design problems that arise when the synchronization algorithm is turned into a digital circuit. We evaluate the fixed-point realization of the synchronization algorithm and introduce some simplifications to reduce, as much as possible, the cost in area of the circuit without losing its performance.

关键词： field programmable gate arrays Wireless LAN Frequency synchronization Bit error rate Degradation Transceivers Hardware Algorithm design and analysis Digital circuits Costs

来源：评论

学校读者我要写书评

暂无评论

An effective fast and small-area parallel-pipeline architecture for OTM-convolutional encoders

An effective fast and small-area parallel-pipeline architect...

引用

IEEE symposium on On-Line Testing (IOLTS)

作者： Houssein Jaber Fabrice Monteiro Abbas Dandache LICM Laboratory University of Paul Verlaine-Metz Metz France

With the ever increasing data throughputs required by communication application, there is an actual need for new effective architectures (small area and high speed) for circuit parts dedicated to error detecting/correcting coding (EDC/ECC). In this paper, we propose a new parallel-pipeline design scheme for convolution encoders that meets these requisites. this approach apply both to the OTM (One To Many) and the MTO (Many To One) encoder variants. Here, we will focus only on the OTM case to prove the effectiveness of this new architecture. In order to evaluate the complexity/performance tradeoff and validate the architecture, several encoders have been implemented on FPGA devices of the Altera Stratix II family corresponding to different convolutional codes and parallelization levels. It is obvious from the experimental results the new architecture outperforms the former ones, including those proposed by us in for OTM and MTO. Indeed, similar bit rates have been achieved with noticeable area consumption reduction (up to 8.10 Gbits/s achieved with a 58% smaller circuit in the case of 32-bit parallel implementations).

关键词： Convolutional codes throughput Decoding Forward error correction Convolution Communication systems Architecture Circuits Error correction codes field programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

High Speed Dynamic Partial Reconfiguration for Real Time Multimedia Signal Processing

High Speed Dynamic Partial Reconfiguration for Real Time Mul...

引用

Euromicro symposium on Digital System Design

作者： S. Bhandari S. Subbaraman S. Pujari F. Cancare F. Bruschi M.D. Santambrogio P.R. Grassi Department of Microelectronics and VLSI Design International Institute of Information Technology Pune India Department of Electronics Walchand College of Engineering Sangli India Sambalpur University Institute of Information Technology Sambalpur India Dipartimento di Elettronica e Informazione Politecnico di Milano Milano Italy Computer Science and Artificial Intelligence Laboratory MIT Milano USA

the use of field programmable gate Array (FPGA) based System on Chip (SoC) is a promising approach in Multimedia applications. In SoC, computationally intensive tasks are off-loaded to the hardware logic. A feature introduced with new FPGA devices, Dynamic Partial Reconfiguration (DPR) is suitable to change this hardware logic when needed and while the rest of the system continues its functioning. As the applications running on hardware logic are real-time and computationally intensive, in order to make use of DPR to change the hardware logic, the efficiency of the DPR process is crucial. this paper describes how a FPGA-based Multimedia Application (Audio-Video filtering), benefits from dynamic partial reconfiguration and a custom DPR controller: the Speed Efficient Dynamic Partial Reconfiguration Controller (SEDPRC). Experimental results have shown that the novel controller brings benefits to the reconfiguration time. Enhancements in reconfiguration throughput up to a 55× factor are achieved.

关键词： field programmable gate arrays Hardware Program processors Streaming media System-on-a-chip Real-time systems Multimedia communication

来源：评论

学校读者我要写书评

暂无评论

Efficient tiling patterns for reconfigurable gate arrays 08

Efficient tiling patterns for reconfigurable gate arrays

引用

Proceedings of the 16th international acm/sigda symposium on field programmable gate arrays

作者： Sumanta Chaudhuri Jean-Luc Danger Philippe Hoogvorst Sylvain Guilley ENST Paris France

ISBN: (纸本)9781595939340

this article does a purely mathematical analysis based on generic models, and the idea is to investigate the possibility of using tiling patterns other than Manhattan grid in FPGAs. the goal of our research is to evolve FPGA architectures with advances in technology, and specifically better utilization of available interconnect layers. We propose a method to evaluate tiling patterns based on the first principles ( i.e Rent's Rule, Donath's result, equivalence of wire flux and wire length). We show that, use of tiling patterns formed with higher order polygons can improve the speed and area performances of an FPGA. this gain is highly dependent on depopulation schemes and other parameters. However for generic tiling patterns with crossbar switchboxes there is a 22% gain in area for the hexagonal tiling pattern, and a 30% gain in area for the octagonal tiling pattern. Moreover the average interconnect length is around 15% lesser for hexagonal and 31% lesser for the octagonal tiling compared to square tiling. We can expect a proportional increase in speed. We also present a comparative plot of total interconnect lengths for these tiling patterns and the hierarchical gate arraysthe physical realizability of these tiling patterns in CMOS are to be investigated. We present a layout scheme for both hexagonal and octagonal FPGAs. To our knowledge standard processes support 45° metal lines, whereas 60° lines can be etched using non-standard processes. We must keep in mind, that in practice one must use some sort of depopulation and staggering scheme, and these results provide only an idea of gains that can be achieved. the actual interconnect structure is of course dependent on several factors (i.e available interconnect layers, difficulty of fabrication, required speed/area, evolution of CMOS technology etc). Our future research direction will be to choose an efficient interconnect strategy based on this and previous researches, as well as experimental results

关键词： tiling interconnect FPGA hexagonal octagonal

来源：评论

学校读者我要写书评

暂无评论

Composite Lightweight Authenticated Encryption Based on LED Block Cipher and PHOTON Hash Function for IoT Devices

Composite Lightweight Authenticated Encryption Based on LED ...

引用

IEEE international symposium on Embedded Multicore Socs (MCSoC)

作者： Mohammed Al-Shatari Fawnizu Azmadi Hussin Azrina Abd Aziz Mohd Saufy Rohmad Xuan-Tu Tran Department of Electrical and Electronic Engineering Universiti Teknologi Petronas Seri Iskandar Perak Malaysia Faculty of Electrical Engineering Universiti Teknologi MARA Shah Alam Selangor Malaysia VNU Information Technology Institute Vietnam National University Hanoi Vietnam

ISBN: (纸本)9781665465007

IoT devices are being used in different environments recently. they are mostly resource-constrained, and therefore, their data security is crucial. Several lightweight cryptographic primitives were proposed to overcome the limitations of the devices while maintaining moderate security levels. Such primitives provide either encryption or authentication. the encryption must be authenticated by a Message Authentication Code (MA C) or hash function for better overall security. therefore, an architecture of integrated lightweight authenticated encryption (AE) based on LED block cipher and PHOTON hash function is presented. LED and PHOTON architectures were combined while exploiting area-performance trade-offs and utilizing the shared internal functions. the architecture is designed in Verilog HDL, synthesized in Altera Quartus II and simulated on field programmable gate Array (FPGA) devices. the individual design of LED utilizes 357 logic elements (LE) and PHOTON utilizes 852 LE resulting in a total of 1209 LE. the logic utilization of the proposed shared architecture is 1046 LE. the results reveal that 13.5 % reduction in logic area is achieved compared to the independent implementations of LED and PHOTON.

关键词： Hash functions Ciphers Multicore processing programmable logic arrays Light emitting diodes Encryption Internet of things

来源：评论

学校读者我要写书评

暂无评论

the role of FPGAs in a converged future with heterogeneous programmable processors: pre-conference workshop 11

The role of FPGAs in a converged future with heterogeneous p...

引用

Proceedings of the 19th acm/sigda international symposium on field programmable gate arrays

作者： Jonathan Rose Guy Lemieux University of Toronto Toronto ON Canada University of British Columbia Vancouver BC Canada

ISBN: (纸本)9781450305549

the battle of fixed function devices vs. programmable devices has been won by the programmables. the question facing us now is to determine what kinds of programmability to place on next generation systems/devices. Research and development on many applications has shown that different kinds of hardware and software programmability succeed for different application classes: powerful, singlethread-optimized CPUs continue to do very well for many applications; the General Purpose GPU is carving a niche in high throughput, parallel floating point codes in addition to its home turf of graphics; the FPGA is particularly good at variable bit-size computations and data steering, as well as parallel distributed control of networks. Future systems may well need all three types of these types of engines, and perhaps interesting mixtures of them. this is particularly true when we deal with the combined goals of optimizing cost, performance and *** this workshop, we will look to the future of the FPGA within these types of 'converged' programmable computing engines, and reflectively ask ourselves: What role can the FPGA play? What future applications in areas such as networking, mobile, and artificial intelligence can be driven by FPGAs? How do FPGAs fit into the architecture realm of CPUs, general purpose GPUs, and DSPs? How should the designer/programme express their intent in the most effective way possible? What are the requirements for a compilation and optimization environment that allow FPGAs to intermix within a heterogeneous and converged future?the intent of this workshop is to open a discussion on these questions. there will be a series of short, invited talks interspersed with free and open discussion.

关键词： heterogeneity reconfigurable computing high level programming models fpga heterogeneous computing systems signal processing dsp

来源：评论

学校读者我要写书评

暂无评论

A parallel real time implementation of stereo matching

A parallel real time implementation of stereo matching

引用

international symposium on Parallel and Distributed Processing (IPDPS)

作者： Hong Jeong Yuns Oh Department of Electronic and Computer Engineering Pohang University of Science and Technology Pohang South Korea

ISBN: (纸本)0769509908

We present a VLSI architecture and implementation for a highly parallel trellis-based stereo matching algorithm that has been previously presented by the authors. the algorithm obtains disparity (depth) information from a pair of images and has a complexity of O(N/sup 2/) for N pixel scan lines and O(N) operations can be performed in parallel. the architecture consists of a linear array of identical processing elements with only nearest-neighbor communication. the host provides pixel data to each end of the array during the forward iterations and reads the computed disparity during the backward iterations. the design is highly scalable. A 10 processor array that can handle 340 pixel scan lines has been fabricated using a 0.65 /spl mu/m CMOS process and has achieved 8 Mpixels/s throughput.

关键词： Artificial intelligence Stereo vision Pixel Real time systems Very large scale integration Computer architecture Navigation Digital signal processing chips Gold field programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

From high-level deep neural models to FPGAs 49

From high-level deep neural models to FPGAs

引用

IEEE/acm international symposium on Microarchitecture (MICRO)

作者： Hardik Sharma Jongse Park Divya Mahajan Emmanuel Amaro Joon Kyung Kim Chenkai Shao Asit Mishra Hadi Esmaeilzadeh Alternative Computing Technologies (ACT) Lab Georgia Institute of Technology Intel Corporation

ISBN: (纸本)9781509035090

Deep Neural Networks (DNNs) are compute-intensive learning models with growing applicability in a wide range of domains. FPGAs are an attractive choice for DNNs since they offer a programmable substrate for acceleration and are becoming available across different market segments. However, obtaining both performance and energy efficiency with FPGAs is a laborious task even for expert hardware designers. Furthermore, the large memory footprint of DNNs, coupled with the FPGAs' limited on-chip storage makes DNN acceleration using FPGAs more challenging. this work tackles these challenges by devising DnnWeaver, a framework that automatically generates a synthesizable accelerator for a given (DNN, FPGA) pair from a high-level specification in Caffe [1]. To achieve large benefits while preserving automation, DNNWEAVER generates accelerators using hand-optimized design templates. First, DnnWeaver translates a given high-level DNN specification to its novel ISA that represents a macro dataflow graph of the DNN. the DnnWeaver compiler is equipped with our optimization algorithm that tiles, schedules, and batches DNN operations to maximize data reuse and best utilize target FPGA's memory and other resources. the final result is a custom synthesizable accelerator that best matches the needs of the DNN while providing high performance and efficiency gains for the target FPGA. We use DnnWeaver to generate accelerators for a set of eight different DNN models and three different FPGAs, Xilinx Zynq, Altera Stratix V, and Altera Arria 10. We use hardware measurements to compare the generated accelerators to both multicore CPUs (ARM Cortex A15 and Xeon E3) and many-core GPUs (Tegra K1, GTX 650Ti, and Tesla K40). In comparison, the generated accelerators deliver superior performance and efficiency without requiring the programmers to participate in the arduous task of hardware design.

关键词： field programmable gate arrays Hardware Schedules Weaving Acceleration System-on-chip Computational modeling

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共30页 << < 21 22 23 24 25 26 27 28 29 30 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：