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Optical Mark Recognition Based on Image Processing Techniques for the Answer Sheets of the Colombian high-Stakes Tests 6th

Optical Mark Recognition Based on Image Processing Technique...

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6th Workshop on Engineering Applications (WEA)

作者： Espitia, Oscar Paez, Andres Mejia, Yuri Carrasco, Mario Gonzalez, Natalia Inst Colombiano Evaluac Educ ICFES Bogota Colombia Univ Antonio Narino Bogota Colombia

ISBN: (纸本)9783030310196;9783030310189

Optical Mark Recognition (OMR) is the process of electronically extracting intended data from marked fields, such as squares and bubbles fields, on printed forms. OMR is useful for applications in which large numbers of hand-filled forms need to be processed quickly and with a high degree of accuracy, for instance, reading the answer sheets of high-stakes tests. Nowadays, image processing techniques and advancement in computing could help to read the answer sheets, quickly and reducing operational costs. this work introduces a systematic procedure of image processing with two segmentation steps that conclude in the extraction and recognition of marks of answer sheets of Colombian high-Stakes Tests. Some preliminary results show that the accuracy is 99.83%, on average, in the first calibration stage, with 4 blocks of about 400 images, each one. A sampling procedure was performed to determine an adequate number of images to verify the performance of the method in the scenario of the application Saber 11 in the second semester of 2018. the conclusion of the exercise, with around 65.000 images, was 99.7% of accuracy, which was run in an 8 logical processors pc architecture, getting an average speed of 8 sheets per second. thus making it suitable for real applications or for performing a labeling process for deep learning training.

关键词： OMR Image processing high-Stakes Tests

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Multicore performance Engineering of Sparse Triangular Solves Using a Modified Roofline Model 30

Multicore Performance Engineering of Sparse Triangular Solve...

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30th International symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Wittmann, Markus Hager, Georg Janalik, Radim Lanser, Martin Klawonn, Axel Rheinbach, Oliver Schenk, Olaf Wellein, Gerhard Friedrich Alexander Univ Erlangen Reg Comp Ctr Erlangen Germany Univ Svizzera Italiana Fac Informat Inst Computat Sci Lugano Switzerland Univ Cologne Fac Math & Nat Sci Cologne Germany TU Bergakad Freiberg Fac Math & Comp Sci Freiberg Germany Friedrich Alexander Univ Dept Comp Sci Erlangen Germany

ISBN: (纸本)9781538677698

the Roofline model is widely used to visualize the performance of executed code together with the upper performance bounds given by the memory bandwidth and the processor peak performance. the model can thus provide an insightful visualization of bottlenecks. In this paper, we try to establish realistic bandwidth ceilings for the sparse triangular solve step of PARDISO, a leading sparse direct solver package, which is also part of the Intel MKL library. the performance of the forward and backward substitution process is analyzed and benchmarked for a representative set of sparse matrices on seven modern x86-type multicore architectures and the Knights Landing manycore architecture. It is shown how to accurately measure the necessary quantities also for threaded code, and the measurement approach, its validation, as well as limitations are discussed. Our modeling approach covers the serial and parallel execution phases, allowing for in-socket performance predictions.

关键词： Sparse matrices Particle separators Analytical models Computational modeling computer architecture Mathematical model Hardware

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Automated GPU Grid Geometry Selection for OpenMP Kernels 30

Automated GPU Grid Geometry Selection for OpenMP Kernels

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30th International symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Lloyd, Taylor Chikin, Artem Kedia, Sanket Jain, Dhruv Amaral, Jose Nelson Univ Alberta Edmonton AB Canada IIT Kharagpur Kharagpur W Bengal India

ISBN: (纸本)9781538677698

Modern supercomputers are increasingly using GPUs to improve performance per watt. Generating GPU code for target regions in OpenMP 4.0, or later versions, requires the selection of grid geometry to execute the GPU kernel. Existing industrial-strength compilers use a simple heuristic with arbitrary numbers that are constant for all kernels. After characterizing the relationship between region features, grid geometry and performance, we built a machine-learning model that successfully predicts a suitable geometry for such kernels and results in a performance improvement with a geometric mean of 5% across the benchmarks studied. However, this prediction is impractical because the overhead of the predictor is too high. A careful study of the results of the predictor allowed for the development of a practical low-overhead heuristic that resulted in a performance improvement of up to 7 times with a geometric mean of 25.9%. this paper describes the methodology to build the machine-learning model, and the practical low-overhead heuristic that can be used in industry-strong compilers.

关键词： GPUs heterogeneous computing OpenMP Machine Learning Grid Geometry

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NetForager: Geographically-Distributed Network performance Monitoring of Web Applications

NetForager: Geographically-Distributed Network Performance M...

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IEEE Annual computing and Communication Workshop and Conference (CCWC)

作者： Levent Dane Deniz Gurkan Computer Science University of Houston Houston TX USA Computer Engineering Technology University of Houston Houston TX USA

ISBN: (数字)9781728137834

ISBN: (纸本)9781728137841

Users connect to web applications for various content and services. In addition to the internet for the global user/ customer base, in today's enterprises, most business needs are also served by web applications. the application performance monitoring, testing, and maintenance is a considerable effort when serving customers and business needs. Ensuring a high level of user experience, isolation of network issues from application service performance, and providing a seamless experience independent of the proximity of the end user to the application server are some of the challenges faced in performance assurance efforts. In this respect, a reliable testing and monitoring mechanism for application performance is essential to business continuity. Furthermore, virtualization technologies along with extensive mobility adds tremendous challenge to collection of reliable and isolated data in conducting performance monitoring for any application. In this paper, we present the results of a comprehensive network traffic analysis conducted in a geographically distributed manner for over 15 representative web applications. We report that web applications utilize a wide range of bandwidth capacity due to location of the dynamic content and the time of day that the data may be retrieved. the variations create an inconsistent performance level in their network usage metrics. Our reported metrics such as the duration of complete web data transfer and bandwidth utilization can help enterprises, network engineers, and service providers in fine tuning their services. Our approach does not contain sensitive user information, allows for extensive configuration and customization of the framework, and finally, data capture processes have a built-in sharing mechanism for repeatable network experiments through a data collection description language.

关键词： Data collection Monitoring computer architecture IP networks Containers Servers Measurement

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Enabling Efficient Job Dispatching in Accelerator-extended Heterogeneous Systems with Unified Address Space 30

Enabling Efficient Job Dispatching in Accelerator-extended H...

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30th International symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Kornaros, Georgios Coppola, Marcello Technol Educ Inst Crete Dept Informat Engn Iraklion 71500 Crete Greece STMicroelectronics Grenoble France

ISBN: (纸本)9781538677698

In addition to GPUs that see increasingly widespread use for general-purpose computing, special-purpose accelerators are widely used for their high efficiency and low power consumption, attached to general-purpose CPUs, thus forming Heterogeneous System architectures (HSAs). this paper presents a new communication model for heterogeneous computing, that utilizes a unified memory space for CPUs and accelerators and removes the requirement for virtual-to-physical address translation through an I/O Memory Management Unit (IOMMU), thus making stronger the adoption of Heterogeneous System architectures in SoCs that do not include an IOMMU but still representing a large number in real products. By exploiting user-level queuing, workload dispatching to specialized hardware accelerators allows the removal of drawbacks present when copying objects through using the operating system calls. Additionally, dispatching is structured to enable fixed-size packet management that hardware specialized logic accelerates. To also eliminate IOMMU performance loss and IOMMU management complexity, we propose direct accelerator data placement in contiguous space in system-memory, where, the dispatcher provides trasparent access to the accelerators and at the same time offers an easy abstraction in the programming layer for the application. We demonstrate dispatching rates that exceed ten thousand jobs per second implementing architectural support on a low-cost embedded System-on-Chip, bounded only by the computing capacity of the hardware accelerators.

关键词： Hardware Kernel Graphics processing units Dispatching computer architecture System-on-chip Runtime

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Balancing load of GPU subsystems to accelerate image reconstruction in parallel beam tomography 30

Balancing load of GPU subsystems to accelerate image reconst...

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30th International symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Chilingaryan, Suren Ametova, Evelina Kopmann, Andreas Mirone, Alessandro Karlsruhe Inst Technol Karlsruhe Germany Katholieke Univ Leuven Leuven Belgium ESRF Grenoble France

ISBN: (纸本)9781538677698

Synchrotron X-ray imaging is a powerful method to investigate internal structures down to the micro-and nanoscopic scale. Fast cameras recording thousands of frames per second allow time-resolved studies with a high temporal resolution. Fast image reconstruction is essential to provide the synchrotron instrumentation with the imaging information required to track and control the process under study. Traditionally Filtered Back Projection algorithm is used for tomographic reconstruction. In this article, we discuss how to implement the algorithm on nowadays GPGPU architectures efficiently. the key is to achieve balanced utilization of available GPU subsystems. We present two highly optimized algorithms to perform back projection on parallel hardware. One is relying on the texture engine to perform reconstruction, while another one utilizes the Core computational units of the GPU. Both methods outperform current state-of-the-art techniques found in the standard reconstructions codes significantly. Finally, we propose a hybrid approach combining both algorithms to better balance load between GPU subsystems. It further boosts the performance by about 30% on NVIDIA Pascal micro-architecture.

关键词： Graphics processing units Image reconstruction Engines computer architecture Open area test sites Tomography

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Automatic Ray-Tracer Cloud Offloading in OpenMP 30

Automatic Ray-Tracer Cloud Offloading in OpenMP

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30th International symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Mortatti, Matheus Yviquel, Herve Araujo, Guido Univ Campinas UNICAMP Inst Comp Campinas SP Brazil

ISBN: (纸本)9781538677698

Rendering an image from a 3D scene requires a large amount of computation which grows exponentially with the complexity of the scene (e.g. number of objects and light sources). With the increasing demand of high definition content, 3D designers need to use high-performance computer systems to keep the rendering time acceptable. Since owning computer clusters is expensive, designers usually rent computing power directly from cloud service providers (e.g. AWS and Azure). However, even though many cloud providers already propose dedicated rendering services, integrating them within the standard workflow of modeling softwares can become a complex and cumbersome task. It typically requires exporting the project from the design software, dealing with various access control mechanisms from different clouds to upload the project, and executing the rendering remotely through command-line. Offloading computation to the cloud is a technique which can considerably simplify such tasks. To achieve that, this paper uses an extension of OpenMP 4. X to eliminate any major interactions with the end-user, while minimizing the complexity of cloud integration and optimizing the design workflow. It applies such approach to a ray-tracing application, a simplified version of the engines used by professional 3D modeling software (e.g. Blender). It automatically offloads the rendering process from the user computer to computer cluster within the Microsoft Azure cloud, brings the resulting images back after the computation ends and displays them directly on the screen of the user computer, thus providing a transparent programming model and good speed-ups over local execution.

关键词： Cloud computing Rendering (computer graphics) Computational modeling Software three-dimensional displays Cameras Engines

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Parallel Multi-hop Routing Protocol for 5G Backhauling Network Using HPC Platform

Parallel Multi-hop Routing Protocol for 5G Backhauling Netwo...

引用

International Conference on computer Engineering and Systems

作者： Somaya A. Aboulrous Ali A. El-Moursy Mohamed Saad Amany Abdelsamea Salwa M. Nassar Hazem Abbas Computer and Systems Engineering Ain Shams University Cairo Egypt Computer Engineering University of Sharjah Sharjah UAE Electronics Research Institute Giza Egypt

ISBN: (数字)9780738105598

ISBN: (纸本)9781665405232

Fifth generation (5G) systems are considered as the future of telecommunications and data processing. 5G systems are envisaged to increase current network capacity by 1000-fold. In addition to increasing spectral efficiency and utilizing wider bandwidths, ultra network densification with wireless small cells is considered a significant capacity-enhancing method for meeting the ever-increasing demand of 5G data traffic requirements. the enormous amounts of data traffic generated in inter-small-cell 5G backhaul networks require efficient routing protocols to speed up the routing decisions, while ensuring high data rates, low latency, and low power consumption requirements. therefore, a parallel routing protocol is proposed to speed up routing decisions in 5G backhaul networks, using high performance computing (HPC). We explore the efficiency of utilizing HPC to manage and speed up the parallel routing protocol using different communication network sizes. Our numerical results indicate that our HPC implementation achieves a routing speed-up of 37× for large network size (2048).

关键词： Wireless communication 5G mobile communication Spectral efficiency Spread spectrum communication Routing Routing protocols Telecommunications

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ASNet: Introducing Approximate Hardware to high-Level Synthesis of Neural Networks

ASNet: Introducing Approximate Hardware to High-Level Synthe...

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International symposium on Multiple-Valued Logic

作者： Saman Froehlich Lucas Klemmer Daniel Große Rolf Drechsler DFKI GmbH and Group of Computer Architecture University of Bremen Germany

ISBN: (数字)9781728154060

ISBN: (纸本)9781728154077

Approximate computing is a design paradigm which makes use of error tolerance inherent to many applications in order to trade off accuracy for performance. One classic example for such an application is machine learning with Neural Networks (NNs). Recently, LeFlow, a high-Level Synthesis (HLS) flow for mapping Tensorflow NNs into hardware has been proposed. the main steps of LeFlow are to compile the Tensorflow models into the LLVM Intermediate Representation (IR), perform several transformations and feed the result into a HLS tool. In this work we take HLS-based NN synthesis one step further by integrating hardware approximation. To achieve this goal, we upgrade LeFlow such that (a) the user can specify hardware approximations, and (b) the user can analyze the impact of hardware approximation already at the SW level. Based on the exploration results which satisfy the NN quality expectations, we import the chosen approx. HW components into an extended version of the HLS tool to finally synthesize the NN to Verilog. the experimental evaluation demonstrates the advantages of our proposed ASNet for several NNs. Significant area reductions as well as improvements in operation frequency are achieved.

关键词： Artificial neural networks Tools Hardware design languages Generators Libraries Hardware Complexity theory

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high-performance Ensembles of Online Sequential Extreme Learning Machine for Regression and Time Series Forecasting 30

High-Performance Ensembles of Online Sequential Extreme Lear...

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30th International symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Grim, Luis Fernando L. Gradvohl, Andre Leon S. Univ Campinas FT UNICAMP Sch Technol Limeira SP Brazil Fed Inst Educ Sci & Technol Sao Paulo IFSP Piracicaba SP Brazil

ISBN: (纸本)9781538677698

Ensembles of Online Sequential Extreme Learning Machine algorithm are suitable for forecasting Data Streams with Concept Drifts. Nevertheless, data streams forecasting require high-performance implementations due to the high incoming samples rate. In this work, we proposed to tune-up three ensembles, which operates with the Online Sequential Extreme Learning Machine, using high-performance techniques. We reimplemented them in the C programming language with Intel MKL and MPI libraries. the Intel MKL provides functions that explore the multithread features in multicore CPUs, which expands the parallelism to multiprocessors architectures. the MPI allows us to parallelize tasks with distributed memory on several processes, which can be allocated within a single computational node, or spread over several nodes. In summary, our proposal consists of a two-level parallelization, where we allocated each ensemble model into an MPI process, and we parallelized the internal functions of each model in a set of threads through Intel MKL. thus, the objective of this work is to verify if our proposals provide a significant improvement in execution time when compared to the respective conventional serial approaches. For the experiments, we used a synthetic and a real dataset. Experimental results showed that, in general, the high-performance ensembles improve the execution time, when compared with its serial version, performing up to 10-fold faster.

关键词： high-performance computing Machine Learning Time Series Forecasting Regression Data Streams Concept Drift

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