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Combining Evolutionary Information and Sparse Bayesian Probability Model to Accurately Predict Self-interacting Proteins 15th

Combining Evolutionary Information and Sparse Bayesian Proba...

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15th International Conference on Intelligent computing, ICIC 2019

作者： Wang, Yan-Bin You, Zhu-Hong Yi, Hai-cheng Chen, Zhan-Heng Guo, Zhen-Hao Zheng, Kai University of Chinese Academy of Sciences Beijing100049 China Xinjiang Technical Institute of Physics and Chemistry Chinese Academy of Science Urumqi830011 China School of Computer Science and Technology China University of Mining and Technology Xuzhou China

ISBN: (纸本)9783030269685

Self-interacting proteins (SIPs) play a crucial role in investigation of various biochemical developments. In this work, a novel computational method was proposed for accelerating SIPs validation only using protein sequence. Firstly, the protein sequence was represented as Position-Specific Weight Matrix (PSWM) containing protein evolutionary information. then, we incorporated the Legendre Moment (LM) and Sparse Principal Component Analysis (SPCA) to extract essential and anti-noise evolutionary feature from the PSWM. Finally, we utilized robust Probabilistic Classification Vector Machine (PCVM) classifier to carry out prediction. In the cross-validated experiment, the proposed method exhibits high accuracy performance with 95.54% accuracy on *** dataset, which is a significant improvement compared to several competing SIPs predictors. the empirical test reveal that the proposed method can efficiently extracts salient features from protein sequences and accurately predict potential SIPs. © 2019, Springer Nature Switzerland AG.

关键词： Proteins

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ProFess: A Probabilistic Hybrid Main Memory Management Framework for high performance and Fairness 24

ProFess: A Probabilistic Hybrid Main Memory Management Frame...

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24th IEEE International symposium on high performance computer architecture (HPCA)

作者： Knyaginin, Dmitry Papaefstathiou, Vassilis Stenstrom, Per Chalmers Univ Technol Gothenburg Sweden FORTH ICS Iraklion Crete Greece

ISBN: (纸本)9781538636596

Non-Volatile Memory (NVM) technologies enable cost-effective hybrid main memories with two partitions: M1 (DRAM) and slower but larger M2 (NVM). this paper considers a flat migrating organization of hybrid memories. A challenging and open issue of managing such memories is to allocate M1 among co-running programs such that high fairness is achieved at the same time as high performance. this paper introduces ProFess: a Probabilistic hybrid main memory management Framework for high performance and fairness. It comprises: i) a Relative-Slowdown Monitor (RSM) that enables fair management by indicating which program suffers the most from competition for M1;and ii) a probabilistic Migration-Decision Mechanism (MDM) that unlocks high performance by realizing cost-benefit analysis that is individual for each pair of data blocks considered for migration. Within ProFess, RSM guides MDM towards high fairness. We show that for the multiprogrammed workloads evaluated, ProFess improves fairness by 15% (avg.;up to 29%), compared to the state-of-the-art, while outperforming it by 12% (avg.;up to 29%).

关键词： hybrid main memory flat migrating organization fairness performance hardware

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Memory Hierarchy for Web Search 24

Memory Hierarchy for Web Search

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24th IEEE International symposium on high performance computer architecture (HPCA)

作者： Ayers, Grant Ahn, Jung Ho Kozyrakis, Christos Ranganathan, Parthasarathy Stanford Univ Stanford CA 94305 USA Seoul Natl Univ Seoul South Korea Google Mountain View CA USA

ISBN: (纸本)9781538636596

Online data-intensive services, such as search, serve billions of users, utilize millions of cores, and comprise a significant and growing portion of datacenter-scale workloads. However, the complexity of these workloads and their proprietary nature has precluded detailed architectural evaluations and optimizations of processor design trade-offs. We present the first detailed study of the memory hierarchy for the largest commercial search engine today. We use a combination of measurements from longitudinal studies across tens of thousands of deployed servers, systematic microarchitectural evaluation on individual platforms, validated trace-driven simulation, and performance modeling - all driven by production workloads servicing real-world user requests. Our data quantifies significant differences between production search and benchmarks commonly used in the architecture community. We identify the memory hierarchy as an important opportunity for performance optimization, and present new insights pertaining to how search stresses the cache hierarchy, both for instructions and data. We show that, contrary to conventional wisdom, there is significant reuse of data that is not captured by current cache hierarchies, and discuss why this precludes state-of-the-art tiled and scale-out architectures. Based on these insights, we rethink a new cache hierarchy optimized for search that trades off the inefficient use of L3 cache transistors for higher-performance cores, and adds a latency-optimized on-package eDRAM L4 cache. Compared to state-of-the-art processors, our proposed design performs 27% to 38% better.

关键词： web search warehouse-scale computing memory systems

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Evaluating the performance and improving the usability of parallel and distributed Word Embeddings tools

Evaluating the performance and improving the usability of pa...

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Euromicro Conference on Parallel, Distributed and Network-Based Processing

作者： Matheus L. da Silva Vinícius Meyer Dionatrã F. Kirchoff F. S. Joaquim Neto Renata Vieira A. F. César De Rose Polytechnic School Pontifical Catholic University of Rio Grande do Sul (PUCRS) Porto Alegre RS Brazil

ISBN: (数字)9781728165820

ISBN: (纸本)9781728165837

the representation of words by means of vectors, also called Word Embeddings (WE), has been receiving great attention from the Natural Language Processing (NLP) field. WE models are able to express syntactic and semantic similarities, as well as relationships and contexts of words within a given corpus. Although the most popular implementations of WE algorithms present low scalability, there are new approaches that apply high-performance computing (HPC) techniques. this is an opportunity for an analysis of the main differences among the existing implementations, based on performance and scalability metrics. In this paper, we present a study which addresses resource utilization and performance aspects of known WE algorithms found in the literature. To improve scalability and usability we propose a wrapper library for local and remote execution environments that contains a set of optimizations such as the pWord2vec, pWord2vec MPI, Wang2vec and the original Word2vec algorithm. Utilizing these optimizations it is possible to achieve an average performance gain of 15x for multicores and 105x for multinodes compared to the original version. there is also a big reduction in the memory footprint compared to the most popular python versions.

关键词： Optimization Scalability Libraries Training Usability Natural language processing computer architecture

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Accelerate GPU Concurrent Kernel Execution by Mitigating Memory Pipeline Stalls 24

Accelerate GPU Concurrent Kernel Execution by Mitigating Mem...

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24th IEEE International symposium on high performance computer architecture (HPCA)

作者： Dai, Hongwen Lin, Zhen Li, Chao Zhao, Chen Wang, Fei Zheng, Nanning Zhou, Huiyang North Carolina State Univ Dept Elect & Comp Engn Raleigh NC 27695 USA Xi An Jiao Tong Univ Sch Elect & Informat Engn Xian Shaanxi Peoples R China

ISBN: (纸本)9781538636596

Following the advances in technology scaling, graphics processing units (GPUs) incorporate an increasing amount of computing resources and it becomes difficult for a single GPU kernel to fully utilize the vast GPU resources. One solution to improve resource utilization is concurrent kernel execution (CKE). Early CKE mainly targets the leftover resources. However, it fails to optimize the resource utilization and does not provide fairness among concurrent kernels. Spatial multitasking assigns a subset of streaming multiprocessors (SMs) to each kernel. Although achieving better fairness, the resource underutilization within an SM is not addressed. thus, intra-SM sharing has been proposed to issue thread blocks from different kernels to each SM. However, as shown in this study, the overall performance may be undermined in the intra-SM sharing schemes due to the severe interference among kernels. Specifically, as concurrent kernels share the memory subsystem, one kernel, even as computing-intensive, may starve from not being able to issue memory instructions in time. Besides, severe L1 D-cache thrashing and memory pipeline stalls caused by one kernel, especially a memory-intensive one, will impact other kernels, further hurting the overall performance. In this study, we investigate various approaches to overcome the aforementioned problems exposed in intra-SM sharing. We first highlight that cache partitioning techniques proposed for CPUs are not effective for GPUs. then we propose two approaches to reduce memory pipeline stalls. the first is to balance memory accesses of concurrent kernels. the second is to limit the number of inflight memory instructions issued from individual kernels. Our evaluation shows that the proposed schemes significantly improve the weighted speedup of two state-of-the-art intra-SM sharing schemes, Warped-Slicer and SMK, by 24.6% and 27.2% on average, respectively, with lightweight hardware overhead.

关键词： Kernel Graphics processing units Pipelines Instruction sets Resource management Benchmark testing computer architecture

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DM-SIRT: A Distributed Method for Multi-tilt Reconstruction in Electron Tomography 15th

DM-SIRT: A Distributed Method for Multi-tilt Reconstruction ...

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15th International symposium on Bioinformatics Research and Applications (ISBRA)

作者： Wang, Zihao Zhang, Jingrong Liu, Xintong Liu, Zhiyong Wan, Xiaohua Zhang, Fa Chinese Acad Sci Inst Comp Technol High Performance Comp Res Ctr Beijing 100190 Peoples R China Univ Chinese Acad Sci Beijing Peoples R China Beijing Inst Technol Sch Automat Beijing Peoples R China

ISBN: (纸本)9783030202422;9783030202415

the 'missing wedge' of single tilt in electron tomography introduces severely artifacts into the reconstructed results. To reduce the 'missing wedge' effect, a widely used method is 'multi-tilt reconstruction', which collects projections using multiple different axes. However, as the number of tilt series increases, its computing and memory costs also rises. While the demand to speed up its reconstruction procedure grows, the huge memory requirement from the 3D structure and strong data dependencies from projections heavily limit its parallelization. In our work, we present a new fully distributed multi-tilt reconstruction framework named DM-SIRT. To improve the parallelism of the reconstruction process and reduce the memory requirements of each process, we formulate the multi-tilt reconstruction as a consensus optimization problem and design a distributed multi-tilt SIRT algorithm. To improve the reconstruction resolution, we applied a multi-agent consensus equilibrium (MACE) with a new data division strategy. Experiments show that along with the visually and quantitatively improvement in resolution, DM-SIRT can acquire a 5.4x speedup ratio compared to the raw multi-tilt reconstruction version. It also has 87% decrease of memory overhead and 8 times more scalable than the raw reconstruction version.

关键词： Cryo-electron Tomography Parallel computing Consensus optimization Multi-tilt reconstruction TxBR

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high Precision, high performance FPGA Adders

High Precision, High Performance FPGA Adders

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Annual IEEE symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Martin Langhammer Bogdan Pasca Gregg Baeckler Intel Corporation

FPGAs are now being commonly used in the datacenter as smart Network Interface Cards (NICs), with cryptography as one of the strategic application areas. Public key cryptography algorithms in particular require arithmetic with thousands of bits of precision. Even an operation as simple as addition can be difficult for the FPGA when dealing with large integers, because of the high resource count and high latency needed to achieve usable performance levels with known methods. this paper examines the architecture and implementation of high-performance integer adders on FPGAs for widths ranging from 1024 to 8192 bits, in both single-instance and many-core chip-filling configurations. For chip-filling designs the routing impact of these wide busses are assessed, as they often have an impact outside the immediate locality of the structures. the architectures presented in this work show 1 to 2 orders magnitude reduction in the area-latency product over commonly used approaches. Routing congestion is managed, with near 100% logic efficiency (packing) for the adder function. performance for these largely automatically placed designs are approximately the same as for carefully floor-planned non-arithmetic applications. In one example design, we show a 2048 bit adder in 5021 ALMs, with a latency of 6 clock cycles, at 628 MHz in a Stratix 10 E-2 device.

关键词： Adders Field programmable gate arrays Routing Pipeline processing performance evaluation Pipelines computer architecture

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DUO: Exposing On-chip Redundancy to Rank-Level ECC for high Reliability 24

DUO: Exposing On-chip Redundancy to Rank-Level ECC for High ...

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24th IEEE International symposium on high performance computer architecture (HPCA)

作者： Gong, Seong-Lyong Kim, Jungrae Lym, Sangkug Sullivan, Michael David, Howard Erez, Mattan UT Austin Austin TX 78712 USA Microsoft Albuquerque NM USA NVIDIA Santa Clara CA USA Huawei Shenzhen Peoples R China

ISBN: (纸本)9781538636596

DRAM row and column sparing cannot efficiently tolerate the increasing inherent fault rate caused by continued process scaling. In-DRAM ECC (IECC), an appealing alternative to sparing, can resolve inherent faults without significant changes to DRAM, but it is inefficient for highly-reliable systems where rank-level ECC (RECC) is already used against operational faults. In addition, DRAM design in the near future (possibly as early as DDR5) may transfer data in longer bursts, which complicates high-reliability RECC due to fewer devices being used per rank and increased fault granularity. We propose dual use of on-chip redundancy (DUO), a mechanism that bypasses the IECC module and transfers on-chip redundancy to be used directly for RECC. Due to its increased redundancy budget, DUO enables a strong and novel RECC for highly-reliable systems, called DUO SDDC. the long codewords of DUO SDDC provide fundamentally higher detection and correction capabilities, and several novel secondary-correction techniques integrate together to further expand its correction capability. According to our evaluation results, DUO shows performance degradation on par with or better than IECC (average 2-3%), while consuming less DRAM energy than IECC (average 4-14% overheads). DUO provides higher reliability than either IECC or the state-of-the-art ECC technique. We show the robust reliability of DUO SDDC by comparing it to other ECC schemes using two different inherent fault-error models.

关键词： DRAM reliability scaling errors ECC

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Making Memristive Neural Network Accelerators Reliable 24

Making Memristive Neural Network Accelerators Reliable

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24th IEEE International symposium on high performance computer architecture (HPCA)

作者： Feinberg, Ben Wang, Shibo Ipek, Engin Univ Rochester Dept Elect & Comp Engn 601 Elmwood Ave Rochester NY 14627 USA Univ Rochester Dept Comp Sci Rochester NY 14627 USA

ISBN: (纸本)9781538636596

Deep neural networks (DNNs) have attracted substantial interest in recent years due to their superior performance on many classification and regression tasks as compared to other supervised learning models. DNNs often require a large amount of data movement, resulting in performance and energy overheads. One promising way to address this problem is to design an accelerator based on in-situ analog computing that leverages the fundamental electrical properties of memristive circuits to perform matrix-vector multiplication. Recent work on analog neural network accelerators has shown great potential in improving both the system performance and the energy efficiency. However, detecting and correcting the errors that occur during in-memory analog computation remains largely unexplored. the same electrical properties that provide the performance and energy improvements make these systems especially susceptible to errors, which can severely hurt the accuracy of the neural network accelerators. this paper examines a new error correction scheme for analog neural network accelerators based on arithmetic codes. the proposed scheme encodes the data through multiplication by an integer, which preserves addition operations through the distributive property. Error detection and correction are performed through a modulus operation and a correction table lookup. this basic scheme is further improved by data-aware encoding to exploit the state dependence of the errors, and by knowledge of how critical each portion of the computation is to overall system accuracy. By leveraging the observation that a physical row that contains fewer 1s is less susceptible to an error, the proposed scheme increases the effective error correction capability with less than 4.5% area and less than 4.7% energy overheads. When applied to a memristive DNN accelerator performing inference on the MNIST and ILSVRC-2012 datasets, the proposed technique reduces the respective misclassification rates by 1.5x and 1.

关键词： computer architecture Accelerator architectures

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Prediction of Plant lncRNA-Protein Interactions Using Sequence Information Based on Deep Learning 15th

Prediction of Plant lncRNA-Protein Interactions Using Sequen...

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15th International Conference on Intelligent computing, ICIC 2019

作者： Zhou, Haoran Luan, Yushi Wekesa, Jael Sanyanda Meng, Jun School of Computer Science and Technology Dalian University of Technology DalianLiaoning116024 China School of Bioengineering Dalian University of Technology DalianLiaoning116024 China

ISBN: (纸本)9783030267650

Plant long non-coding RNA (lncRNA) plays an important role in many biological processes, mainly through its interaction with RNA binding protein (RBP). To understand the function of lncRNA, a basic step is to determine which proteins are interacted with lncRNA. therefore, RBP can be predicted by computational approaches. However, the main challenge is that it is difficult to find interaction patterns or primitives. In this study, we propose a method based on sequences to predict plant lncRNA-protein interaction, namely PLRPI uses k-mer frequency feature for RNA and protein, stacked denoising autoencoder and gradient boosting decision tree to learn the hidden interaction between plant lncRNAs and proteins sequences. the experimental results show that PLRPI achieves good performance on the test datasets Ath948 and ZEA22133 based on lncRNA-protein interaction of Arabidopsis thaliana and Zea mays. Our method gets an accuracy of 90.4% on Ath948 and 82.6% on ZEA22133. PLRPI is also superior to other methods in some public RNA-protein interaction datasets. the result shows PLRPI has strong generalization ability and high robustness. It is an effective model for predicting plant lncRNA-protein interactions. © 2019, Springer Nature Switzerland AG.

关键词： Proteins

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