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15th symposium on computer architecture and high performance computing

作者： da Silva, AF Lobosco, M de Amorim, CL Univ Fed Rio de Janeiro COPPE BR-21945 Rio De Janeiro Brazil

ISBN: (纸本)0769520464

In this work, we propose a new distributed run-time environment, which we called cJava, that enables multithread Java applications to execute in clusters transparently. Our implementation of cJava supports the distributed shared memory (DSM) which required significant extensions to the original Java virtual machine (JVM). First, a distributed object manager was incorporated to the JVM's memory management subsystem for creating a global object space. Second, synchronized accesses to the global object space were extended so that they could use the lock() and unlock() primitives that cJava's DSM supports. third, cJava adapted the thread subsystem to enable remote creation and global monitors. Last, a subsystem for remote signaling was added to the original JVM. the main advantage of cJava is that it can execute existing multithread Java applications straightaway. Most importantly, our results of cJava's performance across several benchmarks show that cJava offers an efficient run-time system for executing transparently multithread Java applications in clusters.

关键词： Application software computer architecture Instruction sets Java Multiprocessing systems Programming profession Runtime Systems engineering and theory Virtual machining Yarn

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A modeling methodology and pre-run-time scheduling for embedded real-time software 15

A modeling methodology and pre-run-time scheduling for embed...

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15th symposium on computer architecture and high performance computing

作者： Barreto, R Maciel, P Cavalcante, S Univ Fed Amazonas UFAM DCC BR-69077000 Manaus Amazonas Brazil

ISBN: (纸本)0769520464

One of the most intricate problem in the synthesis of real-time systems is the scheduling. this paper presents a formal modeling methodology based on time Petri nets (TPN) and a framework for application-specific scheduler synthesis. Finding a feasible scheduling is not an easy task because this problem, in its general form, is NP-hard. the method proposed in this paper finds a scheduling, whether one exists, using state space exploration. the problem with this approach is the space size, which can be very large for medium to large systems. this paper shows how to minimize this problem using behavior restrictions at system modeling, and a partial-order reduction method. Additionally, the algorithm proposed for finding a feasible schedule uses a depth-first search based method. therefore, states are only generated if strictly necessary. It is verified through real-world experimental results that a schedule is found examining a reduced number of states.

关键词： Embedded computing Embedded software Modeling Petri nets Processor scheduling Real time systems Scheduling algorithm Space exploration State-space methods Timing

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A BSP/CGM algorithm for computing Euler tours in graphs 15

A BSP/CGM algorithm for computing Euler tours in graphs

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15th symposium on computer architecture and high performance computing

作者： Cáceres, EN Nasu, CY Univ Fed Mato Grosso Sul Campo Grande MS Brazil

ISBN: (纸本)0769520464

In this paper we describe a parallel algorithm using the BSP/CGM model (Bulk Synchronous Parallel/Coarse Grained Multicomputer) to obtain the Euler tours in graphs. It is based on the PRAM (Parallel Random Access Machine) algorithm by Caceres et al. For an input graph of n vertices and m edges, the algorithm requires local computation time of O((m + n)/p), O((m + n'p) memory and O(log p) communication rounds, where p is the number of processors. To our knowledge there are no other parallel algorithms under the coarse-grained models for the Euler tours in graphs. the proposed algorithm is implemented using MPI (Message Passing Interface) and the C language. the parallel program runs on a Beowulf with 66 nodes. the implementation results confirm the theoretical complexity results of the algorithm.

关键词： Bridges Cities and towns Data structures Graph theory Message passing Parallel algorithms Phase change random access memory Rivers Search methods User-generated content

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New parallel algorithms for frequent itemset mining in very large databases 15

New parallel algorithms for frequent itemset mining in very ...

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15th symposium on computer architecture and high performance computing

作者： Veloso, A Meira, W Parthasarathy, S Univ Fed Minas Gerais Dept Comp Sci Belo Horizonte MG Brazil

ISBN: (纸本)0769520464

Frequent itemset mining is a classic problem in data mining. It is a non-supervised process which concerns in finding frequent patterns (or itemsets) hidden in large volumes of data in order to produce compact summaries or models of the database. these models are typically used to generate association rules, but recently they have also been used in far reaching domains like e-commerce and bio-informatics. Because databases are increasing in terms of both dimension (number of attributes) and size (number of records), one of the main issues in a frequent itemset mining algorithm is the ability to analyze very large databases. Sequential algorithms do not have this ability, especially in terms of run-time performance, for such very large databases. therefore, we must rely on high performance parallel and distributed computing. We present new parallel algorithms for frequent itemset mining. their efficiency is proven through a series of experiments on different parallel environments, that range from shared-memory multiprocessors machines to a set of SMP clusters connected together through a high speed network. We also briefly discuss an application of our algorithms to the analysis of large databases collected by a Brazilian web portal.

关键词： Algorithm design and analysis Association rules Data analysis Data mining Databases Distributed computing high-speed networks Itemsets Parallel algorithms Runtime

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Finite difference simulations of the Navier-Stokes equations using parallel distributed computing 15

Finite difference simulations of the Navier-Stokes equations...

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15th symposium on computer architecture and high performance computing

作者： De Angeli, JP Valli, AMP Reis, NC De Souza, AF UFES Dept Informat BR-29060970 Vitoria ES Brazil

ISBN: (纸本)0769520464

this paper discusses the implementation of a numerical algorithm for simulating incompressible fluid flows based on the finite difference method and designed for parallel computing platforms with distributed-memory, particularly for clusters of workstations. the solution algorithm for the Navier-Stokes equations utilizes an explicit scheme for pressure and an implicit scheme for velocities, i.e., the velocity field at a new time step can be computed once the corresponding pressure is known. the parallel implementation is based on domain decomposition, where the original calculation domain is decomposed into several blocks, each of which given to a separate processing node. All nodes then execute computations in parallel, each node on its associated subdomain. the parallel computations include initialization, coefficient generation, linear solution on the sub-domain, and inter-node communication. the exchange of information across the sub-domains, or processors, is achieved using the message passing interface standard, MPI. the use of MPI ensures portability across different computing platforms ranging from massively parallel machines to clusters of workstations. the execution time and speed-up are evaluated through comparing the performance of different numbers of processors. the results indicate that the parallel code can significantly improve prediction capability and efficiency for large-scale simulations.

关键词： Clustering algorithms Computational modeling Concurrent computing Design methodology Distributed computing Finite difference methods Fluid flow Navier-Stokes equations Numerical simulation Workstations

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Adaptive compressed caching: Design and implementation 15

Adaptive compressed caching: Design and implementation

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15th symposium on computer architecture and high performance computing

作者： de Castro, RS do Lago, AP Da Silva, D Univ Sao Paulo Dept Comp Sci BR-05508 Sao Paulo Brazil

ISBN: (纸本)0769520464

In this paper, we reevaluate the use of adaptive compressed caching in order to improve system performance through reduction of accesses to the backing stores. We propose a new and simple adaptability policy that adjusts the compressed cache size on-the-fly, and evaluate a compressed caching system with this policy through an implementation in a widely used operating system, Linux. We also redesign compressed caching in order to provide performance improvements for all tested workloads and address the problems faced in previous works and implementations that led to non-conclusive results. Among these fundamental modifications, our compressed cache is the first one to also compress file cache pages, to adaptively disable compression of clean pages when necessary and to address applications with poor compressibility. We tested a system with our adaptive compressed cache under many applications and benchmarks, each one with different memory pressures. the results showed performance improvements (up to 171.4%) in all of them if under memory pressure, and minimal overhead (up to 0.39%) when there is very light memory pressure. We believe this work shows that this adaptive compressed cache design should be actually considered as an effective mechanism for improvement in system performance.

关键词： Adaptive systems Benchmark testing computer science Data compression Hard disks Kernel Linux Operating systems System performance System testing

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基于Nginx负载均衡的大规模脑电信号处理集群架构设计与实现

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信息通信技术与政策 2025年第3期51卷 16-24页

作者：刘玉婷吴彤任祥辉中国电子科技集团公司第十五研究所北京100083

随着脑电信号处理技术在医疗、神经科学及人机交互领域的广泛应用,传统单机架构在高并发场景下存在计算资源受限、延迟高、稳定性差等问题。设计了一种基于Nginx负载均衡的脑电信号处理集群架构,通过反向代理技术将并发请求分配至分布... 详细信息

随着脑电信号处理技术在医疗、神经科学及人机交互领域的广泛应用,传统单机架构在高并发场景下存在计算资源受限、延迟高、稳定性差等问题。设计了一种基于Nginx负载均衡的脑电信号处理集群架构,通过反向代理技术将并发请求分配至分布式节点,结合标准化数据处理流程及统一集群入口,显著提升系统实时性、资源利用率与吞吐量。实验表明,在并发量为100~2000个的情况下,集群架构的平均响应时间与最小响应时间均有了显著优化,同时吞吐量也得到了大幅提升,且Nginx的IP访问控制策略有效拦截非法请求,保障数据安全。该架构通过动态负载均衡实现资源高效调度,为大规模神经数据处理提供技术支撑。未来可融合人工智能与边缘计算技术,拓展至复杂脑电分析场景,助力精准医疗与智能交互发展。

关键词： Nginx 负载均衡集群脑电信号处理安全访问

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Comparison of genomes using high-performance parallel computing 15

Comparison of genomes using high-performance parallel comput...

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15th symposium on computer architecture and high performance computing

作者： Almeida, NF Alves, CER Caceres, EN Song, SW Univ Fed Mato Grosso do Sul Cuiaba MT Brazil

ISBN: (纸本)0769520464

Comparison of the DNA sequences and genes of two genomes can be useful to investigate the common functionalities of the corresponding organisms and get a better understanding of how the genes or groups of genes are organized and involved in several functions. In this paper we use high-performance parallel computing to compare the whole genomes of two organisms, namely Xanthomonas axonopodis pv. citri and Xanthomonas campestris pv. campestris, each with more than five million base-pairs. Our purpose is two-fold. First we intend to exploit the high-performance power of a cluster of low-cost microcomputers, propose a parallel solution to this problem, and show its feasibility with implementation and performance results. Second we do additional comparisons of the two genomes by locating and compare not only the homologous genes (expressed in terms of the 20-letter amino acids) but also compare the regions or gaps (in terms of the 4-letter DNA nucleotides) between the corresponding homologous genes. We have implemented the proposed comparison strategy to compare the two genomes Xanthomonas axonopodis pv. citri (Xac) and Xanthomonas campestris pv. campestris (Xcc). the parallel platform used is a Beowulf cluster of 64 nodes consisting of low cost microcomputers. Xac has 5,175,554 base pairs and 4,313 protein-coding genes while Xcc has 5,076,187 base pairs and 4,182 protein-coding genes. the parallel solution is based on the dynamic programming approach and presents not only less processing time, but also better quality results as compared to approaches based on Blast and EGG.

关键词： Amino acids Bioinformatics Costs DNA Genomics Microcomputers Organisms Parallel processing Proteins Sequences

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Architectural Contesting

Architectural Contesting

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15th International symposium on high-performance computer architecture

作者： Najaf-abadi, Hashem H. Rotenberg, Eric N Carolina State Univ Dept Elect & Comp Engn Raleigh NC 27695 USA

ISBN: (纸本)9781424429325

this paper presents results showing that workload behavior tends to vary considerably at granularities of less than a thousand instructions. If it were possible to adjust the microarchitecture to suit the workload behavior at such rates, significant single-thread performance enhancement would be achievable. However, previous techniques are too sluggish to be able to effectively respond to such fine-grain change. An approach is proposed that exploits the multi-core trend to enable swift adjustment in the employed microarchitecture upon variation in workload behavior. A number of cores that are each custom-designed for optimum performance under a class of workloads concurrently execute code in a leader-follower arrangement. In this manner, effective execution automatically and fluidly transfers to the most suitable microarchitecture as the workload behavior varies. We refer to this approach as architectural contesting. Two-way contesting yields an average speedup of 15% (maximum speedup of 25%) over a benchmark's own customized core. the paper also explores the interplay between contesting and the number of core types available in the heterogeneous multi-core. this exposes the broader issue of constrained heterogeneous multi-core design and how it influences, and may be influenced by, contesting.

关键词： computer architecture

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A high-performance Accelerator for Floating-Point Matrix Multiplication 15

A High-Performance Accelerator for Floating-Point Matrix Mul...

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15th IEEE International symposium on Parallel and Distributed Processing with Applications (ISPA) / 16th IEEE International Conference on Ubiquitous computing and Communications (IUCC)

作者： Jia, Xun Wu, Gunning Xie, Xianghui State Key Lab Math Engn & Adv Comp Wuxi 214125 Peoples R China

ISBN: (纸本)9781538637906

Matrix multiplication is a widely-used routine in science and engineering applications. Accelerating this routine is important, because applications with large-scale matrix multiplication are increasingly common, especially in the area of high-performance computing (HPC). However, existing computing platforms including CPU, GPGPU and FPGA suffer from unsatisfactory performance or efficiency for this routine. In this paper, we propose a high-performance accelerator for double-precision floating-point matrix multiplication, and build a performance model for design space exploration based on a memory access scheduling. Impact of architecture parameters on accelerator performance and efficiency are evaluated and analyzed. Experimental results show that our proposed accelerator with 256 processing elements (PEs) can achieve a maximum performance of 767.99 GFLOPS and an efficiency of 99.99% for large-scale matrix multiplication, which is well suited to the requirement of HPC applications.

关键词： matrix multiplication linear array accelerator high-performance architecture

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