检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

4,546 篇 会议
81 篇 期刊文献
15 册 图书

馆藏范围

4,642 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

2,557 篇 工学
- 2,363 篇 计算机科学与技术...
- 1,162 篇 软件工程
- 494 篇 电气工程
- 406 篇 信息与通信工程
- 212 篇 电子科学与技术（可...
- 212 篇 控制科学与工程
- 98 篇 网络空间安全
- 80 篇 动力工程及工程热...
- 80 篇 生物工程
- 68 篇 光学工程
- 65 篇 机械工程
- 56 篇 生物医学工程（可授...
- 36 篇 建筑学
- 30 篇 化学工程与技术
- 29 篇 环境科学与工程（可...
614 篇 理学
- 375 篇 数学
- 144 篇 物理学
- 93 篇 生物学
- 74 篇 系统科学
- 69 篇 统计学（可授理学、...
465 篇 管理学
- 346 篇 管理科学与工程(可...
- 134 篇 图书情报与档案管...
- 129 篇 工商管理
- 65 篇 公共管理
111 篇 法学
- 103 篇 社会学
104 篇 医学
- 73 篇 公共卫生与预防医...
- 31 篇 临床医学
- 29 篇 基础医学(可授医学...
65 篇 文学
- 65 篇 新闻传播学
39 篇 经济学
- 38 篇 应用经济学
17 篇 教育学
10 篇 农学
1 篇 艺术学

主题

1,193 篇 computer archite...
425 篇 hardware
344 篇 high performance...
295 篇 computational mo...
255 篇 concurrent compu...
236 篇 application soft...
213 篇 computer science
205 篇 parallel process...
180 篇 distributed comp...
178 篇 costs
171 篇 delay
169 篇 grid computing
168 篇 bandwidth
164 篇 field programmab...
154 篇 resource managem...
153 篇 cloud computing
145 篇 computer network...
142 篇 throughput
129 篇 processor schedu...
125 篇 scalability

机构

22 篇 institute of com...
16 篇 graphic era deem...
14 篇 chitkara univers...
13 篇 university of ch...
11 篇 college of compu...
10 篇 school of comput...
10 篇 computer science...
9 篇 georgia inst tec...
9 篇 computer systems...
9 篇 intel corp santa...
8 篇 department of co...
8 篇 department of el...
8 篇 ibm thomas j. wa...
8 篇 barcelona superc...
8 篇 mathematics and ...
8 篇 quantum universi...
8 篇 中国电子科技集团...
8 篇 carnegie mellon ...
8 篇 mathematics and ...
8 篇 key laboratory o...

作者

14 篇 navaux philippe ...
10 篇 satvik vats
9 篇 vats satvik
9 篇 i. foster
9 篇 d.k. panda
8 篇 dhabaleswar k. p...
8 篇 dongarra jack
8 篇 loh gabriel h.
8 篇 guedes dorgival
8 篇 viktor k. prasan...
8 篇 prasanna viktor ...
8 篇 mutlu onur
7 篇 shiva mehta
7 篇 borin edson
7 篇 chong frederic t...
7 篇 torrellas josep
7 篇 kim nam sung
7 篇 li chao
7 篇 zhou huiyang
7 篇 ferreira renato

语言

4,579 篇 英文
41 篇 其他
19 篇 中文
3 篇 葡萄牙文
1 篇 法文

检索条件"任意字段=15th Symposium on Computer Architecture and High Performance Computing"

共 4642 条记录，以下是251-260 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Formalized high Level Synthesis with Applications to Cryptographic Hardware 15th

Formalized High Level Synthesis with Applications to Cryptog...

引用

15th International symposium on NASA Formal Methods (NFM)

作者： Harrison, William Blumenfeld, Ian Bond, Eric Hathhorn, Chris Li, Paul Torrence, May Ziegler, Jared Two Six Technol Inc 901 N Stuart Rd Arlington VA 22203 USA

ISBN: (纸本)9783031331695;9783031331701

Verification of hardware-based cryptographic accelerators connects a low-level RTL implementation to the abstract algorithm itself;generally, the more optimized for performance an accelerator is, the more challenging its verification. this paper introduces a verification methodology, model validation, that uses a formalized high-level synthesis language (FHLS) as an intermediary between algorithm specification and hardware implementation. the foundation of our approach to model validation is a mechanized denotational semantics for the ReWire HLS language. Model validation proves the faithfulness of FHLS models to the RTL implementation and we summarize a model validation case study for a suite of pipelined Barrett multipliers.

关键词： Programming languages and models Verifying cryptographic systems Automated theorem proving

来源：评论

学校读者我要写书评

暂无评论

Towards a Data Provenance Collection and Visualization Framework for Monitoring and Analyzing HPC Environments 15th

Towards a Data Provenance Collection and Visualization Frame...

引用

15th International Conference on Management of Digital EcoSystems (MEDES)

作者： Sukhija, Nitin Bautista, Elizabeth Schultz, Adam Whitney, Cary Davis, thomas Slippery Rock Univ Slippery Rock PA 16057 USA Lawrence Berkeley Natl Lab NERSC Berkeley CA USA

ISBN: (纸本)9783031516429;9783031516436

Today, the high performance computing (HPC) landscape is growing and evolving rapidly and is catalyzing innovations and discoveries to new levels of power and fidelity in a multitude of domains. With this rapid evolution and integration of heterogeneous architectures, technologies and software models underlying HPC infrastructure, managing the confidentiality, integrity, reliability and availability of these complex systems has become extremely challenging. thus, many research efforts are focusing on monitoring solutions for collecting, correlating and analyzing health metrics and events data for achieving HPC facilities operational efficiency. Data provenance and its sources (such as metadata, lineage) empowers monitoring and event management solutions with capabilities of verification and historical evidence for identifying and troubleshooting HPC infrastructure issues and for forecasting and gaining meaningful insights about the data transformations. In this preliminary work, we present a data provenance collection and visualization infrastructure integrated with the Operations Monitoring and Notification Infrastructure (OMNI) data warehouse at Lawrence Berkeley National Laboratory's (LBNL) National Energy Scientific computing Center (NERSC) that has implemented Apache Hop, Neo4j and Grafana Loki for automated root cause analysis and visualization in the face of a computational center's and users' critical needs. Moreover, herein we also present several cases illustrating the benefits of employing the proposed framework using 600K concatenated JSON system events and health metrics datasets originating from the Perlmutter computational system, to aid in collection, analysis and visualization of the gathered data provenance. We further elucidate the advantages of this preliminary framework towards reducing the time for detecting and responding to computational center critical issues caused due to physical and cyber threats.

关键词： high performance computing Availability Fault Tolerance Reliability Big Data Monitoring Root Cause Analysis Provenance

来源：评论

学校读者我要写书评

暂无评论

ParkinSense: A Fuzzy Inference System designed to aid in diagnosing Parkinson's Disease 15

ParkinSense: A Fuzzy Inference System designed to aid in dia...

引用

15th International Conference on computing Communication and Networking Technologies, ICCCNT 2024

作者： Mahadik, Aaryan Trivedi, Veena Khubchandani, Kunal Tandon, Raj Valecha, Bhavika Computer Engg Vesit Chembur India Vesit Cmpn Dept Chembur India

ISBN: (纸本)9798350370249

Parkinson's Disease (PD) is a progressive neurodegenerative disorder that poses significant challenges in early detection and precise classification of its severity. this research paper introduces a machine learning and fuzzy logic based approach to address these challenges by developing a predictive model for Parkinson's disease detection and severity classification. the study utilizes a diverse dataset comprising clinical information and speech features from individuals with and without Parkinson's disease. through comprehensive data preprocessing and feature engineering, the paper aims to extract relevant patterns and biomarkers associated with the disease and to predict a probability of the disease using a fuzzy approach. A variety of machine learning algorithms, including but not limited to support vector machines, random forests, and neural networks, are employed to train and evaluate the model. the focus is on achieving high accuracy, sensitivity, and specificity in detecting the presence of Parkinson's disease. Additionally, the model is designed to classify the severity levels of Parkinson's disease, providing valuable insights into disease progression. the findings aim to enhance our understanding of the disease's underlying mechanisms and facilitate more targeted and personalized treatment strategies. the proposed model's performance is assessed through rigorous validation techniques, including cross-validation and independent testing. the paper aspires to bridge the gap between machine learning advancements and the pressing clinical needs in Parkinson's disease diagnosis and severity assessment, fostering a more informed and proactive approach to patient care. this research investigates Parkinson's disease detection through machine learning, incorporating features such as shimmer and frequency analysis. By employing advanced algorithms, the study aims to enhance diagnostic precision by examining subtle vocal and movement characteristics associated with P

关键词： classification fuzzy logic Machine learning parkinson's disease

来源：评论

学校读者我要写书评

暂无评论

MFHBT: Hybrid Binary Translation System with Multi-stage Feedback Powered by LLVM 15th

MFHBT: Hybrid Binary Translation System with Multi-stage Fee...

引用

15th International symposium on Advanced Parallel Processing Technologies, APPT 2023

作者： Yang, Zhaoxin Chen, Xuehai Wang, Liangpu Guo, Weiming Zhao, Dongru Yang, Chao Zhang, Fuxin SKLP Institute of Computing Technology CAS Beijing China University of Chinese Academy of Sciences Beijing China University of Science and Technology of China Hefei China State Grid Liaoning Electric Power Supply Co. Ltd Shenyang China

ISBN: (纸本)9789819978717

the shortage of applications has become a major concern for new Instruction Set architecture (ISA). Binary translation is a common solution to overcome this challenge. However, the performance of binary translation is heavily dependent on the quality of the translated code. To achieve high-quality translation, recent studies focus on integrating binary translators with compilation optimization methods. Nevertheless, such integration faces two main challenges. Firstly, it is hard to employ complex compilation optimization techniques in a dynamic binary translator (DBT) without introducing significant runtime overhead. Secondly, the task of implementing register mapping in the compiler is challenging, which can reduce expensive memory access instructions generated to maintain the guest CPU state. To resolve these challenges, we propose a hybrid binary translation system with multi-stage feedback, combining dynamic and static binary translator, named MFHBT. this system eliminates the runtime overhead caused by compilation optimization. Additionally, we introduce a mechanism to implement the register mapping through inline constraints and stack variables in the compiler. We implement a prototype of this new system powered by LLVM. Experimental results demonstrate an 81% decrease in the number of memory access instructions and a performance improvement of 3.28 times compared to QEMU. © the Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2024.

关键词： Mapping

来源：评论

学校读者我要写书评

暂无评论

Joint Wireless and computing Resource Management with Optimal Slice Selection in in-network-edge Metaverse System 15

Joint Wireless and Computing Resource Management with Optima...

引用

15th International Conference on Information and Communication Technology Convergence, ICTC 2024

作者： Rashid, Sulaiman Muhammad Aliyu, Ibrahim Isah, Abubakar Lee, Jihoon Oh, Sangwon Hahn, Minsoo Kim, Jinsul Chonnam National University Department of Intelligent Electronics and Computer Engineering Gwangju Korea Republic of Astana It University Department of Computational and Data Science Astana Kazakhstan

ISBN: (纸本)9798350364637

this paper presents an approach to joint wireless and computing resource management in slice-enabled metaverse networks, addressing the challenges of inter-slice and intra-slice resource allocation in the presence of in-network computing. We formulate the problem as a mixed-integer nonlinear programming (MINLP) problem and derive an optimal solution using standard optimization techniques. through extensive simulations, we demonstrate that our proposed method significantly improves system performance by effectively balancing the allocation of radio and computing resources across multiple slices. Our approach outperforms existing benchmarks, particularly in scenarios with high user demand and varying computational tasks. © 2024 IEEE.

关键词： Mixed-integer linear programming

来源：评论

学校读者我要写书评

暂无评论

FPGA Implementation of XOR-MUX based Full Adder and Truncated Multiplier for Signal Processing Applications 15

FPGA Implementation of XOR-MUX based Full Adder and Truncate...

引用

15th International Conference on computing Communication and Networking Technologies, ICCCNT 2024

作者： Pavithara, P. Raghapriya, N.R. Dinesh, P.M. Gowtham, S. Viji, D. Kavin Kumar, K. Chandrasekaran, Gokul Department of Electronics and Communication Engineering Kongu Engineering College Perundurai Erode638060 India Department of Computer Science and Engineering Erode Sengunthar Engineering College Thuduppathi638057 India Department of Electronics and Communication Engineering Sona College of Technology Salem636005 India Department of Electrical and Electronics Engineering KSR College of Engineering Tiruchengode637215 India Department of Artificial Intelligence and Data Science Erode Sengunthar Engineering College Thuduppathi638057 India Department of Electronics and Communication Engineering Karpagam Institute of Technology Coimbatore India

ISBN: (纸本)9798350370249

there has been considerable advancement in the digital world, particularly in image processing applications, in recent years. the most important requirements are area efficiency, minimal delay, low power consumption, and fast speed. Due to the arithmetic operations of adders and multipliers, digital devices are prone to have increase in the size of logic because they take up more space in VLSI implementation. the proposed method of XOR-MUX based full adder and truncated multiplier concentrates on reducing the delay and area. Replacing normal multipliers with truncated multipliers computes n bit output instead of 2n bit outputs that is, the MSB bit of the truncated multiplier are retained whereas the LSB bits are truncated thereby preserving the information. this is suitable for certain applications of FIR filters that do not concentrate on lower bit length. In this project, the conventional full adders are replaced by XOR-MUX based full adders and are utilized in truncated multipliers which results in area reduction by 1 2 . 6 6 % and delay reduction by 11.68 % with a modest increase in power consumption. this reduction in truncated multipliers contributes towards the design of high performance FIR filters in signal processing applications. ©2024 IEEE.

关键词： FIR filters

来源：评论

学校读者我要写书评

暂无评论

AID-DTI: Accelerating high-Fidelity Diffusion Tensor Imaging with Detail-Preserving Model-Based Deep Learning 15th

AID-DTI: Accelerating High-Fidelity Diffusion Tensor Imaging...

引用

15th International Workshop on Computational Diffusion MRI, CDMRI 2024, held in conjunction with 27th International Conference on Medical Image computing and computer-Assisted Intervention, MICCAI 2024

作者： Fan, Wenxin Cheng, Jian Li, Cheng Yang, Jing Wu, Ruoyou Zou, Juan Wang, Shanshan Paul C. Lauterbur Research Center for Biomedical Imaging Shenzhen Institutes of Advanced Technology Chinese Academy of Sciences Shenzhen518055 China University of Chinese Academy of Sciences Beijing100049 China Beihang University Beijing100191 China Peng Cheng Laboratory Shenzhen518055 China School of Physics and Electronic Science Changsha University of Science and Technology Changsha410114 China

ISBN: (纸本)9783031869198

Deep learning has shown great potential in accelerating diffusion tensor imaging (DTI). Nevertheless, existing methods tend to suffer from Rician noise and eddy current, leading to detail loss in reconstructing the DTI-derived parametric maps especially when sparsely sampled q-space data are used. To address this, this paper proposes a novel method, AID-DTI (Accelerating high fiDelity Diffusion Tensor Imaging), to facilitate fast and accurate DTI with only six measurements. AID-DTI is equipped with a newly designed Singular Value Decomposition-based regularizer, which can effectively capture fine details while suppressing noise during network training by exploiting the correlation across DTI-derived parameters. Additionally, we introduce a Nesterov-based adaptive learning algorithm that optimizes the regularization parameter dynamically to enhance the performance. AID-DTI is an extendable framework capable of incorporating flexible network architecture. Experimental results on Human Connectome Project (HCP) data consistently demonstrate that the proposed method estimates DTI parameter maps with fine-grained details and outperforms other state-of-the-art methods both quantitatively and qualitatively. © the Author(s), under exclusive license to Springer Nature Switzerland AG 2025.

关键词： Diffusion tensor imaging

来源：评论

学校读者我要写书评

暂无评论

An Experimental Comparison of RISC-V Processors: performance, Power, Area and Security - Special Session Paper 37

An Experimental Comparison of RISC-V Processors: Performance...

引用

37th IEEE International symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2024

作者： Lazzeri, Elia Forlin, Bruno Endres Furano, Gianluca Ottavi, Marco Cassano, Luca Politecnico di Milano Dipartimento di Elettronica Informazione e Bioingegneria Italy University of Twente Faculty of Electrical Engineering Mathematics and Computer Science Netherlands Europeran Space Agency European Space Research and Technology Centre Netherlands

ISBN: (纸本)9798350366884

the RISC-V instruction set architecture (ISA) has garnered significant interest from both industry and academia because of its open source nature. Recent years have witnessed a surge in published implementations of the RISC-V ISA, with various companies actively pursuing its adoption in their products. However, a comprehensive analysis comparing these emerging RISC-V processors with each other and against established embedded computing platforms has not yet been published. this paper presents an experimental evaluation of three high-performance RISC-V processors: BOOM, NOEL-V, and CVA6 (formerly Ariane). the investigation is conducted on a Xilinx Kintex-7 Field-Programmable Gate Array (FPGA) platform. We perform a detailed analysis of critical performance metrics, covering area footprint, power consumption, and performance efficiency. Additionally, we assess the security posture of these cores against transient execution attacks, a prominent contemporary security threat. Finally, a comparative evaluation is undertaken between the RISC-V processors and two conventional application-level ARM processors to elucidate technological discrepancies and application suitability. this analysis aims to provide valuable insights into the current state and potential of RISC-V processors within the embedded computing domain. © 2024 IEEE.

关键词： ARM processors

来源：评论

学校读者我要写书评

暂无评论

Ring Road: A Scalable Polar-Coordinate-based 2D Network-on-Chip architecture 57

Ring Road: A Scalable Polar-Coordinate-based 2D Network-on-C...

引用

57th Annual IEEE/ACM International symposium on Microarchitecture, MICRO 2024

作者： Feng, Yinxiao Li, Wei Ma, Kaisheng Tsinghua University Beijing China Tsinghua University Department of Computer Science and Technology Beijing China

ISBN: (纸本)9798350350579

Networks-on-chip (NoCs) are scaled out to build large-scale multi-chip networks to meet the growing demand for computing. However, the traditional router-based NoC architecture has significant limitations: 1) the overhead of routers is high, especially for long-distance traffic that traverses numerous chips and hops;2) On/off-chip traffic is mixed up, so the local NoC performance is dragged down by the cross-chip traffic;3) the routing design of intra/inter-chip networks is also entangled. the alternative router-less solution based on isolated multi-ring (IMR) can address some of these issues;however, the complete lack of routers leads to wiring overhead and limited scalability thus not suitable for large-scale multi-chip networks. therefore, we are motivated to design a new network architecture that can reduce router/wiring overhead, isolate on/off-chip traffic, and decouple inter/intra-chip routing design by combining the advantages of both routers and router-less rings. In this paper, we propose Ring Road, in which high-speed isolated multi-rings are integrated with compact routers, thus achieving flexible traffic delivery with less router usage and overhead. A polar-coordinate-based description is presented to describe the topology, and corresponding deadlock-free routing algorithms are discussed. As a standalone NoC, Ring Road is low-cost, low-latency, and high-performance. It can also be scaled out into multi-chip networks without redesigning the on-chip routing regardless of inter-chip topology. With low-cost isolated ring channels, no matter how heavy the cross-chip traffic is, the local NoC performance remains consistent. Circuit implementation and post-synthesis analysis show that Ring Road achieves 1.7∼2× bandwidth-per-Area and 1.6∼1.9× bandwidth-per-power compared with the traditional mesh router. Cycle-Accurate simulation shows that Ring Road achieves better performance and energy efficiency at various workloads and configurations. © 2024 IEEE.

关键词： Network-on-chip

来源：评论

学校读者我要写书评

暂无评论

A Charge-Digital Hybrid Compute-In-Memory Macro with full precision 8-bit Multiply-Accumulation for Edge computing Devices 15

A Charge-Digital Hybrid Compute-In-Memory Macro with full pr...

引用

15th IEEE International symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2022

作者： Chen, Jinwu Xiong, Tianzhu Si, Xin National Asic Center Southeast University Nanjing China

ISBN: (纸本)9781665464994

Compute-in-memory (CIM) is emerging as a new computing architecture to overcome the high energy consumption of edge-side AI and IoT devices. When performing high-precision neural network calculations, analog CIM and digital CIM have their own advantages and disadvantages. In this paper, we combine the advantages of high energy efficiency of analog CIM and high accuracy of digital CIM to propose a charge-digital hybrid CIM (CDH-CIM) macro. By placing the high bits in the digital domain and the low bits in the charge domain, the multiply-accumulation (MAC) operation of 8b input activations (lAs) and 8b weights is achieved with no precision loss. the proposed CDH-CIM macro is designed using 22nm FDSOI CMOS process. Simulation shows that the macro achieves 6.9811.0 TOPS/W at 0.8V and 71.92% inference accuracy when performing CIFAR-100 dataset. © 2022 IEEE.

关键词： Energy utilization

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共465页 << < 22 23 24 25 26 27 28 29 30 31 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：