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IEEE International symposium on Quality Electronic Design

作者： Hasita Veluri Dilip Vasudevan Lawrence Berkeley National Laboratory Applied Mathematics and Computational Research Berkeley CA USA

ISBN: (数字)9798331509422

ISBN: (纸本)9798331509439

We present a runtime reconfigurable Field Programmable Crossbar Array (FPCA) architecture designed to enable high-accuracy multiplication and division alongside high through-put ML operations. Our innovative in-memory compute-based multiplier and divider designs employing novel partial product reduction techniques support expandable multi-precision floating-point operations. Leveraging advanced interface and peripheral design techniques, our error-resilient FPCA achieves 0% error for in-memory digital operations, demonstrating remarkable robustness and reliability despite device and crossbar irregularities. Additionally, our architecture enhances neural network training throughput by 63.8 × and improves power efficiency by 5.18 ×compared to state-of-the-art memristor-based accelerators. this work paves the way for future developments in high-performance, error-resistant in-memory computing solutions.

关键词： Training three-dimensional displays Runtime computer architecture Artificial neural networks In-memory computing throughput Reliability engineering Robustness System-on-chip

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A high-performance Data Verification Mechanism in Blockchain-Based IoT Systems 21

A High-Performance Data Verification Mechanism in Blockchain...

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21st IEEE International symposium on Parallel and Distributed Processing with Applications, 13th IEEE International Conference on Big Data and Cloud computing, 16th IEEE International Conference on Social computing and Networking and 13th International Conference on Sustainable computing and Communications, ISPA/BDCloud/SocialCom/SustainCom 2023

作者： Zhang, Jingyu Zhou, Pian Sun, Yongtao Luo, Lailong Changsha University of Science and Technology School of Computer and Communication Engineering Changsha China National University of Defense Technology Science and Technology on Information Systems Engineering Laboratory School of Systems Engineering Changsha China

ISBN: (纸本)9798350329223

With the rapid development of the distributed network and communication, the Internet of things (IoT) systems have been applied to all walks of life. Blockchain technology is one of the most popular research fields recently, which can provide a reliable storage solution and solve information security issues for IoT systems. Transaction information is the most critical fundamental data in the blockchain systems, which needs to be verified to avoid being tempered with by malicious nodes in the process of transmission. With the exponential growth of the number of IoT devices, the limitations of the current storage structure put too much pressure on the system nodes. How to improve verification efficiency has become a key challenge. To alleviate this problem, this paper proposes a novel high-performance verification mechanism for data security protection in blockchain-based IoT systems. We design a new storage structure based on Huffman trunk tree (HTT), and conduct the quantitative analysis of transaction weights. Transactions are stored in full-featured devices in the form of Huffman Merkle tree (HMT), and only the content of HTT is saved in lightweight devices. Finally, the performance superiority of our mechanism is proved through theoretical analysis and experimental evaluation. In blockchain-based IoT systems, our mechanism significantly reduces the data transmission cost and computation overhead, effectively improving the efficiency of data verification. © 2023 IEEE.

关键词： Efficiency

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WCSim: A Cloud computing Simulator with Support for Bag of Tasks Workflows

WCSim: A Cloud Computing Simulator with Support for Bag of T...

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International symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Maicon Ança dos Santos Gabriel J. A. Grabher Matheus F. Kovaleski Cláudio F. R. Geyer Gerson Geraldo H. Cavalheiro PPGC/UFPel Pelotas Brazil LIG/Université Grenoble-Alpes Grenoble France II/UFRGS Porto Alegre Brazil

In this paper, we present WCSim, Workflow Cloud Simulator. Firstly, we argue that this cloud simulation tool offers a high level of accessibility by allowing the description of various components, such as users, infrastructures, and workload, of a given scenario simply by providing parameters at launch time, without requiring the extension of the simulator code. then, we explain how we conceived the components for the simulation models and provide a detailed description of the implemented software. Additionally, we compare the results of a small scenario obtained from two other simulation tools with those provided by WCSim. Finally, we present a case study that illustrates the usage of WCSim. the paper also introduces the a abstraction to model workflows as a Direct Acyclic Graph of Bag of Tasks.

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high-Rate Machine Learning for Forecasting Time-Series Signals 30

High-Rate Machine Learning for Forecasting Time-Series Signa...

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IEEE 30th International symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Panahi, Atiyehsadat Kabir, Ehsan Downey, Austin Andrews, David Huang, Miaoqing Bakos, Jason D. Univ Arkansas Dept Comp Sci & Comp Engn Fayetteville AR 72701 USA Univ South Carolina Dept Comp Sci & Comp Engn Columbia SC 29208 USA

ISBN: (纸本)9781665483322

"Active structures" are physical structures that incorporate real-time monitoring and control. Examples include active vibration damping or blast mitigation systems. Evaluating physics-based models in real-time is generally not feasible for such systems having high-rate dynamics which require microsecond response times, but data-driven machine-learning-based models can potentially offer a solution. this paper compares the cost and performance of two FPGA-based implementations of real-time, continuously-trained models for forecasting time-series signals with non-stationarities, with one using high-Level Synthesis (HLS) and the other a programmable overlay architecture. the proposed model accepts a uni-variate vibration signal and seeks to forecast future samples to inform high-rate controllers. the proposed forecasting method performs two concurrent neural inference operations. One inference forecasts the state of the signal f samples into the future as a function of the most recent h samples, while the other forecasts the current sample given h samples starting from h + f - 1 samples into the past. the first forecast produces the forecast while the second forecast allows the system to calculate the model's loss and perform an immediate model update before the next sample period.

关键词： real-time learning high-rate machine learning (HRML) neural network multi-level perceptron overlay SIMD high-level synthesis (HLS) control theory high-rate dynamics high-rate structural health monitoring

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Systematic Approaches for Precise and Approximate Quantum State Runtime Assertion 27

Systematic Approaches for Precise and Approximate Quantum St...

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27th IEEE International symposium on high-performance computer architecture (HPCA)

作者： Liu, Ji Zhou, Huiyang North Carolina State Univ Raleigh NC 27695 USA

ISBN: (纸本)9781665422352

With the rapid growth of quantum computing technology, programmers need new tools for debugging quantum programs. Recent works show that assertions are a promising way for debugging quantum programs. However, there are two main drawbacks with the existing schemes. First, the existing schemes, including both statistical and dynamic assertions are only capable of asserting limited types of states, namely classical, superposition, and specific entanglement states. Second, the use cases of these assertions are limited, since the programmer has to know the exact/precise state to assert. In this work, we propose two systematic approaches for dynamic quantum state assertion and they can assert a much broader range of quantum states including both pure states and mixed states. We also introduce the idea of approximate quantum state assertion for the cases where the programmers only have limited knowledge of the quantum states. Approximate assertion is capable of checking membership in a set of states {vertical bar phi), vertical bar phi), ... }. While precise quantum state assertion can check a specific quantum state, approximate assertion enables a way to check whether the qubits of interest are in a super-set of some expected states, which is analogous to the well-known Bloom filter for membership checking in classical computing. Our experiments demonstrate that our systematic approaches can assert many more quantum states and can be used in various assertion locations for qubit state checking.

关键词： quantum computing runtime assertion

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Polaris: Enhancing CXL-based Memory Expanders with Memory-side Prefetching 15th

Polaris: Enhancing CXL-based Memory Expanders with Memory-si...

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15th International symposium on Advanced Parallel Processing Technologies, APPT 2023

作者： Zhou, Zhe Xu, Shuotao Chen, Yiqi Zhang, Tao Shu, Ran Qu, Lei Cheng, Peng Xiong, Yongqiang Sun, Guangyu School of Integrated Circuits Beijing China School of Computer Science Beijing China Beijing Advanced Innovation Center for Integrated Circuits Beijing China Microsoft Research Asia Beijing China

ISBN: (纸本)9789819978717

the use of CXL-based memory expanders introduces increased latency compared to local memory due to control and transmission overheads. this latency difference negatively impacts tasks that are sensitive to latency. While cache prefetching has traditionally been used to mitigate memory latency, addressing this performance gap requires improved CPU prefetch coverage. However, tuning a CPU prefetcher for CXL memory necessitates costly CPU modifications and can result in cache pollution and wasted memory bandwidth. To address these challenges, we propose a solution called Polaris, a novel CXL memory expander that integrates a hardware prefetcher in the CXL memory controller chip. Polaris analyzes incoming memory requests and prefetches cachelines to a dedicated SRAM buffer without requiring modifications to CPUs or software. In cases where prefetch hits occur, Polaris establishes a "shortcut" for rapid memory access, significantly reducing the performance gap between CXL and local DDR memory. Furthermore, if small CPU changes are allowed, such as extending Intel’s DDIO, Polaris can further minimize CXL memory access overheads by actively pushing high-confidence prefetches to the CPU’s last-level cache (LLC). Extensive experiments demonstrate that, in conjunction with various CPU-side prefetchers, Polaris enables up to 85% of common workloads (on average, 43%) to effectively tolerate CXL memory’s longer latency. © the Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2024.

关键词： Memory architecture

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Special issue on advances in techniques for assessment performance portability of HPC applications

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Future Generation computer Systems 2025年 171卷

作者： Marowka, Ami Stpiczyński, Przemyslaw Wyrzykowski, Roman Parallel Research Lab Petach Tikva49729 Israel Institute of Computer Science Maria Curie-Sklodowska University Lublin20-033 Poland Department of Computer Science Czestochowa University of Technology Czestochowa42-201 Poland

this special issue aims to present new developments and advances in techniques for assessment performance portability of high performance computing applications. It contains revised and extended versions of selected papers presented at the 10th Workshop on Language-Based Parallel Programming Models, WLPP 2024, which was a part of 15th International Conference on Parallel Processing and Applied Mathematics, PPAM 2024, held on September 8–11, 2024, in Ostrava, Czech Republic. © 2025

关键词： HPC applications Parallel programming languages performance portability

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Impact of Adaptive Velocity based Hello Intervals in UAS to Sustainability: Enhancing Network performance through Adaptive Velocity based Hello Intervals 2023

Impact of Adaptive Velocity based Hello Intervals in UAS to ...

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15th International Conference on Contemporary computing, IC3 2023

作者： Saini, Hemant Kumar Jain, Kusumlata Department of Computer Science & Engineering Manipal University Jaipur Jaipur Rajasthan Dehmi Kalan303007 India Department of Computer & Communication Engineering Manipal University Jaipur Jaipur Rajasthan Dehmi Kalan303007 India

ISBN: (纸本)9798400700224

With the growing demands of sustainability in the environment, unmanned aerial systems (UAS) are implemented in almost every monitoring zone, like agriculture, disasters, medical purposes, etc., wherever it is difficult to cover a large area in a limited amount of time in a fast manner. So sustainability was achieved and eased with UAS, but with its new boon, it also suffers from issues with energy sources due to its high mobility. Conventionally, mobile devices create the network in 2D, named ,mobile adhoc network (MANET), but due to fast and high coverage, the new refined system with high flexibility created flying adhoc network (FANET). But the UAS running on battery power suffers from battery drain due to this drastic mobility. Since the UAS completely fly and communicate with routing management, most of the FANET utilises AODV routing, where communication is held through the hello packets, whose intervals are critical to maintain, which were seen being trivially transmitted periodically without indeed. thus, a new adaptive velocity-based hello interval method was proposed that transmits the hello packet in the peer network according to the speed of the UAS, so the wastage of energy at non-required points could be saved. this would improve the battery power, which would elongate the flight time, as well as their network performance. the scheme is tested over NS3.27, where it results in saving about 4-8% energy and getting benefits in throughput and end-to-end delays as well. © 2023 ACM.

关键词： Network performance

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Student performance Prediction Analysis Using Neural Networks 15th

Student Performance Prediction Analysis Using Neural Network...

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15th International Conference on Soft computing and Pattern Recognition, SoCPaR 2023 and 14th World Congress on Nature and Biologically Inspired computing, NaBIC 2023

作者： Prashanth, Mallellu Sai Uma Maheswari, V. Aluvalu, Rajinikanth Prasad Kantipudi, M.V.V. Symbiosis Institute of Technology Hyderabad Campus Symbiosis International University Pune India Department of Computer Science and Engineering Chaitanya Bharathi Institute of Technology Hyderabad India Symbiosis Institute of Technology Pune Campus Symbiosis International University Pune India

ISBN: (纸本)9783031810824

this research paper presents a comprehensive analysis of student performance based on a merged dataset from two subjects: Mathematics and Portuguese. the dataset encompasses a wide range of student attributes and behaviours, allowing us to explore various factors influencing academic success. the study employs exploratory data analysis, data visualization, statistical tests, and machine learning techniques to uncover patterns and relationships within the data. the analysis begins with data preprocessing, including column renaming, categorical variable creation, and merging of datasets. Visualizations such as count plots, heatmaps, and distribution plots are utilized to understand the distribution of final grades and correlations between attributes. Furthermore, the study investigates the impact of romantic status, weekend alcohol consumption, parental education, social activities, desire for higher education, and urban/rural living areas on student performance. Chi-square tests for association are conducted to assess the significance of relationships between categorical variables and final grades. Machine learning models, including Decision Trees, Random Forests, Support Vector Machines, Logistic Regression, AdaBoost, and Stochastic Gradient Descent, are employed to predict student performance. Feature selection techniques are also employed to determine the optimal number of features for achieving high prediction accuracy. through this comprehensive analysis, we gain insights into the complex interplay of various factors affecting student performance. the findings contribute to a deeper understanding of academic success and highlight potential areas for intervention and improvement. this research serves as a valuable resource for educators, policymakers, and researchers seeking to enhance educational outcomes and facilitate targeted interventions for students. © the Author(s), under exclusive license to Springer Nature Switzerland AG 2025.

关键词： Support vector machines

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DeepWave: A Software Stack for Parallelizing Deep Learning Models Used in Geophysics

DeepWave: A Software Stack for Parallelizing Deep Learning M...

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International symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Allan Pinto Gustavo Leite Marcio Pereira Hervé Yviquel Sandro Rigo Guido Araujo (LNLS) Brazilian Synchrotron Light Laboratory Brazilian Center for Research in Energy and Materials (CNPEM) Campinas Sao Paulo Brazil Institute of Computing University of Campinas (UNICAMP) Campinas Sao Paulo Brazil

ISBN: (数字)9798350356168

ISBN: (纸本)9798350356175

this paper introduces DeepWave, a novel software stack, and methodology designed to integrate generative artificial intelligence into traditional seismic surveying techniques, significantly enhancing the computational efficiency of geophysical exploration. By utilizing advanced machine learning frameworks such as JAX, FLAX, and ALPA, DeepWave employs a parallelization strategy for image-to-image translation networks, optimizing the seismic data interpretation process. DeepWave reduces the computational demands of intensive geophysical algorithms, such as Full-waveform Inversion (FWI), while maintaining the accuracy required for detailed subsurface analysis. this method enables faster and more efficient processing of large seismic datasets, providing deeper insights into the Earth’s subsurface structures with reduced computational resources. the results demonstrate a substantial improvement in processing speed and resource management, establishing a new geophysical research and exploration standard.

关键词： Training Deep learning Machine learning algorithms Computational modeling high performance computing Full stack Parallel processing Computational efficiency Resource management Standards

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