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performance Evaluation of Modified Best First Decreasing Algorithms for Dynamic Virtual Machine Placement in Cloud computing 1

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15th International Conference on Cloud computing, CLOUD 2022, held as part of the Services Conference Federation, SCF 2022

作者： Akinwumi, Joseph Adeyanju, Ibrahim Department of Computer Engineering Afe Babalola University Ado-Ekiti Nigeria Department of Computer Engineering Federal University Oye-Ekiti Nigeria

ISBN: (数字)9783031234989

ISBN: (纸本)9783031234972

Cloud computing has become the popular choice in developing countries such as Nigeria where access to high performance computing facilities is inadequate. Individuals, organizations and institutions in need of high performance computing facilities can subscribe to cloud computing facilities on a pay-as-you-go basis. Whenever a customer requests for cloud computing services, there is a problem of allocating virtual machines for such services on available physical machines while minimizing energy consumption and carbon-dioxide emission, as well as maximizing resource utilization. the Modified Best First Decreasing(MBFD) algorithm is a baseline algorithm for evaluating the performance of virtual machine placement algorithms in cloud computing. this research carries out a performance evaluation of the MBFD algorithms in the CloudSim 3.0.3 simulator under three different configurations A, B and C. Configuration A has fewer processor resources than configuration B which has fewer processor resources than configuration C. CloudSim 3.0.3 is installed in Eclipse Integrated Development Environment on a Laptop with two Intel Celeron Processors at 1.60 GHz each and 4 GB memory. Configurations B and C have lower energy consumption and faster computation time compared to configuration A. the lowest average energy consumption is 101.97 KWh and standard deviation of 8.63 KWh when Local Regression Robust with minimum utilization heuristic algorithm was executed under configuration B. the fastest average computation time is 0.21898 s for static threshold with minimum utilization heuristic algorithm under configuration B. this work recommends evaluating the adaptive heuristics on real-life cloud computing testbed to further validate the results. © 2022, the Author(s), under exclusive license to Springer Nature Switzerland AG.

关键词： Energy utilization

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Enhancing Deepfake Detection: Leveraging Deep Models for Video Authentication

Enhancing Deepfake Detection: Leveraging Deep Models for Vid...

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International Conference on computing and Networking Technology (ICCNT)

作者： Vikram Sundaram Babitha Senthil Susmitha Vekkot Department of Electronics and Communication Engineering Amrita School of Engineering Amrita Vishwa Vidyapeetham Bengaluru India

ISBN: (数字)9798350370249

ISBN: (纸本)9798350370270

this research endeavors to revolutionize deepfake detection by achieving unparalleled accuracy with a modest dataset. Leveraging CNN-based feature extractors and either CNN or MLP as high-level architectures, the methodology prioritizes precision in discerning authentic from fabricated content. Remarkably, both the InceptionV3 and InceptionResNetV2 models, employing Multilayer Perceptrons (MLP) as their highlevel architecture, demonstrate outstanding accuracy rates, of $\mathbf{84.6\%}$. Moreover, the Receiver Operating Characteristic (ROC) for InceptionResNetV2 stands at an exceptional 0.99, while for NasNetLarge, it reaches $\mathbf{0. 9 8}$. Additionally, the MLP InceptionResNetV2 model demonstrated exceptional performance with 12 True Negatives (TN) and only 1 False Negative (FN). these findings underscore the efficacy of the proposed approach in combating the proliferation of deceptive media content.

关键词： Deepfakes Accuracy Computational modeling Authentication computer architecture Receivers Multilayer perceptrons Media Feature extraction

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S-Clflush: Securing Against Flush-based Cache Timing Side-Channel Attacks

S-Clflush: Securing Against Flush-based Cache Timing Side-Ch...

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International symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Tejeshwar Bhagatsing thorawade Prajakta Yeola Varun Venkitaraman Virendra Singh Indian Institute of Technology Bombay India

ISBN: (数字)9798350356168

ISBN: (纸本)9798350356175

Micro-architectural attacks exploit intrinsic vulnerabilities within computing systems, circumventing advanced security techniques such as cryptographic algorithms, access control policies, and secure enclaves. these attacks encompass a range of methodologies, including cache timing side-channel attacks like Flush+Reload, Flush+Flush, and Prime+Probe, as well as speculative execution attacks such as Spectre and Meltdown. these exploits leverage specific characteristics of micro-architecture to infer sensitive data, posing a significant threat to system security. Cache timing side-channel attacks exploit the inclusive nature of the last-level cache (LLC) to deduce the memory access patterns of victim processes. By observing the timing variations associated with cache hits and misses, attackers can extract confidential information, such as cryptographic keys. Although existing mitigation strategies provide a level of security, they typically do so at the expense of system performance and increased hardware. these trade-offs limit the practical applicability of such defences in performance-critical environments. this paper proposes S-Clflush: Secure Clflush, an innovative defence mechanism specifically designed to counter flush-based cache timing side-channel attacks. S-Clflush achieves this by modifying the existing clflush instruction to prevent attackers from inferring memory access patterns based on cache access latency. Unlike traditional mitigation techniques, S-Clflush enhances security without incurring performance degradation or additional area overhead. the proposed mechanism is formally verified to ensure its security guarantees. Our evaluation against the state-of-the-art mitigation technique TimeCache shows a 0.5% improvement in performance and a 58% reduction in MPKI on average without adding area overhead.

关键词： Degradation Prevention and mitigation System performance high performance computing Side-channel attacks computer architecture Hardware Timing Security Data mining

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A Distributed Algorithm for Identifying Strongly Connected Components on Incremental Graphs

A Distributed Algorithm for Identifying Strongly Connected C...

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International symposium on computer architecture and high performance computing (SBAC-PAD)

作者： S. Srinivasan A. Khanda A. Pandey S. K. Das S. Bhowmick B. Norris Department of Computer Science University of Oregon Eugene OR USA Department of Computer Science and Engineering University of North Texas Denton TX USA Department of Computer Science Missouri University of Science and Technology Rolla MO USA Department of Management Information Systems Bowie State University MD

Incremental graphs that change over time capture the changing relationships of different entities. Given that many real-world networks are extremely large, it is often necessary to partition the network over many distributed systems and solve a complex graph problem over the partitioned network. this paper presents a distributed algorithm for identifying strongly connected components (SCC) on incremental graphs. We propose a two-phase asynchronous algorithm that involves storing the intermediate results between each iteration of dynamic updates in a novel meta-graph storage format for efficient recomputation of the SCC for successive iterations. To the best of our knowledge, this is the first attempt at identifying SCC for incremental graphs across distributed compute nodes. Our experimental analysis on real and synthesized graphs shows up to 2.8x performance improvement over the state-of-the-art by reducing the overall memory utilized and improving the communication bandwidth.

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A new level-set analysis and sparse storage format for the SPTRSV in GPUs

A new level-set analysis and sparse storage format for the S...

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International symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Manuel Freire Ernesto Dufrechou Pablo Ezzatti

ISBN: (数字)9798350356168

ISBN: (纸本)9798350356175

Due to its relevant role in many numerical methods, the solution of sparse triangular linear systems (SpTRSV) in parallel platforms is continuously studied to extract as much performance as possible from the latest hardware architectures. In the case of GPUs, the latest solvers use the synchronization-free paradigm. When the problem involves several system solutions for the same matrix, they often pre-process it through a levelset analysis to improve the equation solution scheduling in the solution phase. In addition, other optimizations address the load balancing issues and irregular memory access of the SpTRSV. In this work, we modify the classical approach to compute the level sets used in the parallel SpTRSV computation, and we show that the new strategy generally reduces the computation time of the solver. Furthermore, we design an internal matrix representation that can significantly accelerate the solution stage at the cost of increasing the memory storage requirements of the algorithm. the experimental evaluation shows that the proposed modifications can improve the performance of a recent levelset and synchronization-free solver by up to 70%, significantly outperforming other state-of-the-art solvers, especially when several linear systems must be solved for each analysis phase.

关键词： Linear systems Costs Processor scheduling Level set high performance computing Memory management Load management Hardware Sparse matrices Optimization

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Revisiting HyperDimensional Learning for FPGA and Low-Power architectures 27

Revisiting HyperDimensional Learning for FPGA and Low-Power ...

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27th IEEE International symposium on high-performance computer architecture (HPCA)

作者： Imani, Mohsen Zou, Zhuowen Bosch, Samuel Rao, Sanjay Anantha Salamat, Sahand Kumar, Venkatesh Kim, Yeseong Rosing, Tajana Univ Calif Irvine Dept Comp Sci Irvine CA 92697 USA Univ Calif San Diego Dept Comp Sci & Engn San Diego CA 92093 USA MIT Dept Elect Engn & Comp Sci Cambridge MA 02139 USA Daegu Gyeongbuk Inst Sci & Technol Informat & Commun Engn Daegu South Korea

ISBN: (纸本)9781665422352

Today's applications are using machine learning algorithms to analyze the data collected from a swarm of devices on the Internet of things (IoT). However, most existing learning algorithms are overcomplex to enable real-time learning on IoT devices with limited resources and computing power. Recently, Hyperdimensional computing (HDC) is introduced as an alternative computing paradigm for enabling efficient and robust learning. HDC emulates the cognitive task by representing the values as patterns of neural activity in high-dimensional space. HDC first encodes all data points to high-dimensional vectors. It then efficiently performs the learning task using a well-defined set of operations. Existing HDC solutions have two main issues that hinder their deployments on low-power embedded devices: (i) the encoding module is costly, dominating 80% of the entire training performance, (ii) the HDC model size and the computation cost grow significantly with the number of classes in online inference. In this paper, we proposed a novel architecture, LookHD, which enables real-time HDC learning on low-power edge devices. LookHD exploits computation reuse to memorize the encoding module and simplify its computation with single memory access. LookHD also address the inference scalability by exploiting HDC governing mathematics that compresses the HDC trained model into a single hypervector. We present how the proposed architecture can be implemented on the existing low power architectures: ARM processor and FPGA design. We evaluate the efficiency of the proposed approach on a wide range of practical classification problems such as activity recognition, face recognition, and speech recognition. Our evaluations show that LookHD can achieve, on average, 28.3 x faster and 97.4 x more energy-efficient training as compared to the state-of-the-art HDC implemented on the FPGA. Similarly, in the inference, LookHD is 2.2 x faster, 4.1 x more energy-efficient, and has 6.3 x smaller model siz

关键词： HyprDimensional computing Brain-inspired computing Machine learning Real-time learning FPGA

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Fusing Multi-Granularity Data for Stock Trend Prediction with Contrastive Pre-training 23

Fusing Multi-Granularity Data for Stock Trend Prediction wit...

引用

15th International Conference on Machine Learning and computing, ICMLC 2023

作者： Xu, Haonan Li, Jiange Wang, Peng Yin, Xianchen Xue, Wenfang Center for Research on Intelligent Perception and Computing National Laboratory of Pattern Recognition Institute of Automation Chinese Academy of Sciences School of Artificial Intelligence University of Chinese Academy of Sciences Beijing Shi Haidian Qu China Department of Information Technology China Securities Co. Ltd. Beijing Shi China Department of Index and Quantitative Investment China Securities Co. Ltd. Beijing Shi China

ISBN: (纸本)9781450398411

the advances in financial theory and power of computer technology have driven the development of quantitative investing. Stock trend forecasting as an important topic in quantitative investment has attracted more and more researchers. the development of deep learning has also led to the emergence of many interesting models in the field. However, most of the existing models only use daily frequency data to predict the stock price fluctuations, lacking the consideration of high-frequency data and relational data. At the same time, it remains a challenge to incorporate multi-granularity data into model training. Based on this, we propose a contrastive pre-training model fusing high frequency data and daily frequency data(HRC), which construct pre-training tasks with a positive and negative sample design in terms of data granularity and stock relationships. In addition to this, we also constructed a label-based training task using the performance of returns to classify stocks. the experiments on real-world stock dataset show significant improvements of our approach over the baselines. © 2023 Owner/Author.

关键词： Deep learning

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FPGA-Based Hardware-in-the-Loop Real-Time Simulation Implementation 66

FPGA-Based Hardware-in-the-Loop Real-Time Simulation Impleme...

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2023 IEEE 66th International Midwest symposium on Circuits and Systems, MWSCAS 2023

作者： Kordi, Farshideh Barnard, Christian Fortier, Paul Miled, Amine Université Laval Departement of Electrical and Computer Engineering QuébecQC Canada

ISBN: (纸本)9798350302103

Hardware-in-the-Loop (HIL) simulators have become an essential tool in the automotive industry as they allow comprehensive testing and validation of electronic control units (ECUs), Although HIL simulations are widely used in the vehicle, aerospace and other industries that rely on electronic control systems, they can also be quite challenging to develop. One of the main challenges of HIL simulators is creating a virtual environment that accurately replicates the behavior of the real-world system. Artificial intelligence (AI) algorithms can be trained on extensive real-world datasets to create more accurate virtual environments of complex systems for HIL simulations. Moreover, latency is a crucial factor in producing a reliable virtual environment for ECU in HIL simulations. FPGA (Field Programmable Gate Array) can help to minimize latency in HIL simulations by providing high-performance computing resources. this paper aims to address these challenges by presenting a machine learning-based HIL simulator design on FPGA. the proposed architecture uses FPGA to accelerate the computations of a temporal convolutional neural network (TCN). the paper also describes how increasing the number of input channels can improve the performance of the TCN model on an FPGA. © 2023 IEEE.

关键词： anti-lock brake system (ABS) artificial intelligence (AI) electronic control unit (ECU) Hardware-in-the-Loop (HIL) simulator temporal convolutional networks (TCN)

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Enhancing CNN performance Across Diverse Domains: Exploring the Efficacy of Domain Adversarial Neural Network with the Use of CNN for Improved Generalization in Deep Learning

Enhancing CNN Performance Across Diverse Domains: Exploring ...

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International Conference on computing and Networking Technology (ICCNT)

作者： Vs Gaadha Amrutha S Dev Vinitha Panicker Aswin Sreerag Anargha Ranjit Amrita School of Computing Amrita Vishwa Vidyapeetham Amritapuri India

ISBN: (数字)9798350370249

ISBN: (纸本)9798350370270

Convolutional neural networks (CNNs) are foundational tools for image classification in deep learning, with models like InceptionNet, ResNet, MobileNet, and DenseNet excelling in feature extraction and validation. However, their performance can suffer in domains with high variability. Domain Adversarial Neural Networks (DANN) address this issue by reducing domain shift through finding domain-invariant representations. DANNs, by training adversaries, enable CNNs to generalize better across different environments, thus enhancing overall performance. this study explores the efficacy of DANN in boosting CNN performance across varied environments. Initially, we detail each base model, focusing on their architecture and feature extraction capabilities. We then introduce DANN as a domain optimization method, showcasing its ability to learn domain-invariant representations. Extensive testing and comparative analysis reveal that integrating DANN with CNN models significantly outperforms using CNNs alone. the findings confirm DANN’s improved generalizability, effectiveness in mitigating domain shift, and potential for advancing deep learning-based image classification tasks.

关键词： Deep learning Training Accuracy Neural networks computer architecture Feature extraction Robustness Convolutional neural networks Image classification Testing

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QuCloud: A New Qubit Mapping Mechanism for Multi-programming Quantum computing in Cloud Environment 27

QuCloud: A New Qubit Mapping Mechanism for Multi-programming...

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27th IEEE International symposium on high-performance computer architecture (HPCA)

作者： Liu, Lei Dou, Xinglei Chinese Acad Sci Sys Inventor Lab ICT SKLCA Beijing Peoples R China

ISBN: (纸本)9781665422352

For a specific quantum chip, multi-programming improves overall throughput and resource utilization. Previous studies on mapping multiple programs often lead to resource under-utilization, high error rate, and low fidelity. this paper proposes QuCloud, a new approach for mapping quantum programs in the cloud environment. We have three new designs in QuCloud. (1) We leverage the community detection technique to partition physical qubits among concurrent quantum programs, avoiding the waste of robust resources. (2) We design X-SWAP scheme that enables inter-program SWAPs and prioritizes SWAPs associated with critical gates to reduce the SWAP overheads. (3) We propose a compilation task scheduler that schedules concurrent quantum programs to be compiled and executed based on estimated fidelity for the best practice. We evaluate our work on publicly available quantum computer IBMQ16 and a simulated quantum chip IBMQ50. Our work outperforms the state-of-the-art work for multi-programming on fidelity and compilation overheads by 9.7% and 11.6%, respectively.

关键词： n/a

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