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Evaluation of a multithreaded architecture for cellular computing

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8th International symposium on high-performance computer architecture, HPCA 2002

作者： Caşcaval, C. Castaños, J.G. Ceze, L. Denneau, M. Gupta, M. Lieber, D. Moreira, J.E. Strauss, K. Warren, H.S. IBM Thomas J. Watson Research Center Yorktown HeightsNY10598-0218 United States

ISBN: (纸本)0769515258

Cyclops is a new architecture for high-performance parallel computers that is being developed at the IBM T. J. Watson Research Center. the basic cell of this architecture is a single-chip SMP (symmetric multiprocessor) system with multiple threads of execution, embedded memory and integrated communications hardware. Massive intra-chip parallelism is used to tolerate memory and functional unit latencies. Large systems with thousands of chips can be built by replicating this basic cell in a regular pattern. In this paper, we describe the Cyclops architecture and evaluate two of its new hardware features: a memory hierarchy with a flexible cache organization and fast barrier hardware. Our experiments with the STREAM benchmark show that a particular design can achieve a sustainable memory bandwidth of 40 GB/s, equal to the peak hardware bandwidth and similar to the performance of a 128-processor SGI Origin 3800. For small vectors, we have observed in-cache bandwidth above 80 GB/s. We also show that the fast barrier hardware can improve the performance of the Splash-2 FFT kernel by up to 10%. Our results demonstrate that the Cyclops approach of integrating a large number of simple processing elements and multiple memory banks in the same chip is an effective alternative for designing high-performance systems. © 2002 IEEE.

关键词： Bandwidth

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high performance and energy efficient serial prefetch architecture

High performance and energy efficient serial prefetch archit...

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4th International symposium on high performance computing, ISHPC 2002

作者： Reinman, Glenn Calder, Brad Austin, Todd Computer Science Department University of California Los Angeles United States Department of Computer Science and Engineering University of California San Diego United States Electrical Engineering and Computer Science Department University of Michigan United States

ISBN: (纸本)354043674X

Energy efficient architecture research has flourished recently, in an attempt to address packaging and cooling concerns of current microprocessor designs, as well as battery life for mobile computers. Moreover, architects have become increasingly concerned with the complexity of their designs in the face of scalability, verification, and manufacturing concerns. In this paper, we propose and evaluate a high performance, energy and complexity efficient front-end prefetch architecture. this design, called Serial Prefetching, combines a high fetch bandwidth branch prediction and efficient instruction prefetching architecture with a low-energy instruction cache. Serial Prefetching explores the benefit of decoupling the tag component of the cache from the data component. Cache blocks are first verified by the tag component of the cache, and then the accesses are put into a queue to be consumed by the data component of the instruction cache. Energy is saved by only accessing the correct way of the data component specified by the tag lookup in a previous cycle. the tag component does not stall on a I-cache miss, only the data component. the accesses that miss in the tag component are speculatively brought in from lower levels of the memory hierarchy. this in effect performs a prefetch, while the access migrates through the queue to be consumed by the data component. © 2002 Springer Berlin Heidelberg.

关键词： Energy efficiency

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Datapath merging and interconnection sharing for reconfigurable architectures

Datapath merging and interconnection sharing for reconfigura...

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International symposium on System Synthesis

作者： N. Moreano G. Araujo Zhining Huang S. Malik IC-UNICAMP Sao Paulo Brazil Campo Grande DCT-UFMS Mato Grosso do Sul Brazil Department of Electrical Engineering Princeton University Princeton NJ USA

Recent work in reconfigurable computing research has shown that a substantial performance speedup can be achieved through architectures that map the most relevant application inner-loops to a reconfigurable datapath. Any solution to this problem must be able to synthesize a datapath for each loop and to merge them together into a single reconfigurable datapath. the main contribution of this paper is a novel graph-based technique for the datapath merge problem. this approach is based on the solution of a maximum clique problem that merges datapaths one at a time. A set of experiments, using the MediaBench benchmark, shows that the proposed technique produces 24% fewer datapath interconnections than a previous solution to this problem.

关键词： Merging Reconfigurable architectures Logic arrays Hardware Reconfigurable logic computer architecture Logic design high performance computing Digital systems Software performance

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Distributed electronic patient encounter with high performance and availability

Distributed electronic patient encounter with high performan...

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Annual IEEE symposium on computer-Based Medical Systems

作者： L. Frank A. Mukherjee Copenhagen Business School Frederiksberg Denmark

We describe how it is possible for a group of hospitals to implement both distributed and integrated electronic patient encounters with high performance and availability. We also describe how it is possible in such a system to implement approximated ACID (atomicity, consistency, isolation and durability) properties by using the countermeasure transaction model. this is used to implement recovery, and approximated concurrency control.

关键词： Availability Transaction databases Delay Distributed databases Hospitals Distributed computing

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Extensible Data Management in the middle-tier 12

Extensible Data Management in the middle-tier

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12th International Workshop on Research Issues in Data Engineering - Engineering E-Commerce/E-Business Systems

作者： Cooper, BF Sample, N Franklin, MJ Olshansky, J Shadmon, M Cohen, L RightOrder Inc San Jose CA 95134 USA

ISBN: (纸本)0769514804

Current data management solutions are optimized for intra-enterprise, client-server applications. they depend on predictability, predefined structure, and universal administrative control, and cannot easily cope with change and lack of structure. However, modern e-commerce applications are dynamic, unpredictable, organic, and decentralized, and require adaptability. eXtensible Data Management (XDM) is a new approach that enables rapid development and deployment of networked, data-intensive services by providing semantically-rich, high-performance middle-tier data management, and allows heterogeneous data front different sources to be accessed in a uniform manner. Here, we discuss how middle tier extensible data management can benefit an enterprise, and present technical details and examples from the Index Fabric, an XDM engine we have implemented.

关键词： Application software computer architecture computer science Data engineering Distributed computing Electronic commerce Engines Fabrics Technology management Time to market

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Portals 3.0: Protocol building blocks for low overhead communication 16

Portals 3.0: Protocol building blocks for low overhead commu...

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16th International Parallel and Distributed Processing symposium, IPDPS 2002

作者： Brightwell, R. Riesen, R. Lawry, B. Maccabe, A.B. Sandia National Laboratories Scalable Computing Systems Department PO Box 5800 AlbuquerqueNM87185-1110 United States University of New Mexico Computer Science Department FEC 313 AlbuquerqueNM87131 United States

ISBN: (纸本)0769515738

this paper describes the evolution of the Portals message passing architecture and programming interface from its initial development on tightly-coupled massively parallel platforms to the current implementation running on a 1792-node commodity PC Linux cluster. Portals provides the basic building blocks needed for higher-level protocols to implement scalable, low-overhead communication. Portals has several unique characteristics that differentiate it from other high-performance system-area data movement layers. this paper discusses several of these features and illustrates how they can impact the scalability and performance of higher-level message passing protocols. © 2002 IEEE.

关键词： massively parallel message passing network protocol os bypass workstation cluster

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Infrastructure, requirements and applications for e-Science

Infrastructure, requirements and applications for e-Science

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International symposium on computer architecture and high performance computing (SBAC-PAD)

作者： R. Perrott School of Computer Science Queen''s University Belfast UK

Recent developments in the international arena has meant the technology is now mature enough to bring together those required for the implementation of a grid computing facility. this paper examines the requirements a... 详细信息

关键词： Grid computing Internet Web sites Data mining Distributed computing Europe Business computer networks Collaboration Computational modeling

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Optimal code size reduction for software-pipelined and unfolded loops

Optimal code size reduction for software-pipelined and unfol...

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15th International symposium on System Synthesis

作者： Zhuge, Qingfeng Xiao, Bin Shao, Zili Sha, Edwin H.-M. Chantrapornchai, Chantana Department of Computer Science University of Texas at Dallas Richardson TX 75083 United States Faculty of Science Silpakorn University Nakorn Pathom 73000 Thailand

Software pipelining and unfolding are commonly used techniques to increase parallelism for DSP applications. However, these techniques expand the code size of the application significantly. For most DSP systems with limited memory resources, code size becomes one of the most critical concerns for the high-performance applications. In this paper, we present the code size reduction theory based on retiming and unfolding concepts. We propose a code size reduction framework to achieve the optimal code size of software-pipelined and unfolded loops by using conditional registers. the experimental results on several well-know benchmarks show the effectiveness of our code size reduction technique in controlling the code size of optimized loops.

关键词： Program compilers

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Designing 3-D nonlinear diffusion filters for high performance cluster computing

Designing 3-D nonlinear diffusion filters for high performan...

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24th German Association for Pattern Recognition symposium, DAGM 2002

作者： Bruhn, Andrés Jakob, Tobias Fischer, Markus Kohlberger, Timo Weickert, Joachim Brüning, Ulrich Schnörr, Christoph Mathematical Image Analysis Group Mathematics and Computer Science Saarland University Building 27.1 Saarbrücken66041 Germany Computer Architecture Group Department of Mathematics and Computer Science University of Mannheim Mannheim68131 Germany Computer Vision Graphics and Pattern Recognition Group Department of Mathematics and Computer Science University of Mannheim Mannheim68131 Germany

ISBN: (纸本)354044209X

this paper deals with parallelization and implementation aspects of PDE based image processing models for large cluster environments with distributed memory. As an example we focus on nonlinear isotropic diffusion filtering which we discretize by means of an additive operator splitting (AOS). We start by decomposing the algorithm into small modules that shall be parallelized separately. For this purpose image partitioning strategies are discussed and their impact on the communication pattern and volume is analyzed. Based on the results we develop an algorithmic implementation with excellent scaling properties on massively connected low latency networks. Test runs on a high–end Myrinet cluster yield almost linear speedup factors up to 209 for 256 processors. this results in typical denoising times of 0.5 seconds for five iterations on a 256 × 256 × 128 data cube. © Springer-Verlag Berlin Heidelberg 2002.

关键词： Cluster computing

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An EPIC processor with pending functional units

An EPIC processor with pending functional units

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4th International symposium on high performance computing, ISHPC 2002

作者： Carter, Lori Chuang, Weihaw Calder, Brad Department of Computer Science and Engineering University of California San Diego United States

ISBN: (纸本)354043674X

the Itanium processor, an implementation of an Explicitly Parallel Instruction computing (EPIC) architecture, is an in-order processor that fetches, executes, and forwards results to functional units in-order. the architecture relies heavily on the compiler to expose Instruction Level Parallelism (ILP) to avoid stalls created by in-order processing. the goal of this paper is to examine, in small steps, changing the in-order Itanium processor model to allow execution to be performed out-of-order. the purpose is to overcome memory and functional unit latencies. To accomplish this, we consider architecture with Pending Functional Units (PFU). the PFU architecture assigns/schedules instructions to functional units in-order. Instructions sit at the pending functional units until their operands become ready and then execute out-of-order. While an instruction is pending at a functional unit, no other instruction can be scheduled to that functional unit. We examine several PFU architecture designs. the minimal design does not perform renaming, and only supports bypassing of non-speculative result values. We then examine making PFU more aggressive by supporting speculative register state, and then finally by adding in register renaming. We show that the minimal PFU architecture provides on average an 18% speedup over an in-order EPIC processor and produces up to half of the speedup that would be gained using a full out-of-order architecture. © Springer-Verlag Berlin Heidelberg 2002.

关键词： Program compilers

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