the paper presents a pragmatic scan partitioning architecturethat allows less than perfect scan design in highperformance, VLSI circuits to cost-effectively achieve test development and manufacturing test goals. the...
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the paper presents a pragmatic scan partitioning architecturethat allows less than perfect scan design in highperformance, VLSI circuits to cost-effectively achieve test development and manufacturing test goals. the paper then describes an implementation of the architecture on Compaq's Alpha 21364 microprocessor.
Error propagation is a central problem in grid computing. We re-learned this while adding a Java feature to the Condor computational grid. Our initial experience withthe system was negative, due to the large number o...
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Error propagation is a central problem in grid computing. We re-learned this while adding a Java feature to the Condor computational grid. Our initial experience withthe system was negative, due to the large number of new ways in which the system could fail. To reason about this problem, we developed a theory of error propagation. Central to our theory is the concept of an error's scope, defined as the portion of a system that it invalidates. Withthis theory in hand, we recognized that the expanded system did not properly consider the scope of errors it discovered. We modified the system according to our theory, and succeeded in making it a more robust platform for distributed computing.
Raising the level of abstraction is widely seen as the solution for closing the productivity gap in system design. they key for the success of this approach, however, axe well-defined abstraction levels and models. In...
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Raising the level of abstraction is widely seen as the solution for closing the productivity gap in system design. they key for the success of this approach, however, axe well-defined abstraction levels and models. In this paper, we present such system level semantics to cover the system design process. We define properties and features of each model. Formalization of the flow enables design automation for synthesis and verification to achieve the required productivity gains. through customization, the semantics allow creation of specific design methodologies. We applied the concepts to system languages SystemC and SpecC. Using the example of a JPEG encoder, we will demonstrate the feasibility and effectiveness of the approach.
this work presents an overview of the methodology used to develop dynamic reconfiguration mechanisms for the image processor called DRIP. these techniques included in the design flow try to identify the most effective...
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this work presents an overview of the methodology used to develop dynamic reconfiguration mechanisms for the image processor called DRIP. these techniques included in the design flow try to identify the most effective datapath and control architectures to overcome time-consuming reconfiguration delays and to provide a higher level of programmability to the reconfigurable system.
We present NeST a flexible software-only storage appliance designed to meet the storage needs of the Grid. NeST has three key features that make it well-suited for deployment in a Grid environment. First, NeST provide...
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We present NeST a flexible software-only storage appliance designed to meet the storage needs of the Grid. NeST has three key features that make it well-suited for deployment in a Grid environment. First, NeST provides a generic data transfer architecturethat supports multiple data transfer protocols (including GridFTP and NFS), and allows for the easy addition of new protocols. Second, NeST is dynamic, adapting itself on-the-fly so that it runs effectively on a wide range of hardware and software platforms. third, NeST is Grid-aware, implying that features that are necessary for integration into the Grid, such as storage space guarantees, mechanisms for resource and data discovery, user authentication, and quality of service, are a part of the NeST infrastructure.
State-of-the-art run-time systems are a poor match to diverse, dynamic distributed applications because they are designed to provide support to a wide variety of applications, without much customization to individual ...
Modulo multiplication of long integers (/spl ges/ 1024 bits) is the major operation of many public-key cryptosystems like RSA or Diffie-Hellman. the efficient implementation of modulo arithmetic is a challenging task,...
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Modulo multiplication of long integers (/spl ges/ 1024 bits) is the major operation of many public-key cryptosystems like RSA or Diffie-Hellman. the efficient implementation of modulo arithmetic is a challenging task, in particular on smart cards due to their constrained resources and relatively slow clock frequency. We present the concept of an application-specific instruction set extension (ISE) for long integer arithmetic. We introduce an optimized multiply-and-accumulate (MAC) unit that makes it possible to compute a/spl times/b+c+d with only one instruction, whereby a, b, c, d are single-precision words (unsigned integers). this additional instruction is simple to incorporate into common RISC architectures like the MIPS32. Experimental results show that the inner-product operation of a multiple-precision multiplication can be accelerated by a factor of two without increasing the processor's clock frequency. We also estimate the execution time of a 1024-bit modulo exponentiation assuming that this special MAC instruction was made available. the proposed ISE is an alternative solution to a crypto co-processor especially for multi-application smart cards (e.g., Java cards) with an embedded 32-bit RISC core.
Beowulf clusters, on face value, offer the potential of a viable cost effective alternative for the provision of highperformancecomputing. In this paper we compare the performance of Beowulf clusters built from comm...
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Beowulf clusters, on face value, offer the potential of a viable cost effective alternative for the provision of highperformancecomputing. In this paper we compare the performance of Beowulf clusters built from commodity "off the shelf" components in the support of major research and production codes, with current high-end hardware such as the IBM SP, Compaq AlphaServer SC and SGI Origin 3800. the results concentrate on the application area of computational chemistry. Benchmark data on six commodity-based systems (CS1-CS6) featuring Intel, AMD Athlon and Alpha CPU architectures coupled to traditional Beowulf interconnect, such as Myrinet and Ethernet, are presented. Furthermore, we provide performance data on systems utilising the Quadrics QSNet interconnect technology, and initial results from a prototype of the Cray Supercluster.
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