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Enforcing resource sharing agreements among distributed server clusters

Enforcing resource sharing agreements among distributed serv...

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International symposium on Parallel and Distributed Processing (IPDPS)

作者： Tao Zhao V. Karamcheti Department of Computer Science Courant Institute of Mathematical Science New York University USA

Future scalable, high throughput, and high performance applications are. likely to execute on platforms constructed by clustering multiple autonomous distributed servers, with resource access governed by agreements between the owners and users of these servers. Such systems raise several new resource management challenges, chief amongst which is the enforcement of agreements to ensure that, despite the distributed nature of both requests and resources, user requests only receive a predetermined share of the aggregate resource. Current solutions only enforce such agreements at a coarse granularity and in a centralized fashion, limiting their applicability. this paper presents an architecture for the distributed enforcement of resource sharing agreements. Our approach exploits a uniform application-independent representation of agreements, and combines it with efficient tune-window based coordinated queuing algorithms running on multiple nodes. We have successfully implemented this general strategy in two different network layers: a Layer-7 HTTP redirector and a Layer-4 IP packet redirector; which redirect connection requests from distributed clients to a cluster of distributed servers. Our measurements of both implementations verify that our approach is general and effective.

关键词： Resource management Network servers Web server Costs Aggregates Peer to peer computing computer science Application software Clustering algorithms throughput

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Communication speed selection for embedded systems with networked voltage-scalable processors

Communication speed selection for embedded systems with netw...

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International Workshop on Hardware/Software Codesign (CODES)

作者： Jinfeng Liu P.H. Chou N. Bagherzadeh Department of Electrical & Computer Engineering University of California Irvine CA USA

high-speed serial network interfaces are gaining wide use in connecting multiple processors and peripherals in modem embedded systems, thanks to their size advantage and power efficiency. Many such interfaces also support multiple data rates, and this ability is opening a new dimension in the power/performance trade-offs between communication and computation on voltage scalable embedded processors. To minimize energy consumption in these networked architectures, designers must not only perform functional partitioning but also carefully balance the speeds between communication and computation, which compete for time and energy. Minimizing communication power without considering computation may actually lead to higher energy consumption at the system level due to elongated on-time as well as lost opportunities for dynamic voltage scaling on the processors. We propose a speed selection methodology for globally optimizing the energy consumption in embedded networked architectures. We formulate a multidimensional optimization problem by modeling communication dependencies between processors and their timing budgets. this enables engineers to systematically solve the problem of optimal speed selection for global energy reduction. We demonstrate the effectiveness of our speed selection approach with an image processing application mapped onto a multi-processor architecture with a multi-speed Ethernet.

关键词： Embedded system Energy consumption computer architecture Network interfaces Joining processes Modems computer interfaces Embedded computing Voltage computer networks

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Tarantula: a vector extension to the alpha architecture

Tarantula: a vector extension to the alpha architecture

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Annual International symposium on computer architecture, ISCA

作者： R. Espasa F. Ardanaz J. Emer S. Felix J. Gago R. Gramunt I. Hernandez T. Juan G. Lowney M. Mattina A. Seznec Compaq–UPC Microprocessor Lab Universitat Politècnica Catalunya Barcelona Spain Alpha Development Group Compaq Computer Corporation Shrewsbury MA Compaq UPC Microprocessor Laboratory Universitat Poliltècnica de Catalunya Barcelona Spain Alpha Development Group Compaq Computer Corporation Shrewsbury MA USA

Tarantula is an aggressive floating point machine targeted at technical, scientific and bioinformatics workloads, originally planned as a follow-on candidate to the EV8 processor. Tarantula adds to the EV8 core a vector unit capable of 32 double-precision flops per cycle. the vector unit fetches data directly from a 16 MByte second level cache with a peak bandwidth of sixty four 64-bit values per cycle. the whole chip is backed by a memory controller capable of delivering over 64 GBytes/s of raw bandwidth. Tarantula extends the Alpha ISA with new vector instructions that operate on new architectural state. Salient features of the architecture and implementation are: (1) it fully integrates into a virtual-memory cache-coherent system without changes to its coherency protocol, (2) provides high bandwidth for non-unit stride memory accesses, (3) supports gather/scatter instructions efficiently, (4) fully integrates with the EV8 core with a narrow, streamlined interface, rather than acting as a co-processor (5) can achieve a peak of 104 operations per cycle, and (6) achieves excellent "real-computation" per transistor and per watt ratios. Our detailed simulations show that Tarantula achieves an average speedup of 5X over EV8, out of a peak speedup in terms of flops of 8X. Furthermore, performance on gather/scatter intensive benchmarks such as Radix Sort is also remarkable: a speedup of almost 3X over EV8 and 15 sustained operations per cycle. Several benchmarks exceed 20 operations per cycle.

关键词： Bandwidth Instruction sets Scattering Communication system control computer architecture Bioinformatics CMOS technology Microprocessors Access protocols Coprocessors

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Vector vs. superscalar and VLIW architectures for embedded multimedia benchmarks

Vector vs. superscalar and VLIW architectures for embedded m...

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IEEE/ACM International symposium on Microarchitecture (MICRO)

作者： C. Kozyrakis D. Patterson Electrical Engineering Department University of Stanford USA Computer Science Division University of California Berkeley USA

Multimedia processing on embedded devices requires an architecture that leads to high performance, low power consumption, reduced design complexity, and small code size. In this paper, we use EEMBC, an industrial benchmark suite, to compare the VIRAM vector architecture to superscalar and VLIW processors for embedded multimedia applications. the comparison covers the VIRAM instruction set, vectorizing compiler and the prototype chip that integrates a vector processor with DRAM main memory. We demonstrate that executable code for VIRAM is up to 10 times smaller than VLIW code and comparable to /spl times/86 CISC code. the simple, cache-less VIRAM chip is 2 times faster than a 4-way superscalar RISC processor that uses a 5 times faster clock frequency and consumes 10 times more power VIRAM is also 10 times faster than cache-based VLIW processors. Even after manual optimization of the VLIW code and insertion of SIMD and DSP instructions, the single-issue VIRAM processor is 60% faster than 5-way to 8-way VLIW designs.

关键词： VLIW Energy consumption Prototypes Vector processors Reduced instruction set computing Clocks Frequency Manuals Design optimization Digital signal processing chips

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high-level synthesis with SIMD units

High-level synthesis with SIMD units

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Asia and South Pacific Design Automation Conference

作者： V. Raghunathan A. Raghunathan M.B. Srivastava M.D. Ercegovac Department of Electrical Engineering University of California Los Angeles CA USA C & C Research Laboratories NEC USA Inc. Princeton NJ USA Department of Computer Science University of California Los Angeles CA USA

ISBN: (纸本)0769514413

this paper presents novel techniques to integrate the use of Single Instruction Multiple Data (SIMD) functional units in a high-level synthesis (HLS) design methodology. SIMD functional units can be configured to operate in one or more SIMD modes, in which they process multiple sets of smaller bitwidth operands in parallel. Conceptually, the use of SIMD functional units enables HLS to (i) exploit parallelism to a higher degree without using additional resources, (ii) improve resource utilization by enabling hardware re-use at a fine-grained level, and (iii) improve energy efficiency for a given area and/or performance constraint. We illustrate the issues involved in performing high-level synthesis with SIMD functional units, and discuss how algorithms involved in a typical high-level synthesis flow can be enhanced to result in maximal performance and energy improvements. these techniques are not restricted to specific high-level synthesis tools/algorithms, and can be plugged into any generic high-level synthesis system.

关键词： high level synthesis computer architecture Hardware Space exploration Application software Arithmetic Logic Circuits computer science high performance computing

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Prospects for single molecule information devices

Prospects for single molecule information devices

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European Conference on Solid-State Circuits (ESSCIRC)

作者： Y. Wada Advanced Research Laboratory CREST JST Hitachi and Limited Japan

Present information technologies use semiconductor devices and magnetic/optical discs, however, they are all foreseen to face fundamental limitations within a decade. therefore, superseding devices are required for the next paradigm of high performance information technologies. this paper describes prospects for single molecule devices suitable for future information technologies. Possible four milestones for realizing the Peta(10 15 )/Exa(10 18 )-floating operations per second (FLOPS) personal molecular supercomputer are proposed. Current status and necessary technologies of the first milestone are described, and necessary technologies for the next three milestones are also discussed.

关键词： computer architecture Information technology Information processing MOSFETs Quantum computing Microprocessors Semiconductor devices Magnetic semiconductors Humans Semiconductor materials

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Vacuum packing: extracting hardware-detected program phases for post-link optimization

Vacuum packing: extracting hardware-detected program phases ...

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IEEE/ACM International symposium on Microarchitecture (MICRO)

作者： R.D. Barnes E.M. Nystrom M.C. Merten W.W. Hwu Center for Reliable and High-Performance Computing Department of Electical and Computer Engineering University of Illinois Urbana-Champaign USA

this paper presents Vacuum Packing, a new approach to profile-based program optimization. Instead of using traditional aggregate or summarized execution profile weights, this approach uses a transparent hardware profiler to automatically detect execution phases and record branch profile information for each new phase. the code extraction algorithm then produces code packages that are specially formed for their corresponding phases. the algorithm compensates for the incomplete and often incoherent branch profile information that arises due to the nature of hardware profilers. the technique avoids unnecessary code replication by focusing on hot code, making efficient connections between the original code and the new code, linking code packages at select points to facilitate phase transitions, and providing a platform for efficient optimization. We demonstrate that using a concise set of profile information from a hardware profiler, we can generate code packages, specialized for each phase of execution, that capture more than 80% of the average total program execution. We further show that the approach is very effective in extracting code regions that capture the phasing behavior of programs, that the code size increase is moderate, and that the code regions benefit from sample optimizations.

关键词： Data mining Packaging Reliability engineering Aggregates Phase detection Joining processes computer architecture Java Emulation Libraries

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Specification, modeling and design tools for system-on-chip

Specification, modeling and design tools for system-on-chip

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Asia and South Pacific Design Automation Conference

作者： L. Lavagno S. Dey R. Gupta Cadence Berkeley Laboratories USA University of California San Diego USA University of California Irvine USA

ISBN: (纸本)0769514413

Summary form only given. Illustrates first the languages and models of computation available to the system-level. designer to capture precisely and unambiguously requirements. We discuss for what application domain and platform each language is most appropriate, focusing mostly on platform-independent languages and MOCs, since they support the greatest freedom in mapping choice. We will then discuss how the architecture of the platform, and the services it offers to the application designer, can also be formally and compactly captured and specified. We will show how the mapping paradigm can be used to select an implementation for the functional blocks and their communication, and how simulation and implementation methods can be derived automatically. In particular, we will describe how software estimation and synthesis for reactive real-time systems can be competitive with hand design, while retaining the ease of re-use typical of high-level specifications. In the next part of the tutorial, we will establish the importance of on-chip communication architectures in determining the performance of System-on-Chips (SoCs). We will track several on-chip communication architectures that are in use today.

关键词： System-on-a-chip computer architecture Embedded system performance analysis Design methodology Network-on-a-chip Power system modeling Laboratories Pervasive computing Costs

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high-performance architectures for elementary function generation

High-performance architectures for elementary function gener...

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15th IEEE symposium on computer Arithmetic (ARIth-15 2001)

作者： Cao, J Wei, BWY Cheng, J San Jose State Univ Dept Elect Engn San Jose CA 95192 USA

ISBN: (纸本)0769511503

high-speed elementary function generation is crucial to the performance of many DSP applications. this paper presents three new architectures for generating elementary functions with IEEE single precision using second-order interpolation. these designs have been developed through a. combination of architectural innovations and algorithm developments. they represent a range of trade-off between the use of memory modules and computational circuits Our most memory intensive architecture uses one third less memory than alternative schemes while incurring no time penalty and minimal additional circuitry.

关键词： Digital arithmetic

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computer arithmetic - A processor architect's perspective

Computer arithmetic - A processor architect's perspective

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15th IEEE symposium on computer Arithmetic (ARIth-15 2001)

作者： Lee, RB Princeton Univ Princeton NJ 08544 USA

ISBN: (纸本)0769511503

the Instruction Set architecture (ISA) of a programmable processor is the native language of the machine. It defines the set of operations and resources that are optimized for that computer, information appliance or server. It is based on the workload characterization of the types of software expected to run on that computer. Unfortunately, the workload characterization upon which microprocessor ISA choices have been made has not kept up with the changing nature of general-purpose computations and communications. this has resulted in a plethora of special-purpose hardware chips and boards for these new information processing paradigms, and a general misunderstanding that software running on programmable processors cannot achieve certain performance, cost or power levels. Microprocessors that attain high performance levels in the new processing areas tend to have complex microarchitecture and very fast cycle times, both of which result in high cost and power. Actually, much faster, lower cost and lower power computations can be achieved by optimizing the Instruction-Set architecture of the processor for these new information-processing paradigms. In this talk, we discuss new ISA features, which address the increasing need for pervasive secure information processing and ubiquitous multimedia information processing. In particular, we discuss new arithmetic operations that are very useful for fast software cryptography or the processing of multimedia information. For example, we discuss novel permutation instructions and methodologies for achieving arbitrary permutations of bits and subwords in n-bit words. these are needed for fast symmetric-key cryptography and in multimedia applications. We also discuss interesting forms of saturation arithmetic and their applications, and other new types of computer arithmetic. the realization of these new arithmetic operations calls for innovative logic and circuit implementations of new functional units, or imaginatively enhanced

关键词： Digital arithmetic

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