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performance Evaluation of QoS in Dynamic Ran Slicing of 5G Network 8th

Performance Evaluation of QoS in Dynamic Ran Slicing of 5G N...

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8th International Conference on Emerging Research in computing, Information, Communication and Applications, ERCICA 2023

作者： Hegde, Parikshit P. Shahapur, Lavanya Ajay Kushal, B. Tomar, Kushagra Pujari, Pragathi Jannu, Ashwini R. Computer Science Department KLE Technological University Hubballi India

ISBN: (纸本)9789819976218

Access to the Internet is growing exponentially due to its ease of usability, flexibility, and lowering data plans. the diverse network service requirements encourage mobile operators to look for mechanisms that facilitate efficient use of network infrastructure, so that it can reduce the operational and expenditure costs. Use cases like the video streaming services requires high bandwidth, autonomous driving and remote medical surgery requires low latency, and various IoT applications work with low bandwidth to cater to the users needs. We simulate the RAN slicing using an emulator called eXP-RAN which effectively manages the allocation of different network resources to the created slices. the infrastructure, slicing, and service layers are the three distinct layers in the proposed system architecture. the isolation and abstraction of the network resources is also applied to the created slices by this emulator. © 2024, the Author(s), under exclusive license to Springer Nature Singapore Pte Ltd.

关键词： Base stations eXP-RAN emulator Forwarding nodes MEC hosts Mobile network operator Network slicing Radio resource Ran slicing Video streaming services

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Special Session: Software-Based Self-Test Generation for RISC-V - Stuck-At Generation, Functional Cell-Aware Untestability, and FPGA Demonstration 37

Special Session: Software-Based Self-Test Generation for RIS...

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37th IEEE International symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2024

作者： Faller, Tobias Deligiannis, Nikolaos I. Cantoro, Riccardo Reorda, Matteo Sonza Becker, Bernd University of Freiburg Department of Computer Science Freiburg Germany Turin Italy

ISBN: (纸本)9798350366884

Software-Based Self-Tests (SBST) allow at-speed, native online-testing of processors by running software programs on the processor core, requiring no Design for Testability (DfT) infrastructure. Traditionally, the generation of such SBST programs requires time-consuming manual labor in combination with in-depth knowledge of the processor's architecture to target hard-to-test faults. In contrast, encoding the SBST generation task as a Bounded Model Checking (BMC) problem allows using sophisticated, state-of-the-art BMC solvers to automatically generate an SBST for a given fault model and, moreover, prove the untestability of certain faults. During generation, a constraint specification Validity Checker Module (VCM) ensures correct, functional SBST behavior. the operating conditions in the field and the processor and system-specific constraints are included in this specification, too, in a highly configurable form. In this paper, we present an intermediate VCM interface to generalize the functional constraint specification on RISC-V processors and apply it to two in-field test-related areas. First, we perform SBST generation for detecting permanent hardware faults (stuck-at) in the ALU and the register file of multiple RISC-V processors. Second, we perform functional untestability analysis for the cell-aware fault model on the same processors. Finally, we synthesize the largest processor core on an FPGA with user-controlled fault injection to demonstrate the subsequent detection via the generated stuck-at SBST to a non-technical audience. © 2024 IEEE.

关键词： Software testing

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Improving EEG-based Emotion Recognition using DCGAN with MobileNet

Improving EEG-based Emotion Recognition using DCGAN with Mob...

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International Conference on computing and Networking Technology (ICCNT)

作者： Shashank Kaushik Gyanendra K. Verma Department of Information Technology National Institute of Technology Raipur India

ISBN: (数字)9798350370249

ISBN: (纸本)9798350370270

Emotions play a crucial role in influencing human behaviour, decision-making, and task performance. EEG signals are preferred for emotion recognition due to their non-invasive nature, cost-effectiveness, and high temporal resolution. CNNs have emerged as effective tools for emotion recognition specifically with image datasets. their strength lies in automatically extracting intricate features from images, aiding in identifying subtle facial expression details that convey emotions. Transfer Learning (TL) allows precise parameter learning and specialized CNN configurations. We utilized the fine-tuning of a pre-trained CNN model, MobileNet, to classify four emotional states. the experimental outcomes demonstrated ${9 9. 8 9 \%, 9 8 \%}$ and $95.75 \%$ accuracy with DCGAN with MobileNet architecture which proves its usefulness in emotion recognition.

关键词： Emotion recognition Accuracy Image resolution Computational modeling Transfer learning computer architecture Brain modeling Feature extraction Robustness Signal resolution

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IDS-DEEP: a strategy for selecting the best IDS for Drones with heterogeneous EmbEdded Platforms

IDS-DEEP: a strategy for selecting the best IDS for Drones w...

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International symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Louis Morge-Rollet Camélia Slimani Laurent Lemarchand Frédéric Le Roy David Espes Jalil Boukhobza ENSTA Bretagne Lab-STICC CNRS UMR 6285 Brest France Université de Bretagne Occidentale

ISBN: (数字)9798350356168

ISBN: (纸本)9798350356175

Drone swarms are increasingly being used to perform critical missions, such as inspection of ports and industrial installations. Each drone can embed heterogeneous execution platforms to successfully perform various computing tasks. As security threats may disrupt the progression of the drone mission, network intrusion detection systems (IDSs) are used. they analyze network traffic to detect malicious behaviors, but generally rely on resource-hungry machine learning models. To adapt to the dynamic nature of the mission, it is necessary to embed several IDS implementations leveraging heterogeneous computing resources of the drone and presenting a trade-off between security, throughput, and energy consumption. To address this issue, we propose, in this paper, an end-to-end flow composed of an offline phase to choose the IDS implementations to embed on the drone platform and an online phase to select the best implementation online considering the mission conditions at a given time. We devised a MILP formulation for the offline phase that proved to provide a 89.41% better Inverted Generational Distance (IGD) than a random choice. For the online phase, we investigated several solutions and designed a novel optimized strategy that proved to be around 16.76 times faster than TOPSIS while having comparable QoS metrics.

关键词： Measurement high performance computing Network intrusion detection Telecommunication traffic Quality of service Machine learning Inspection throughput Security Drones

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Detecting DDoS Attacks in Software Defined Networks (SDNs) with Random Forests 2023

Detecting DDoS Attacks in Software Defined Networks (SDNs) w...

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15th International Conference on Contemporary computing, IC3 2023

作者： Murtuza, Shariq Asawa, Krishna Department of Computer Science & Engineering and Information Technology Jaypee Institute of Information Technology Uttar Pradesh Noida India

ISBN: (纸本)9798400700224

the Software-Defined Networking (SDN) paradigm empowers network operators to manage and coordinate network activities, allowing for greater flexibility and dynamic updating of switching tables. Over time, more and more service providers are integrating SDN into their core network infrastructure, recognizing the benefits of its robustness and adaptability. In the face of the rapid expansion of high-speed consumer Internet, data centers are increasingly migrating their internal networks to SDN-based backbones, which offer enhanced performance and scalability. SDN is widely projected to become the technology of the future, with many of the top Fortune 500 companies already implementing SDN in some form or another to meet their core network requirements. As a result, network devices, Internet service providers, content delivery networks, and data centers will increasingly be linked to high-performing SDNs and will communicate via them. the ubiquitous penetration of SDN-based networks, coupled with the multitude of user devices connected to them, is critical for the consumers of these services. However, like traditional networks, Software Defined networks are vulnerable to Denial of Service attacks, which target the availability of a service connected to the network. thus, it is essential to develop effective strategies for identifying and mitigating such attacks to ensure the integrity and reliability of SDN-based networks. © 2023 ACM.

关键词： Denial-of-service attack

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Analysing Mechanisms for Virtual Channel Management in Low-Diameter Networks

Analysing Mechanisms for Virtual Channel Management in Low-D...

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International symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Alejandro Cano Cristóbal Camarero Carmen Martínez Ramón Beivide Computer and Electronics Department Universidad de Cantabria Santander Spain

To interconnect their growing number of servers, current supercomputers and data centers are starting to adopt low-diameter networks, such as HyperX, Dragonfly and Dragonfly+. these emergent topologies require balancing the load over their links and finding suitable non-minimal routing mechanisms for them becomes particularly challenging. the Valiant load balancing scheme is a very popular choice for non-minimal routing. Evolved adaptive routing mechanisms implemented in real systems are based on this Valiant scheme. All these low-diameter networks are deadlock-prone when non-minimal routing is employed. Routing deadlocks occur when packets cannot progress due to cyclic dependencies. therefore, developing efficient deadlock-free packet routing mechanisms is critical for the progress of these emergent networks. the routing function includes the routing algorithm for path selection and the buffers management policy that dictates how packets allocate the buffers of the switches on their paths. For the same routing algorithm, a different buffer management mechanism can lead to a very different performance. Moreover, certain mechanisms considered efficient for avoiding deadlocks, may still suffer from hard to pinpoint instabilities that make erratic the network response. this paper focuses on exploring the impact of these buffers management policies on the performance of current interconnection networks, showing a 90% of performance drop if an incorrect buffers management policy is used. Moreover, this study not only characterizes some of these undesirable scenarios but also proposes practicable solutions.

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EQC: Ensembled Quantum computing for Variational Quantum Algorithms 22

EQC: Ensembled Quantum Computing for Variational Quantum Alg...

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49th IEEE/ACM Annual International symposium on computer architecture (ISCA)

作者： Stein, Samuel Wiebe, Nathan Ding, Yufei Bo, Peng Kowalski, Karol Baker, Nathan Ang, James Li, Ang Pacific Northwest Natl Lab Richland WA 99354 USA Univ Calif Santa Barbara Santa Barbara CA USA Univ Toronto Toronto ON Canada

ISBN: (纸本)9781450386104

Variational quantum algorithm (VQA), which is comprised of a classical optimizer and a parameterized quantum circuit, emerges as one of the most promising approaches for harvesting the power of quantum computers in the noisy intermediate scale quantum (NISQ) era. However, the deployment of VQAs on contemporary NISQ devices often faces considerable system and time-dependant noise and prohibitively slow training speeds. On the other hand, the expensive supporting resources and infrastructure make quantum computers extremely keen on high utilization. In this paper, we propose a virtualized way of building up a quantum backend for variational quantum algorithms: rather than relying on a single physical device which tends to introduce ever-changing device-specific noise with less reliable performance as time-since-calibration grows, we propose to constitute a quantum ensemble, which dynamically distributes quantum tasks asynchronously across a set of physical devices, and adjusts the ensemble configuration with respect to machine status. In addition to reduced machine-dependant noise, the ensemble can provide significant speedups for VQA training. With this idea, we build a novel VQA training framework called EQC - a distributed gradient-based processor-performance-aware optimization system - that comprises: (i) a system architecture for asynchronous parallel VQA cooperative training;(ii) an analytical model for assessing the quality of a circuit output concerning its architecture, transpilation, and runtime conditions;(iii) a weighting mechanism to adjust the quantum ensemble's computational contribution according to the systems' current performance. Evaluations comprising 500K times' circuit evaluations across 10 IBMQ NISQ devices using a VQE and a QAOA applications demonstrate that EQC can attain error rates very close to the most performant device of the ensemble, while boosting the training speed by 10.5x on average (up to 86x and at least 5.2x). EQC is available at

关键词： Quantum computing Variational Quantum Algorithms Distributed computing

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Effect of Parameter Drift on the Accuracy of Analog CNN Accelerators

Effect of Parameter Drift on the Accuracy of Analog CNN Acce...

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Midwest symposium on Circuits and Systems (MWSCAS)

作者： Michael Keyser Farzad Ordubadi Armin Tajalli Department of Electrical and Computer Engineering University of Utah Salt Lake City Utah

ISBN: (数字)9798350387179

ISBN: (纸本)9798350387186

Challenges and opportunities in the design of high-precision analog machine learning accelerators will be studied. An analytical approach has been proposed to evaluate the effect of process variations and mismatch on the performance of Convolutional Neural Networks (CNNs). A sample CNN based on the VGG11 architecture, modified to classify the CIFAR-10 dataset, was developed and used as part of this study. the analysis carried out in this work reveals that despite the inherent sensitivity of analog circuits to process variations and mismatch, certain computational layers in a CNN show high sensitivity to drift. As a result, proper calibration techniques can be used to target the most sensitive part of the computing system, and mitigate the effects of process variations and mismatch, thus maintaining a high overall system performance and accuracy. Such an approach will enable the development of machine learning accelerators based on analog topologies that are energy-efficient and high-speed without compromising their accuracy.

关键词： performance evaluation Accuracy Sensitivity System performance Machine learning Network architecture Topology

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Description of the Basic Tools of Augmented Reality in the Design of computer Models in Unity 15th

Description of the Basic Tools of Augmented Reality in the D...

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15th EAI International Conference on Automation and Control in theory and Practice, ARTEP 2023

作者： Hrehova, Stella Matisková, Darina Faculty of Manufacturing Technologies with the seat in Prešov Technical University of Košice Prešov Slovakia

ISBN: (纸本)9783031319662

the creation of computer models is an integral part of the design and analysis of various processes. We can see them in almost all areas of our life. the individual procedures and methods used in these activities were constantly developed and improved over the years. Several activities played a major role in this, such as the rapid development of information technologies, not only in the field of software but especially in the field of hardware. With each passing year, we have more powerful devices at our disposal, which enable high efficiency and have the required performance. A related area in which rapid development has occurred is mobile devices, in which their operating systems and hardware enable the implementation of previously impossible programs. If we consider all these factors, it is understandable that new tools are used for simulations or computer models creation. the presented contribution aims to describe the possibilities of using the selected tools of the Unity and Vuforia development environments when using augmented reality elements in the computer model design. We will describe the insertion of an external robot model, the connection with the Vuforia environment, and the simple creation of animation without the need to create a script. © 2023, the Author(s), under exclusive license to Springer Nature Switzerland AG.

关键词： Augmented reality

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An Area-Efficient VLSI architecture with Ladner-Fischer PPA for high-Speed Pseudo-Random Bit Generation

An Area-Efficient VLSI Architecture with Ladner-Fischer PPA ...

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International Conference on computing and Networking Technology (ICCNT)

作者： Sakkthi Saranya P. Maran Sita Devi Bharatula B. Naresh Kumar Reddy Department of ECE Amrita School of Engineering Amrita Vishwa Vidyapeetham Chennai India Department of ECE NIT Tiruchirappalli Tiruchirappalli India

ISBN: (数字)9798350370249

ISBN: (纸本)9798350370270

Pseudorandom Bit Generation (PRBG) plays a crucial role in ensuring the security of cryptographic systems by generating random bit sequences using deterministic algorithms. the effectiveness of these systems hinges on the unpredictability of the cryptographic keys they generate. this study focuses on optimizing the efficiency of PRBG systems by addressing key factors such as speed, area utilization, and power consumption. Leveraging the parallel prefix adder (PPA) architecture, particularly the Laden-Fisher design, our proposed method aims to enhance the performance of PRBG implementations. We present a Verilog-based design implemented using Vivado 2023.1 targeting an Artix-7 FPGA platform. through this approach, we achieve rapid and reliable bit generation while effectively managing FPGA resources, ultimately enhancing the overall efficiency of PRBG systems.

关键词： Power demand computer architecture Very large scale integration Fasteners Generators Encryption Reliability Hardware design languages Adders Field programmable gate arrays

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