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Parallel retrograde analysis on different architecture

Parallel retrograde analysis on different architecture

引用

10th Annual IEEE International symposium on high performance Distributed computing

作者： Wu, R Beal, DF HP Laboratories Hewlett-Packard Company Palo Alto CA United States

ISBN: (纸本)0769512968

Retrograde analysis is an efficient exhaustive search method. It is a powerful tool that can be used in solving problems where end states have known values but starting states do not. It has been widely used to solve mathematically-precise games such as chess endgames, and is potentially usable in energy-minimization problems. With increasing computing power, both in speed and storage capacity, retrograde analysis will become more and more useful. this paper looks at successful applications to games, the challenges ahead, and the modifications that are required to utilize distributed hardware. the power and the usefulness of retrograde analysis are still limited by the computing resources one has access to. Today, the best sequential retrograde algorithms are capable of solving problems with about 109 states in a few hours on a standard personal computer Bigger problems need more powerful computers, or take much longer to solve, or are simply out of reach of today's technologies, Introducing parallelism to retrograde analysis is a natural way to attack the bigger problems. there are today three main architectures available for doing parallel retrograde analysis: namely Symmetric Multiprocessor systems, high-speed network based distributed systems, and Internet based distributed systems. In this paper, we discuss some of the key issues in doing parallel retrograde analysis on these different architectures. Technical challenges are addressed in detail, as well as some examples and proposals. these examples and proposals are drawn from various board games, but the ideas can be applied to other problem domains.

关键词： Distributed computer systems

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A video replacement policy based on revenue to cost ratio in amulticast tv-anytime system 15

A video replacement policy based on revenue to cost ratio in...

引用

15th International Parallel and Distributed Processing symposium, IPDPS 2001

作者： Zhou, Xiaobo Xu, Cheng-Zhong Burchard, L.O. Lüling, R. Department of Computer Science Department of Elec. and Computer Engineering Wayne State University DetroitMI48202 United States University of Paderborn PaderbornD-33102 Germany

ISBN: (纸本)0769509908

this paper analyzes a tree hierarchical network architecture employing video caching and multicasting capacity to support a large scale Video-on-Demand service called TV-Anytime. the host servers are connected to other host servers which collectively store all the videos in the system. the proxy servers are located close to customers and are able to store the most popular videos in an adaptive way. Considering many uncertainties in the future demands for videos, we propose an on-line video replacement policy based on a revenue to cost ratio, with an objective of maximizing the overall revenues generated by the system during the runtime. Simulation results show that this policy leads to an efficient TV-Anytime system and makes the system more adaptive to changes in video popularity which is typically the case in the TV industry. the simulation results also show that multicasting significantly improves the system throughput during the high-load periods and makes the system more scalable. © 2001 IEEE.

关键词： Multicasting

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Improving effective bandwidth through compiler enhancement of global cache reuse 15

Improving effective bandwidth through compiler enhancement o...

引用

15th International Parallel and Distributed Processing symposium, IPDPS 2001

作者： Ding, C. Kennedy, K. Department of Computer Science University of Rochester RochesterNY United States Department of Computer Science Rice University HoustonTX United States

ISBN: (纸本)0769509908

Reusing data in cache is critical to achieving high performance on modern machines because it reduces the impact of the latency and bandwidth limitations of direct memory access. To date, most studies of software memory hierarchy management have focused on the latency problem. However today's machines are increasingly limited by insufficient memory bandwidth-on these machines, latency-oriented techniques are inadequate because they do not seek to minimize the total memory traffic over the whole program. this paper explores the potential for addressing bandwidth limitations by increasing global cache reuse-that is, reusing data across whole program and over the entire data collection. To this end, the paper explores a two-step global strategy. the first step fuses computations on the same data to enable the caching of repeated accesses. the second step groups data used by the same computation to bring about contiguous access to memory. While the first step reduces the frequency of memory accesses, the second step improves their efficiency. the paper demonstrates the effectiveness of this strategy and shows how to automate it in a production compiler. © 2001 IEEE.

关键词： Memory architecture

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Time synchronization for wireless sensor networks 15

Time synchronization for wireless sensor networks

引用

15th International Parallel and Distributed Processing symposium, IPDPS 2001

作者： Elson, J. Estrin, D. Department of Computer Science University of California Los Angelesand USC/Information Sciences Institute

ISBN: (纸本)0769509908

Time synchronization is a critical piece of infrastructure for any distributed system. Distributed, wireless sensor networks make extensive use of synchronized time, but often have unique requirements in the scope, lifetime, and precision of the synchronization achieved, as well as the time and energy required to achieve it. Existing time synchronization methods need to be extended to meet these new needs. We outline the synchronization requirements of future sensor networks and present an implementation of our own low-power synchronization scheme, post-facto synchronization. We also describe an experiment that characterizes its performance for creating short-lived and localized but high-precision synchronization using very little energy. © 2001 IEEE.

关键词： Synchronization

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Bandwidth tracking in distributed heterogeneous networking environments 15

Bandwidth tracking in distributed heterogeneous networking e...

引用

15th International Parallel and Distributed Processing symposium, IPDPS 2001

作者： Sullivan, C. Jurczyk, M. Department of Computer Engineering and Computer Science University of Missouri-Columbia 121 Engineering Building West ColumbiaMO65211 United States

ISBN: (纸本)0769509908

this work investigates bandwidth tracking algorithms in a version of a distributed heterogeneous data dissemination system called the Agile Information Control Environment (AICE). In this environment, the probability of setup or rejection of communication requests has to be derived without any updated knowledge of the actual topologies of the underlying networks. In this paper, a network learning algorithm is therefore introduced that is able to predict the setup/rejection of a communication request with a high accuracy of around 80% by tracking the average spare bandwidth of end-to-end communication channels. the learning algorithm uses elements of exponential growth coupled with a binary search. this enables the learner to quickly learn about changes in the network topology and traffic load. It is shown that the learner is able to predict request setup/rejection with a high accuracy without any information about underlying network topologies. To maximize the learner performance, an initial full mesh aggregation of the underlying network topology at system startup should be used. © 2001 IEEE.

关键词： Network topology

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Continuous wavelet transform on reconfigurable meshes 15

Continuous wavelet transform on reconfigurable meshes

引用

15th International Parallel and Distributed Processing symposium, IPDPS 2001

作者： Pan, Yi Li, Jie Vemuri, Ranga Department of Computer Science Georgia State University AtlantaGA30303 United States Institute of Information Sciences and Electronics University of Tsukuba Tsukuba Science City Ibaraki305-8573 Japan Department of ECECS University of Cincinnati CincinnatiOH45221-0030 United States

ISBN: (纸本)0769509908

Wavelet transforms have proven to be useful tools for several applications, including signal analysis, signal coding, and image compression. In this paper, faster parallel algorithms for computing the continuous wavelet transform are designed for reconfigurable meshes. An O(n1/2/m(log b + log∗ n))-time algorithm for computing the continuous wavelet transform with n signals and an integer grid (m, k) on a 3-D m x k x n reconfigurable mesh is proposed, where b is the number of bits used to represent the values in calculation. A constant-time algorithm 3-D m x k log3 n x t reconfigurable mesh is also proposed. To the best knowledge of the author, this is the first constant-time algorithm for continuous wavelet transform on any parallel architecture. © 2001 IEEE.

关键词： Parallel architectures

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performance benefits of NIC-based barrier on myrinet/GM 15

Performance benefits of NIC-based barrier on myrinet/GM

引用

15th International Parallel and Distributed Processing symposium, IPDPS 2001

作者： Buntinas, D. Panda, D.K. Sadayappan, P. Network-Based Computing Laboratory Department of Computer and Information Science Ohio State University ColumbusOH43210 United States

ISBN: (纸本)0769509908

Barrier synchronization is a common operation in parallel and distributed systems. A fast implementation is important because it allows fine grained parallel programs to be more efficient. It is therefore important to minimize the latency of barrier operations. Modern network interface cards (NICs) have programmable processors which can be used to support collective communications such as barrier. In [4] we have designed and implemented a NIC-based barrier feature over GM. this new NIC-based barrier operation raises many open questions which must be answered. Does the NIC-based barrier perform better than the host-based barrier? How does the performance of the NIC-based barrier change with better NICs? Is the NIC-based barrier scalable? How does the performance of the NIC-based barrier affect the granularity of computation? How does the NIC-based barrier affect the performance of applications? In this paper, we take on these challenges. We find that the NIC-based barrier performs better than the host-based barrier with up to a 2.22 factor of improvement on an eight node system at the MPI-level. We also find that the factor of improvement values increase with the number of nodes indicating that the NIC-based barrier is more scalable. We find that the NIC-based barrier also allows for finer grained computation without affecting the efficiency of the program. Finally, by using synthetic applications on an eight node system, we find up to a 1.93 factor of improvement in the applications using a NIC-based barrier versus using a host-based barrier. these results indicate that NIC-based barrier in current and future clusters can deliver significant performance benefits to the applications. © 2001 IEEE.

关键词： Interfaces (computer)

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architecture, implementation, and deployment of a high performance, high capacity resilient mass storage server (RMSS) 18

Architecture, implementation, and deployment of a high perfo...

引用

18th IEEE symposium on Mass Storage Systems and Technologies, MSS 2001

作者： Jones, Terry Sarnowska, Beata Lovato, Frank Magee, David Kothe, John Bldg 1001 Stennis Space Center MS39529 United States

ISBN: (纸本)0769508499

the Naval Oceanographic Office (NAVOCEANO) high performance computing (HPC) Major Shared Resource Center (MSRC) recently reengineered the existing mass storage system serving its high-performance compute platforms. the purpose was to provide significantly improved file system availability, to refresh the technology and the architectural design, and to position the MSRC to incorporate emerging technologies such as Storage Area Networks (SANs). the resultant configuration utilizes two SUN Enterprise 10000s (E10K) with 3 TB of switched Fibre Channel Disk Arrays and the latest generation of tape devices. the theoretical peak system capacity is in excess of 2 Terabytes (TB) per day, with management of up to 1 PetaBytes (PB) of storage and an aggregate external network throughput of 220 Megabytes (MB) per second. this paper discusses the technologies and considerations used in the design of the MSRC Resilient Mass Storage Server (RMSS), its architecture, implementation and integration, deployment and transition from the existing CRAY Data Migration Facility (DMF). © 2001 IEEE.

关键词： computer architecture

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Data collection and restoration for heterogeneous process migration 15

Data collection and restoration for heterogeneous process mi...

引用

15th International Parallel and Distributed Processing symposium, IPDPS 2001

作者： Chanchio, K. Sun, X.-S. Department of Computer Science Illinois Institute of Technology ChicagoIL60616 United States

ISBN: (纸本)0769509908

this study presents a practical solution for data collection and restoration to migrate a process written in high level stack-based languages such as C and Fortran over a network of heterogeneous computers. We study a logical data model which recognizes complex data structures in process address space. then, novel methods are developed to incorporate the model into a process and to collect and restore data efficiently. We have implemented a prototype software and performed experiments on different programs. Experimental and analytical results show that (I) a user-level process can be migrated across different computing platforms, (2) semantic information of data structures in the process's memory space can be correctly collected and restored, (3) the costs of data collection and restoration depend on the complexity of the logical model representing the process's data structures and the amount of data involved and (4) the implantation of the data collection and restoration mechanisms into the process is not a decisive factor of incurring execution overheads;with appropriate program analysis, we can achieve practically low overhead. © 2001 IEEE.

关键词： Data acquisition

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A greedy grid - the grid economic engine directive 15

A greedy grid - The grid economic engine directive

引用

15th International Parallel and Distributed Processing symposium, IPDPS 2001

作者： Vazhkudai, S. Von Laszewski, G. Department of Computer and Information Science University of Mississippi UniversityMS38677 United States Mathematics and Computer Sciences Division Argonne National Laboratory ArgonneIL60439 United States

ISBN: (纸本)0769509908

the advent of national-scale "Computational Grid" infrastructures has helped deploy advanced services, beyond those taken for granted in today's Internet, such as: remote access to computers, wide area resource management, authentication, and directory services, thus enabling access and utilization of a variety of heterogeneous resources distributed over multiple domains. the availability of these services represents an opportunity to implement advanced services utilizing these basic Grid services. In this paper, we explore issues related to defining services that are based on economy and financial models in order to encourage further resource sharing among the administrative domains while also considering commodity PC's that are part of todays Internet. We propose an extendable architecture, the Grid Economic Engine Directive (Greed), that allows integration of various economy models within the same framework, exposing the services through secure protocols and policies. the services provided by this framework include, for example, a bartering service, a bidding service, and a trading service. We intend to develop components that can be integrated within a customizable Portal simplifying access to many of the services and propose to integrate the Greed economic middleware into the existing Globus metacomputing toolkit, thus enabling the application of economic paradigm to the Globus Computational and Data Grids. We further illustrate the applicability of the proposed Greed services by building a prototype business model as a higher-level application, using the economic middleware. © 2001 IEEE.

关键词： Engines

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