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检索条件"任意字段=15th Symposium on Computer Architecture and High Performance Computing"

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Complex Human Activities Recognition Based on high performance 1D CNN Model 15

Complex Human Activities Recognition Based on High Performan...

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15th IEEE International symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2022

作者： Maurya, Raman Teo, T. Hui Chua, Shi Hui Chow, Hwang-Cherng Wey, I-Chyn Singapore University of Technology and Design Engineering Product Development Singapore Singapore University of Technology and Design Engineering Product Development Science Mathematics and Technology Singapore Chang Gung University Department of Electronic Engineering Taiwan Chang Gung University Department of Electrical Engineering Taiwan

ISBN: (纸本)9781665464994

Human activity recognition (HAR) is an emerging scientific research field that has wide area of applications in different fields such as healthcare, social-sciences and human-computer interaction etc. In many cases, humans perform very complex physical activities that needs to be tracked in order to improve well-being, quality of life and health. In this study, a method for complex HAR based on One dimensional (1D) CNN model using tri-axis accelerometer sensor data was proposed. the sensor data was collected from a smartwatch for three complex human activities which are studying, playing games and mobile scrolling. 1D CNNs provides high accuracy as well as less computational complexity in performing HAR. the proposed 1D CNN model was trained and optimized on a self-prepared dataset in Python. the adapted model provides an accuracy of 98.28 %. A preliminary study shows that the proposed model could effectively recognize the intended activities as a baseline for extending future work in the HAR area. © 2022 IEEE.

关键词： Accelerometers

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Low-Latency Modular Exponentiation for FPGAs 30

Low-Latency Modular Exponentiation for FPGAs

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IEEE 30th International symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Langhammer, Martin Gribok, Sergey Pasca, Bogdan Intel Corp Swindon Wilts England Intel Corp Santa Clara CA 95051 USA Intel Corp Paris France

ISBN: (纸本)9781665483322

Modular exponentiation, especially for very large integers of hundreds or thousands of bits, is a commonly used function in popular cryptosystems such as RSA. the complexity of this algorithm is partly driven by the very large word sizes, which require many - often millions - of primitive operations in a CPU implementation, or a large amount of logic when accelerated by an ASIC. FPGAs, with their many embedded DSP resources have started to be used as well. In almost all cases, the calculations have required multiple - occasionally many - clock cycles to complete. Recently, blockchain algorithms have required very low-latency implementations of modular multiplications, motivating new implementations and approaches. In this paper we show nine different high performance modular exponentiation for 1024-bit operands, using a 1024-bit modular multiplication as it's core. Rather than just showing a number of completed designs, our paper shows the evolution of architectures which lead to different resource mix options. this will allow the reader to apply the examples to different FPGA targets which may have differing ratios of logic, memory, and embedded DSP blocks. In one design, we show a 1024b modular multiplier requiring 83K ALMs and 2372 DSPs, with a delay of 21.21ns.

关键词： Costs computer architecture Delays Complexity theory Blockchains Low latency communication Field programmable gate arrays

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Automated Road Extraction from Aerial Images: A Generative Approach with W-FuseNet Model

Automated Road Extraction from Aerial Images: A Generative A...

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International Conference on computing and Networking Technology (ICCNT)

作者： Debendra Muduli Santosh Kumar Sharma Debasish Pradhan Dept. Computer Science and Eng. C.V. Raman Global University Bhubaneshwar India

ISBN: (数字)9798350370249

ISBN: (纸本)9798350370270

this research introduces an automated road extraction model utilizing deep learning techniques for high-resolution aerial imagery. Focused on applications in urban planning, disaster management, and logistics, the study employs convolutional neural networks (CNNs) and a conditional Generative Adversarial Network (cGAN) architecture. the Massachusetts Roads Dataset, comprising 1171 images, is subject to advanced preprocessing techniques, including resizing, concatenation, and normalization. the proposed model features a carefully crafted generator with an encoder-decoder architecture and a modified Pix2pix-based cGAN for semantic segmentation. Inspired by the PatchGAN concept, the discriminator assesses image patches to distinguish real from generated images. A literature survey evaluates methodologies, emphasizing the Road Structure Refined CNN (RSRCNN), generative learning approaches, and the fully convolutional network (FCN) for road extraction. performance analysis demonstrates the model’s competitive IoU score compared to existing approaches along with accuracy, precision, recall and f1-score. A novel road extraction model using the Massachusetts Roads Dataset is introduced, highlighting WFuseNet architecture and advanced pre-processing techniques.

关键词： Surveys Analytical models Adaptation models Roads Semantic segmentation Urban planning computer architecture Predictive models Convolutional neural networks Remote sensing

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Fast Arbitrary Precision Floating Point on FPGA 30

Fast Arbitrary Precision Floating Point on FPGA

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IEEE 30th International symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Licht, Johannes de Fine Pattison, Christopher A. Ziogas, Alexandros Nikolaos Simmons-Duffin, David Hoefler, Torsten Swiss Fed Inst Technol Dept Comp Sci Zurich Switzerland CALTECH Inst Quantum Informat & Matter Pasadena CA 91125 USA CALTECH Walter Burke Inst Theoret Phys Pasadena CA 91125 USA

ISBN: (纸本)9781665483322

Numerical codes that require arbitrary precision floating point (APFP) numbers for their core computation are dominated by elementary arithmetic operations due to the superlinear complexity of multiplication in the number of mantissa bits. APFP computations on conventional software-based architectures are made exceedingly expensive by the lack of native hardware support, requiring elementary operations to be emulated using instructions operating on machine-word-sized blocks. In this work, we show how APFP multiplication on compile-time fixed-precision operands can be implemented as deep FPGA pipelines with a recursively defined Karatsuba decomposition on top of native DSP multiplication. When comparing our design implemented on an Alveo U250 accelerator to a dual-socket 36-core Xeon node running the GNU Multiple Precision Floating-Point Reliable (MPFR) library, we achieve a 9.8x speedup at 4.8 GOp/s for 512-bit multiplication, and a 5.3x speedup at 1.2 GOp/s for 1024-bit multiplication, corresponding to the throughput of more than 351x and 191x CPU cores, respectively. We apply this architecture to general matrix-matrix multiplication, yielding a 10x speedup at 2.0 GOp/s over the Xeon node, equivalent to more than 375x CPU cores, effectively allowing a single FPGA to replace a small CPU cluster. Due to the significant dependence of some numerical codes on APFP, such as semidefinite program solvers, we expect these gains to translate into real-world speedups. Our configurable and flexible HLS-based code provides as high-level software interface for plug-and-play acceleration, published as an open source project.

关键词： Codes Pipelines Quantum mechanics computer architecture throughput Reliability engineering Hardware

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performance Modeling of MARE2DEM's Adaptive Mesh Refinement for Makespan Estimation

Performance Modeling of MARE2DEM's Adaptive Mesh Refinement ...

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International symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Bruno Da Silva Alves Lucas Mello Schnorr Graduate Program in Computer Science (PPGC) Institute of Informatics – UFRGS Porto Alegre Brazil

Adaptive Mesh Refinement (AMR) is a widely known technique to adapt the accuracy of a solution in critical areas of the problem domain instead of using regular or irregular but static meshes. the MARE2DEM is a parallel application that employs the AMR technique to model 2D electromagnetics in oil and gas exploration. the modeling consists in iteratively applying a data inversion based on a set of measurements collected and registered by a survey on an area of interest. the parallelism of the MARE2DEM works by dividing the workload into a set of refinement groups that represent overlapping areas of the problem domain. Each refinement group can be computed independently of the others by a set of workers, carrying out the AMR in the meshes when necessary. the shape and compute performance of the refinement group depend directly of a set of user-defined parameters. In this article, we provide a method to estimate the MARE2DEM performance for all possible values that can be used in the influencing parameters of the application for a given case study. Our relatively cheap method enables the geologist to configure MARE2DEM correctly and extract the best performance for a given cluster configuration. We detail how the method works and evaluate its effectiveness with success, pinpointing the best values for the creating refinement groups using a real case study from the Marlim field on the coast of Rio de Janeiro, Brazil. Although we demonstrate our evaluation with this scenario, our method works for any input of MARE2DEM.

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Memory Sandbox: A Versatile Tool for Analyzing and Optimizing HBM performance in FPGA

Memory Sandbox: A Versatile Tool for Analyzing and Optimizin...

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International symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Elias Perdomo Xavier Martorell Teresa Cervero Behzad Salami Barcelona Supercomputing Center (BSC) Universitat Politècnica de Catalunya (UPC) Barcelona Spain BSC UPC Barcelona Spain BSC Barcelona Spain

ISBN: (数字)9798350356168

ISBN: (纸本)9798350356175

Main memory access has become an increasing performance bottleneck for traditional and high-performance computing (HPC) applications. high Bandwidth Memory (HBM) has emerged as an alternative to conventional DRAMs, offering higher bandwidth, lower power consumption, and greater integration capabilities to meet the escalating demands of contemporary applications. the transition to HBM of the most advanced Field Programmable Gate Arrays (FPGAs) marks a paradigm shift. However, users face substantial challenges due to the scarce technical documentation and tools supporting HBM on FPGAs. this paper introduces the Memory Sandbox, an open-source tool integrated into our FPGA-Shell 1 , designed to address the complexity of utilizing HBM in FPGAs. It allows developers and students to explore roofline performances while gaining insights to improve their designs. the Memory Sandbox enables users to configure various parameters such as the number of processing elements accessing memory, the access pattern (sequential, pseudo-random, or sparse-wise), and memory configurations, emulating multiple processor threads in diverse heterogeneous scenarios. It provides detailed analyses of memory access impacts in terms of latency and throughput for scenarios with accesses within and across HBM pseudo-channels; as well as HBM performance under concurrent access scenarios. Our results show that HBM achieves 99.99% of its nominal peak bandwidth with long sequential accesses but drops to 0.17% with random data access patterns. the tool also highlights the impact of multiple AXI ports targeting the same pseudo-channel, revealing that the aggregated throughput remains constant regardless of the pseudo-channel count. Furthermore, we validate the Memory Sandbox’s capabilities by effectively profiling complex access patterns like Sparse Matrix-Vector (SpMV), demonstrating its effectiveness in providing accurate performance insights. 1 https://***/MEEPproject/fpga_shell

关键词： Power demand Instruction sets high performance computing Microprocessors Bandwidth throughput Software Sparse matrices Field programmable gate arrays Faces

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Exploring Storage Device Characteristics of A RISC-V Little-core SoC 15

Exploring Storage Device Characteristics of A RISC-V Little-...

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15th IEEE International Conference on Networking, architecture and Storage (NAS)

作者： Lu, Tao Marvell Technol Grp Wilmington DE 19801 USA

ISBN: (纸本)9781728177441

Low-power system-on-chips (SoCs) dominate the Internet of things (IoT) ecosystem, which consists of billions of devices that can generate Zettabytes of data. SoC directly interacts with big data, but there is little research on its storage performance and power consumption characteristics, especially the lack of quantitative evaluation. In this paper, we study the storage characteristics of a low-power RISC-V SoC FPGA. Specifically, we deploy a PCIe SSD to study the performance of storage devices under little cores. We quantitatively evaluate device bandwidth, IOPS throughput, and power consumption. In addition, we compare the same device on the low-power RISC-V SoC and a high-performance x86 server to observe the similarities and differences of the storage device behavior on different computing platforms.

关键词： performance evaluation Power demand Conferences Ecosystems computer architecture throughput System-on-chip

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performance Characterization of MPI_Allreduce in Cloud Data Center Networks 29

Performance Characterization of MPI_Allreduce in Cloud Data ...

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29th International symposium on the Modeling, Analysis, and Simulation of computer and Telecommunication Systems (MASCOTS)

作者： Musleh, Malek Alemania, Allister Penaranda, Roberto Segura, Pedro Yebenes Intel Corp Santa Clara CA 95051 USA

ISBN: (纸本)9781665458382

Advancements in hardware architecture and system design have enabled the transformational pivot towards cloud-computing. the rising cost of on-premise, vertical scaling, and maintenance combined with the rise of workload heterogeneity have fueled this paradigm shift. Furthermore, increasingly demanding use-cases for storage and high-performance computing (HPC) as well as the emergence of new workloads such as machine learning and big-data have motivated research into network traffic analysis, resource disaggregation, job scheduling, and orchestration in a bid to reduce total cost while maintaining high performance. A prime focus of this research is the communication performance of collectives, which comprise a significant portion of the communication of many of the aforementioned workloads. In this paper, we characterize the performance of MPI_Allreduce, which is used extensively in HPC and Deep-Learning (DL) training workloads in cloud environments. We demonstrate several key insights including that the Ring algorithm performs better than the Rabenseifner algorithm under conditions of high congestion and packet drops. We further illustrate detailed performance analysis under different assumptions and provide recommendations on how to address issues that can manifest.

关键词： Data Center Cloud computing Deep Learning AI Training HPC Collectives Congestion Control AllReduce Rabenseifner Ring Kary Tree Recursive Doubling

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Low-Power CRC-BCH Error Correction Integrated with LFSR and Clock Gating: A Comparative Analysis

Low-Power CRC-BCH Error Correction Integrated with LFSR and ...

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IEEE Annual computing and Communication Workshop and Conference (CCWC)

作者： Karthik Velagapudi Shuo Wu Nan Wang Department of Electrical and Computer Engineering California State University Fresno CA USA

ISBN: (数字)9798331507695

ISBN: (纸本)9798331507701

this paper presents a low-power, Clock-Gated Integrated CRC-BCH (Cyclic Redundancy Check - Bose-Chaudhuri-Hocquenghem) Error Correction Code (ECC) architecture designed to address single-event upsets (SEUs) and multi-cell upsets (MCUs) in space applications. ECCs are essential for ensuring reliable data transmission and reception in avionics and memory systems, which are increasingly prone to faults due to cosmic radiation, thereby necessitating robust fault detection and correction mechanisms. In this work, a Linear Feedback Shift Register (LFSR) based fault injector simulator was introduced within the CRC-BCH module to evaluate its error detection and correction capabilities under various fault scenarios. Additionally, a Clock Gating Integrated Circuit (CGIC) was implemented to optimize power consumption. the proposed design achieves significant power efficiency while maintaining high performance and reliability, making it highly suitable for power-sensitive, high-reliability environments.

关键词： Integrated circuits Power demand Redundancy Single event upsets Aerospace electronics Logic gates Reliability engineering Energy efficiency Error correction codes Clocks

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DeVAS: Decoupled Virtual Address Spaces

DeVAS: Decoupled Virtual Address Spaces

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International symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Mirco Mannino Biagio Peccerillo Andrea Mondelli Sandro Bartolini University of Siena Siena Italy Huawei

ISBN: (数字)9798350356168

ISBN: (纸本)9798350356175

the constant growth of workload size in modern applications is making address translation a performance bottleneck. In principle, increasing the virtual page size could be advantageous, as it would allow each cached address translation to cover a larger memory space. Nevertheless, the utilization of larger pages introduces challenges, such as issues related to memory fragmentation and physical page management. In this paper, we present Decoupled Virtual Address Spaces (DeVAS), a virtual memory proposal that enables the decoupling of address translation and memory allocation, by allowing different sizes for virtual and physical pages, aiming to exploit the benefits of both. DeVAS introduces an intermediate virtual address space allocated by the Operating System employing larger pages (e.g., 2MiB), corresponding to the virtual page size seen by the processor, and a memory controller extension devoted to their allocation in physical memory at a smaller granularity (e.g., 4KiB). We show that DeVAS achieves an average 1.13 × performance improvement over a traditional configuration (i.e., with 4KiB pages) with no specific architectural modifications and for memory-intensive benchmarks. Moreover, DeVAS strategy enables architectural modifications for increasing performance, such as simplified/optimized TLB structure and L1-cache design flexibility. When considering these adjustments, DeVAS achieves a speedup of up to 1.20 × compared to the same reference. Furthermore, it matches and even edges the performance of an ideal (i.e., not implementable in practice) virtual memory configuration based on 2MiB pages only.

关键词： Operating systems high performance computing Memory management Process control Aerospace electronics Benchmark testing Resource management Proposals Optimization

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