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A model for moldable supercomputer jobs

A model for moldable supercomputer jobs

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International symposium on Parallel and Distributed Processing (IPDPS)

作者： W. Cirne F. Berman Departamento de Sistemas e Computação Universidade Federal da Paraíba Brazil Computer Science and Engineering University of California San Diego USA

ISBN: (纸本)0769509908

the performance of supercomputer schedulers is influenced by the workloads that serve as their input. Realistic workloads are therefore critical to evaluate how supercomputer schedulers perform in practice. there has been much written in the literature about rigid parallel jobs, i.e. jobs that require partitions of a fixed size to run. However the majority of the parallel jobs in production today are moldable, i.e. jobs that can execute on a variety of partition sizes. In this paper we describe a workload model for moldable jobs, which is based on a user survey and good analytical models. Our model can serve as the basis for the development of performance-efficient strategies for selection of the job partition size, as well as the basis for enhancing supercomputer schedulers to directly accept moldable request.

关键词： Supercomputers Processor scheduling Job production systems Concurrent computing computer science performance evaluation Analytical models US Department of Energy NASA Turning

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performance analysis of wormhole switching in k-ary n-cubes under multimedia traffic

Performance analysis of wormhole switching in k-ary n-cubes ...

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International symposium on Parallel and Distributed Processing (IPDPS)

作者： G. Min M. Ould-Khaoua Department of Computing Science University of Glasgow Glasgow UK

ISBN: (纸本)0769509908

Many recent studies have revealed that the traffic generated by multimedia applications exhibits a high degree of burstiness and possesses strong correlation in the number of message arrivals between adjacent time intervals, which can significantly affect network performance. However all existing performance models for multicomputer networks have assumed the Poisson arrival process, which has been shown on many occasions to be unable to capture the nature of multimedia traffic. this paper proposes the first analytical model for wormhole switching in k-ary n-cube networks under multimedia traffic based on the well-known correlated Markov-modulated Poisson process (MMPP). Results obtained from simulation experiments confirm that the proposed model exhibits a good degree of accuracy for various network sizes and under different operating conditions.

关键词： performance analysis Traffic control Routing Telecommunication traffic Analytical models Computational modeling Queueing analysis Multimedia computing Large-scale systems Network servers

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Evolving the Web-based distributed SI/PDO architecture for high-performance visualization

Evolving the Web-based distributed SI/PDO architecture for h...

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Annual symposium on Simulation

作者： V.P. Holmes J.M. Linebarger D.J. Miller R.L. Vandewart C.P. Crowley Sandia National Laboratories Albuquerque NM USA Computer Science Department University of New Mexico Albuquerque NM USA

ISBN: (纸本)0769510922

We have extended the SI/PDO architecture to allow Web access to visualization tools running on MP systems. We make these tools more easily accessible by providing Web-based interfaces and by shielding the user from the details of these computing environments. We use a multi-tier architecture, where the Java-based GUI tier runs on a Web browser and provides image display and control functions. the visualization tier runs on MP machines. the middle tiers provide custom communication with MP machines, remote file selection, remote launching of services, and load balancing. the system allows for adding and removing of tiers depending upon the situation. this architecture is based on the requirements of our environment: huge data volumes (that cannot be easily moved), use of multiple middleware protocols, MP platform portability, rapid development of the visualization tools, distributed resource management (of MP resources), and the use of existing visualization tools.

关键词： computer architecture Data visualization Service oriented architecture computer interfaces Java Graphical user interfaces Displays Communication system control Load management Middleware

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Improving system performance with compressed memory

Improving system performance with compressed memory

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International symposium on Parallel and Distributed Processing (IPDPS)

作者： S. Roy R. Kumar M. Prvulovic Hewlett Packard Laboratories Palo Alto CA USA Hewlett Packard Laboratories Israel Department of Computer Science University of Illinois Urbana-Champaign Urbana IL USA

ISBN: (纸本)0769509908

this paper summarizes our research on implementing a compressed memory in computer systems. the basic premise is that the throughput for applications whose working set size does not fit in main memory degrades significantly due to an increase in the number of page faults. Hence we propose compressing memory pages that need to be paged out and storing them in memory. this hides the large latencies associated with a disk access, since the page has to be merely uncompressed when a page fault occurs. Our implementation is in the form of a device driver for Linux. We show results with some applications from the SPEC 2000 CPU benchmark suite and a computing kernel. It is seen that speed-ups ranging from 5% to 250% can be obtained depending on the paging behavior of the application.

关键词： System performance Kernel Operating systems Delay Laboratories throughput Degradation Linux Random access memory Hardware

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How to select a replication protocol according to scalability, availability and communication overhead

How to select a replication protocol according to scalabilit...

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Reliable Distributed Systems

作者： R. Jimenez-Peris M. Patino-Martinez G. Alonso B. Kernme School of Computer Science Technical University of Madrid (UPM) Madrid Spain Department of Computer Science Swiss Federal Institute of Technology Zurich Switzerland Department of Computer Science Swiss Federal Institute of Technology (ETHZ) Zurich Switzerland

Data replication is playing an increasingly important role in the design of parallel information systems. In particular, the widespread use of cluster architectures in high-performance computing has created many opportunities for applying data replication techniques in new areas. For instance, as part of work related to cluster computing in bioinformatics, we have been confronted with the problem of having to choose an optimal replication strategy in terms of scalability, availability and communication overhead. thus, we have evaluated several representative replication protocols in order to better understand their behavior in practice. the results obtained are surprising in that they challenge many of the assumptions behind existing protocols. Our evaluation indicates that the conventional read-one/write-all approach is the best choice for a large range of applications requiring data replication. We believe this is an important result for anybody developing code for computing clusters as the read-one/write-all strategy is much simpler to implement and more flexible than quorum-based approaches. In this paper we show that, in addition, it is also the best choice using a number of other selection criteria.

关键词： Protocols Scalability Databases computer science Bioinformatics computer architecture Concurrent computing Availability Information systems Distributed information systems

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Bit-parallel systolic modular multipliers for a class of GF(2/sup m/)

Bit-parallel systolic modular multipliers for a class of GF(...

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computer Arithmetic (ARIth)

作者： Chiou-Yng Lee Erl-Huei Lu Jau-Yien Lee Department of electrical Engineering Chung Gung University Taiwan

ISBN: (纸本)0769511503

In this paper, an effective algorithm for computing multiplication over a class of GF(2/sup m/) based on irreducible all one polynomials (AOP) and equally spaced polynomials (ESP) is presented. the structures are the use of two special operations, called the cyclic shifting and the inner product, to construct the low-latency bit-parallel systolic multipliers. the circuits are simple and modular which is important for hardware implementation. the AOP-based multiplier is composed of (m+1)/sup 2/ identical cells, each of which consisting of one 2-bit AND gate, one 2-bit XOR gate and three 1-bit latches. this multiplier has very low latency and propagation delay, which makes them very fast. Moreover, the AOP-based multiplier of small size can also be applied to construct ESP-based multiplier of large size, in which the elements are represented with the root of an irreducible equally spaced polynomial of degree nr. It is shown that if, for a certain degree, an irreducible ESP of a large degree can be obtained from a corresponding irreducible AOP of a very small degree, then from the complexity point view, the structure of the ESP-based multiplier is beneficial to construct a modular architecture.

关键词： Polynomials Electrostatic precipitators Circuits Cryptography Hardware Latches Propagation delay computer architecture Galois fields Electrical engineering

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Evaluating the performance of a DSM cluster with improved communication subsystem

Evaluating the performance of a DSM cluster with improved co...

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International Conference on Information Networking

作者： Y. Shimono B.O. Apduhan I. Arita Y. Ohnishi Department of Artificial Intelligence Kyushu Institute of Technology Iizuka Japan Information Science Center Kyushu Institute of Technology Iizuka Japan

ISBN: (纸本)0769509517

Parallel applications on network-based computing are most sensitive to communication overhead. the performance of a cluster computing system largely depends on the bandwidth, latency, and communication software processing overhead of the communication subsystem. the currently available fiber optics and opto-electronic device technologies offers solution to the bandwidth problem. However, achieving low latency remains a challenge and is considered by the research community as one critical issue to attain high-performance cluster computing. Different approaches to solve the problem have been proposed which deals with latency reduction and latency hiding. In this paper, we report on the new implementation of a DSM cluster computing system using the low-level application programming interface (LAPI) provided as part of IBM SP2 software. We discuss and evaluate the new (DSE-LAPI) and previous (DSE-TCP) implementations using application benchmarks with SPLASH-2 programs, i.e., FFT, radix, and LU. Likewise, we evaluate the scalability performance of the new implementation. Experimental results show promising performance of the new implementation and it further demonstrate the relative merit of adapting LAPI on a DSM cluster.

关键词： Delay Application software Bandwidth computer applications computer networks Concurrent computing Communication system software Software performance Optical fibers Optoelectronic devices

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high speed parallel-prefix modulo 2/sup n/+1 adders for diminished-one operands

High speed parallel-prefix modulo 2/sup n/+1 adders for dimi...

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computer Arithmetic (ARIth)

作者： H.T. Vergos C. Efstathiou D. Nikolos Computer Technology Institute Patras Greece Computer Engineeing & Informatics Department University of Patras Patras Greece Department of Informatics TEI of Athens Ag Egaleo Greece

ISBN: (纸本)0769511503

We present a new methodology for designing modulo 2/sup n/+1 adders with operands in the diminished-one number system. the proposed methodology leads to parallel-prefix adder implementations. Both an analytical model and VLSI implementations in a standard-cell technology are utilized for comparing the adders designed following the proposed methodology against the existing solutions. Our results indicate; that the proposed parallel-prefix adders are considerably faster than any other already known in the open literature and as fast as the corresponding modulo 2/sup n/ and modulo 2/sup n/-1 adders.

关键词： Adders Design methodology Very large scale integration Informatics Analytical models Digital signal processing Concurrent computing Digital arithmetic Signal processing algorithms Circuits

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Instruction flow-based front-end throttling for power-aware high-performance processors

Instruction flow-based front-end throttling for power-aware ...

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International symposium on Low Power Electronics and Design (ISLPED)

作者： A. Baniasadi A. Moshovos Electrical and Computer Engineering Northwestern University USA Electrical and Computer Engineering University of Toronto Canada

We present a number of power-aware instruction front-end (fetch/decode) throttling methods for high-performance dynamically-scheduled superscalar processors. Our methods reduce power dissipation by selectively turning on and off instruction fetch and decode. Moreover, they have a negligible impact on performance as they deliver instructions just in time for exploiting the available parallelism. Previously proposed front-end throttling methods rely on branch prediction confidence estimation. We introduce a new class of methods that exploit information about instruction flow (rate of instructions passing through stages). We show that our methods can boost power savings over previously proposed methods. In particular, for an 8-way processor a combined method reduces traffic by 14%, 20%, 6% and 6% for the fetch, decode, issue and complete stages respectively while performance remains mostly unaffected. the best previously proposed method reduces traffic by 10%, 15%, 4% and 4% respectively.

关键词： Decoding Frequency Power dissipation Transistors Permission Pipelines Process design computer aided instruction Power engineering computing Power engineering and energy

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Gang scheduling with a queue for large jobs

Gang scheduling with a queue for large jobs

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International symposium on Parallel and Distributed Processing (IPDPS)

作者： B.B. Zhou R.P. Brent School of Computing & Mathematics Deakin University Geelong VIC Australia Computing Laboratory Oxford University Oxford UK

ISBN: (纸本)0769509908

Applying gang scheduling can alleviate the blockade problem caused by exclusively space-sharing scheduling. To simply allow jobs to ran simultaneously on the same processors as in conventional gang scheduling, however, may introduce a large number of time slots in the system. In consequence the cost of context switches will be greatly increased, and each running job can only obtain a small portion of resources including memory space and processor utilisation and so no jobs can finish their computations quickly. therefore, the number of jobs allowed to run in the system should be limited. In this paper we present some experimental results to show that by limiting real large jobs time-sharing the same processors and applying the backfilling technique we can greatly reduce the average number of time slots in the system and significantly improve the performance of both small and large jobs.

关键词： Processor scheduling Parallel processing Time sharing computer systems Dynamic scheduling Mathematics Laboratories Australia Costs Switches Software packages

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