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Faithful powering computation using table look-up and a fused accumulation tree

Faithful powering computation using table look-up and a fuse...

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computer Arithmetic (ARIth)

作者： J.A. Pineiro J.D. Bruguera J.M. Muller Department of Elcctricd and Computer Engineering University of Santiago de Compostela Spain LIP Ecole Normale Superieure de Lyon CNRS Project CNRS ENSL INRIA ARENAIRE France

ISBN: (纸本)0769511503

A method for the calculation of faithfully rounded single-precision floating-point powering (X/sup p/) is proposed in this paper. this method employs table look-up and a second-degree minimax approximation, which allows the employment of reduced size tables to store the coefficients from the polynomial approximation. A specialized squaring unit and a fused accumulation tree carry out with the computation of the quadratic polynomial. Both unfolded and pipelined architectures are presented, and the results of a pre-layout synthesis performed using CMOS 0.35 /spl mu/m technology are shown, achieving a 50% area reduction from linear approximation methods, and with improved speed over other second-degree approximation based algorithms. the pipelined architecture has a latency of three cycles and a throughput of one result per cycle.

关键词： Polynomials Signal processing algorithms Function approximation Piecewise linear approximation Approximation algorithms Iterative algorithms Power engineering computing Minimax techniques Piecewise linear techniques Power engineering and energy

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Speculative precomputation: long-range prefetching of delinquent loads

Speculative precomputation: long-range prefetching of delinq...

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Annual International symposium on computer architecture, ISCA

作者： J.D. Collins Hong Wang D.M. Tullsen C. Hughes Yong-Fong Lee D. Lavery J.P. Shen Department of Computer Science and Engineering University of California San Diego La Jolla CA Microprocessor Research Laboratory Intel Corporation Santa Clara CA USA Microprocessor Research Lab Department of Computer Science and Engineering University of California San Diego La Jolla CA USA Department of Computer Science University of Illinois Urbana-Champaign Urbana IL USA Microcomputer Software Lab Intel Corporation Santa Clara CA Microcomputer Software Laboratory Intel Corporation Santa Clara CA USA Department of Computer Science University of Illinois at Urbana-Champaign Urbana IL

ISBN: (纸本)0769511627

this paper explores Speculative Precomputation, a technique that uses idle thread contexts in a multithreaded architecture to improve performance of single-threaded applications. It attacks program stalls from data cache misses by pre-computing future memory accesses in available thread contexts, and prefetching these data. this technique is evaluated by simulating the performance of a research processor based on the Itanium/sup TM/ ISA supporting Simultaneous Multithreading. Two primary forms of Speculative Precomputation are evaluated. If only the non-speculative thread spawns speculative threads, performance gains of up to 30% are achieved when assuming ideal hardware. However, this speedup drops considerably with more realistic hardware assumptions. Permitting speculative threads to directly spawn additional speculative threads reduces the overhead associated with spawning threads and enables significantly more aggressive speculation, overcoming this limitation. Even with realistic costs for spawning threads, speedups as high as 169% are achieved, with an average speedup of 76%.

关键词： Prefetching Yarn Bandwidth Hardware Surface-mount technology computer science Multithreading Delay Microprocessors Microcomputers

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Modular multiplication and base extensions in residue number systems

Modular multiplication and base extensions in residue number...

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computer Arithmetic (ARIth)

作者： J.-C. Bajard L.-S. Didier P. Kornerup L.I.R.M.M Montpellier France Université de Bretagne Occidentale Brest France SDU Odense University Odense Denmark

ISBN: (纸本)0769511503

We present a new RNS modular multiplication for very large operands. the algorithm is based on Montgomery's (1985) method adapted to residue arithmetic. By choosing the moduli of the RNS system reasonably large, an effect corresponding to a redundant high-radix implementation is achieved, due to the carry-free nature of residue arithmetic. the actual computation in the multiplication takes place in constant time, where the unit of time is a few simple residue operations. However, it is necessary twice to convert values from one residue system into another, operations which take O(n) time on O(n) processors, where n is the number of moduli in the RNS systems. thus these conversions are the bottlenecks of the method, and any future improvements in RNS base conversions, or the use of particular residue systems, can immediately be applied.

关键词： Arithmetic Cryptography Costs Protocols Concurrent computing

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Speculative precomputation: long-range prefetching of delinquent loads 01

Speculative precomputation: long-range prefetching of delinq...

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Proceedings of the 28th annual international symposium on computer architecture

作者： Jamison D. Collins Hong Wang Dean M. Tullsen Christopher Hughes Yong-Fong Lee Dan Lavery John P. Shen Department of Computer Science and Engineering University of California San Diego La Jolla CA Microprocessor Research Lab Intel Corporation Santa Clara CA Department of Computer Science University of Illinois at Urbana-Champaign Urbana IL Microcomputer Software Lab Intel Corporation Santa Clara CA

ISBN: (纸本)9780769511627

this paper explores Speculative Precomputation, a technique that uses idle thread context in a multithreaded architecture to improve performance of single-threaded applications. It attacks program stalls from data cache misses by pre-computing future memory accesses in available thread contexts, and prefetching these data. this technique is evaluated by simulating the performance of a research processor based on the Itanium™ ISA supporting Simultaneous Multithreading. Two primary forms of Speculative Precomputation are evaluated. If only the non-speculative thread spawns speculative threads, performance gains of up to 30% are achieved when assuming ideal hardware. However, this speedup drops considerably with more realistic hardware assumptions. Permitting speculative threads to directly spawn additional speculative threads reduces the overhead associated with spawning threads and enables significantly more aggressive speculation, overcoming this limitation. Even with realistic costs for spawning threads, speedups as high as 169% are achieved, with an average speedup of 76%.

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Fast and scalable parallel algorithms for matrix chain product and matrix powers on distributed memory systems

Fast and scalable parallel algorithms for matrix chain produ...

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International symposium on Parallel and Distributed Processing (IPDPS)

作者： Keqin Li Department of Computer Science State University of New York New Paltz NY USA

ISBN: (纸本)0769509908

Given N matrices A/sub 1/, A/sub 2/,..., A/sub N/ of size N/spl times/N, the matrix chain product problem is to compute A/sub 1//spl times/A/sub 2//spl times//spl middot//spl middot//spl middot/A/sub N/. Given an N/spl times/N matrix A, the matrix powers problem is to calculate the first N powers of A, i.e., A, A/sup 2/A/sup 3/,..., A/sup N/. We consider distributed memory systems (DMS) with p processors that can support one-to-one communications in O(T(p)) time. Assume that the time complexity of the best known sequential algorithm for matrix multiplication is O(N/sup /spl alpha//), where /spl alpha/<2.3755. Let p be arbitrarily chosen in the range 1/spl les/p/spl les/N/sup /spl alpha/+1//log N. We show that the two problems can be solved on a p-processor DMS in T/sub chain/(N,p)=O(N/sup /spl alpha/+1//p+T(p)(N/sup 2(1+1//spl alpha/)//p/sup 2// /sup /spl alpha//(log p/N)/sup 1-2//spl alpha//+log(p log N/N/sup /spl alpha//) log N)) and T/sub power/(N,p)=0(N/sup /spl alpha/+1//p+T(p)(N/sup 2(1+1//spl alpha/)//p/sup 2// /sup /spl alpha//(log p/log N)/sup 1-2//spl alpha//+(log N)/sup 2/)) times, respectively. We also give instantiation of the above results in distributed memory parallel computers and DMS with hypercubic networks, and show that our parallel algorithms are either fully scalable or highly scalable.

关键词： Parallel algorithms Concurrent computing Distributed computing computer networks computer science Polynomials Graph theory Phase change random access memory high performance computing Equations

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Checkpointing and rollback of wide-area distributed applications using mobile agents

Checkpointing and rollback of wide-area distributed applicat...

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International symposium on Parallel and Distributed Processing (IPDPS)

作者： Jiannong Cao G.H. Chan Weijia jia T.S. Dillon Internet Computing and E-Commerce Lab Department of Computing Hong Kong Polytechnic University Hong Kong China Department of Computer Science City University of Hong Kong Hong Kong China

ISBN: (纸本)0769509908

We consider the problem of designing rollback error recovery algorithms for dynamic, wide area distributed systems like the Internet. the characteristics and the scale of such a system complicate the design and performance of the algorithms. Traditional message passing based algorithms incur large overhead, in both the network traffic and message passing delay, in such a wide-area environment. In this paper, we propose a novel approach to designing checkpointing and rollback algorithms using mobile agents as an aid. Using mobile agent leads to a reduction of the total amount of communication and allows us to design algorithms that take the advantage of the most up to date system information for decision making. It also allows us to develop algorithms implementing flexible and adaptive policies. A mobile agent enabled hybrid algorithm combining independent and coordinated checkpointing is proposed. A prototype of the algorithms is developed using IBM's Aglets. Results of performance evaluation are presented and discussed.

关键词： Checkpointing Algorithm design and analysis Mobile agents Message passing Heuristic algorithms Internet Telecommunication traffic Mobile communication Decision making Prototypes

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Parallel fuzzy inference system for large volumes of remote sensing data

Parallel fuzzy inference system for large volumes of remote ...

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IEEE International symposium on Industrial Electronics (ISIE)

作者： Sang Gu Lee Department of Computer Engineering Hannam University South Korea

ISBN: (纸本)0780370902

In the pattern recognition on the large volume of satellite images, the inference time is much increased. In the remote sensing data having 4 wavebands, 778 training patterns are learned. Each land cover pattern is classified by using 159900 patterns including trained patterns. In the fuzzy classification, 778 fuzzy rules are generated. Each fuzzy rule has 4 fuzzy variables in the condition part. therefore, high performance parallel fuzzy inference architecture is needed. In this paper, we propose a novel parallel fuzzy inference system on a T3E parallel computer. In this, fuzzy rules are distributed and executed simultaneously. the ONE-To-ALL algorithm is used to broadcast the fuzzy input to the all nodes. the results of the MIN/MAX operations are transferred to the output processor by the ALL-TO-ONE algorithm. By parallel processing of the fuzzy rules, the parallel fuzzy inference algorithm extracts match parallelism and achieves a good speed factor. this system can be used in a large expert system that has many inference variables in the condition and the consequent part.

关键词： Fuzzy systems Remote sensing Fuzzy control computer architecture Concurrent computing Parallel processing Control systems Inference algorithms Expert systems Database systems

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1st International Workshop on Parallel and Distributed computing Issues in Wireless Networks and Mobile computing

1st International Workshop on Parallel and Distributed Compu...

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International symposium on Parallel and Distributed Processing (IPDPS)

作者： Mohan Kumar Paul Spirakis Department of Computer Science and Engineering University of Texas Arlington Arlington TX USA Computer Technology Institute Patras Greece

ISBN: (纸本)0769509908

Summary form only given, as follows. Mobile computing has emerged as an important area of computing today as we move to the next millennium. this has been made possible due to the tremendous and continued growth of wireless communications and network technology over the past decade, providing infrastructures for "anytime anywhere" access to distributed computing systems and information repositories. the mobility of users offers new challenges to seamless connectivity in a distributed, heterogeneous network of wireline and wireless components. Several techniques and algorithms developed by the parallel and distributed computing community can be applied to solve typical wireless networks and mobile computing: routing, scheduling, load balancing, cache coherence, information access, and QoS provisioning problems. the objective of this workshop is to bring together technologists and researchers of international reputation in the areas of Parallel and Distributed computing and Wireless Networks and Mobile computing in order to have a forum for discussions, exchange of ideas and presentations. It is indeed a very appropriate to have this workshop as part of the IPDPS activities. We received twenty eight papers for the workshop. Each paper was sent to three program committee members for reviewing and after the review process we selected fourteen papers for presentation at the workshop. Due to the high quality of papers received, we had to reject some good papers. We take this opportunity to thank authors of all submitted papers and the referees for their efforts in making this workshop a success. Special thanks to all the steering committee members, the general chair, the publicity chairs and the technical program committee members for their support and assistance. We look forward to having a very fruitful and enjoyable workshop.

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CPR: mixed task and data parallel scheduling for distributed systems

CPR: mixed task and data parallel scheduling for distributed...

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International symposium on Parallel and Distributed Processing (IPDPS)

作者： A. Radulescu C. Nicolescu A.J.C. van_Gemund P.P. Jonker Faculty of Information Technology and Systems Delft University of Technology Delft GA The Netherlands Faculty of Applied Physics Delft University of Technology Delft GA The Netherlands

ISBN: (纸本)0769509908

It is well-known that mixing task and data parallelism to solve large computational applications often yields better speedups compared to either applying pure task parallelism or pure data parallelism. Typically, the applications are modeled in terms of a dependence graph of coarse-grain data-parallel tasks, called a data-parallel task graph. In this paper we present a new compile-time heuristic, named Critical Path Reduction (CPR), for scheduling data-parallel task graphs. Experimental results based on graphs derived from real problems as well as synthetic graphs, show that CPR achieves higher speedup compared to other well-known existing scheduling algorithms, at the expense of some higher cost. these results are also confirmed by performance measurements of two real applications (i.e., complex matrix multiplication and Strassen matrix multiplication) running on a cluster of workstations.

关键词： Parallel processing Processor scheduling Scheduling algorithm Concurrent computing Topology Information technology computer applications Physics computing Costs Measurement

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Concurrency, latency, or system overhead: Which has the largest impact on uniprocessor DRAM-system performance?

Concurrency, latency, or system overhead: Which has the larg...

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Annual International symposium on computer architecture, ISCA

作者： V. Cuppu B. Jacob Department of Electrical & Computer Engineering University of Maryland College Park USA

ISBN: (纸本)0769511627

Given a fixed CPU architecture and a fixed DRAM timing specification, there is still a large design space for a DRAM system organization. Parameters include the number of memory channels, the bandwidth of each channel, burst sizes, queue sizes and organizations, turnaround overhead, memory-controller page protocol, algorithms for assigning request priorities and scheduling requests dynamically, etc. In this design space, we see a wide variation in application execution times; for example, execution times for SPEC CPU 2000 integer suite on a 2-way ganged direct rambles organization (32 data bits) with 64-byte bursts are 10-20% lower than execution times on an otherwise identical configuration that uses 32-byte bursts. this represents two system configurations that are relatively close to each other in the design space; performance differences become even more pronounced for designs further apart. this paper characterizes the sources of overhead in high-performance DRAM systems and investigates the most effective ways to reduce a system's exposure to performance loss. In particular, we look at mechanisms to increase a system's support for concurrent transactions, mechanisms to reduce request latency, and mechanisms to reduce the "system overhead"-the portion of the primary memory system's overhead that is not due to DRAM latency but rather to things like turnaround time, request queueing inefficiencies due to read/write request interleaving, etc. Our simulator models a 2 GHz, highly aggressive out-of-order uniprocessor. the interface to the memory system is fully non-blocking, supporting up to 32 outstanding misses at both the level-1 and level-2 caches and split-transaction busses to all DRAM banks.

关键词： Concurrent computing Delay Random access memory Timing Bandwidth Protocols Scheduling algorithm Dynamic scheduling performance loss Read-write memory

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