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Wattch: A framework for architectural-level power analysis and optimizations

Wattch: A framework for architectural-level power analysis a...

引用

ISCA-27: the 27th Annual International symposium on computer architecture

作者： Brooks, David Tiwari, Vivek Martonosi, Margaret Princeton Univ Princeton United States

Power dissipation and thermal issues are increasingly significant in modern processors. As a result, it is crucial that power/performance tradeoffs be made more visible to chip architects and even compiler writers, in addition to circuit designers. Most existing power analysis tools achieve high accuracy by calculating power estimates for designs only after layout or floorplanning are complete. In addition to being available only late in the design process, such tools are often quite slow, which compounds the difficulty of running them for a large space of design possibilities. this paper presents Wattch, a framework for analyzing and optimizing microprocessor power dissipation at the architecture-level. Wattch is 1000X or more faster than existing layout-level power tools, and yet maintains accuracy within 10% of their estimates as verified using industry tools on leading-edge designs. this paper presents several validations of Wattch's accuracy. In addition, we present three examples that demonstrate how architects or compiler writers might use Wattch to evaluate power consumption in their design process. We see Wattch as a complement to existing lower-level tools;it allows architects to explore and cull the design space early on, using faster, higher-level tools. It also opens up the field of power-efficient computing to a wider range of researchers by providing a power evaluation methodology within the portable and familiar SimpleScalar framework.

关键词： computer architecture

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Smart Memories: a modular reconfigurable architecture

Smart Memories: a modular reconfigurable architecture

引用

Annual International symposium on computer architecture, ISCA

作者： K. Mai T. Paaske N. Jayasena R. Ho W.J. Dally M. Horowitz Computer Systems Laboratory University of Stanford Stanford CA USA

Trends in VLSI technology scaling demand that future computing devices be narrowly focused to achieve high performance and high efficiency, yet also target the high volumes and low costs of widely applicable general purpose designs. To address these conflicting requirements, we propose a modular reconfigurable architecture called Smart Memories, targeted at computing needs in the 0.1 /spl mu/m technology generation. A Smart Memories chip is made up of many processing tiles, each containing local memory, local interconnect, and a processor core. For efficient computation under a wide class of possible applications, the memories, the wires, and the computational model can all be altered to match the applications. To show the applicability of this design, two very different machines at opposite ends of the architectural spectrum, the Imagine stream processor and the Hydra speculative multiprocessor, are mapped onto the Smart Memories computing substrate. Simulations of the mappings show that the Smart Memories architecture can successfully map these architectures with only modest performance degradation.

关键词： Reconfigurable architectures Computational modeling Very large scale integration high performance computing Costs Tiles Wires Streaming media Memory architecture computer architecture

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Java/CORBA technology on a Beowulf cluster 38

Java/CORBA technology on a Beowulf cluster

引用

38th Annual ACM Southeast Conference, ACM-SE 2000

作者： Guo, Liang Bryant, Barrett R. Hyatt, Robert M. Department of Computer and Information Sciences University of Alabama at Birmingham 1300 University Blvd. BirminghamAL35294-1170 United States

ISBN: (纸本)1581132506

Java and CORBA have become standards for network and distributed systems programming over a wide variety of platforms [4]. As a kind of scientific and high performance computing machine, Beowulf is usually built out of commodity hardware components which are connected by a private high speed network, and runs on a free source code and modular design kernel software operating system like FreeBSD and Linux. While Java and CORBA both run on Linux [5], the underlying operating system of Beowulf clusters, there has not been much work in running Java/CORBA applications on Beowulf. the goal of this project is to develop Java/CORBA technology for a Beowulf cluster of computers [6]. the Beowulf cluster at UAB is a configuration of 15 SGI Indigo-2 machines and 8 Dell PowerEdge 6350 quad-processor 550MHz Xeon machines running Linux. the former 15 machines have 256 MB of RAM each and 4 GB of disk space connected with 10mbit/s Ethernet, while the latter 8 machines have 512 MB of RAM and 27 GB of disk space, with a high-speed cLan GigaNet switch connected among them. Current implemented software includes Tuple Space [4] and PVM [1]. Both of these provide for parallel computing over the distributed network of machines. Applications include parallelizing compilers for object-oriented programming languages, distributed implementation of computer chess, parallel and distributed algorithm performance analysis, debugging and visualization, and implementation of mobile agents. ORBacus [7] and JacORB [8] are within consideration for the underlying CORBA framework. © 2000 ACM.

关键词： Common object request broker architecture (CORBA)

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Recency-based TLB preloading

Recency-based TLB preloading

引用

Annual International symposium on computer architecture, ISCA

作者： A. Saulsbury F. Dahlgren P. Stenstrom Sun MicroSystems Laboratories Inc. Palo Alto CA USA Mobile Phones and Terminals Ericsson Mobile Communications AB Sweden Department of Computer Engineering Chalmers University of Technology Sweden

Caching and other latency tolerating techniques have been quite successful in maintaining high memory system performance for general purpose processors. However, translation lookaside buffers (TLB) misses have become a serious bottleneck as working sets are growing beyond the capacity of TLBs. this paper presents one of the first attempts to hide TLB miss latency by using preloading techniques. We present results for traditional next-page TLB miss preloading-an approach shown to cut some of the misses. However, a key contribution of this work is a novel TLB miss prediction algorithm based on the concept of "recency", and we show that it can predict over 55% of the TLB misses for the five commercial applications considered.

关键词： Prefetching Delay Sun Laboratories Mobile communication Mobile handsets high performance computing Maintenance engineering System performance Prediction algorithms

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Smart Memories: a modular reconfigurable architecture 00

Smart Memories: a modular reconfigurable architecture

引用

Proceedings of the 27th annual international symposium on computer architecture

作者： Ken Mai Tim Paaske Nuwan Jayasena Ron Ho William J. Dally Mark Horowitz Computer Systems Laboratory Stanford University Stanford California

ISBN: (纸本)9781581132328

Trends in VLSI technology scaling demand that future computing devices be narrowly focused to achieve high performance and high efficiency, yet also target the high volumes and low costs of widely applicable general purpose designs. To address these conflicting requirements, we propose a modular reconfigurable architecture called Smart Memories, targeted at computing needs in the 0.1μ technology generation. A Smart Memories chip is made up of many processing tiles, each containing local memory, local interconnect, and a processor core. For efficient computation under a wide class of possible applications, the memories, the wires, and the computational model can all be altered to match the applications. To show the applicability of this design, two very different machines at opposite ends of the architectural spectrum, the Imagine stream processor and the Hydra speculative multiprocessor, are mapped onto the Smart Memories computing substrate. Simulations of the mappings show that the Smart Memories architecture can successfully map these architectures with only modest performance degradation.

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Fast synchronization on scalable cache-coherent multiprocessors using hybrid primitives

Fast synchronization on scalable cache-coherent multiprocess...

引用

International symposium on Parallel and Distributed Processing (IPDPS)

作者： D.S. Nikolopoulos T.S. Papatheodorou High Performance Information Systems Laboratory Department of Computer Engineering and Informatics University of Patras Patras Greece

this paper presents a new methodology for implementing fast synchronization on scalable cache-coherent multiprocessors, through the use of hybrid primitives. Hybrid primitives leverage commodity hardware to speed-up the execution of the atomic remote Read-Modify-Write (RMW) instructions employed in synchronization algorithms to resolve contending processors, while exploiting the caches to reduce network traffic during the waiting and release phases of a synchronization primitive. We present a systematic methodology for transforming any synchronization primitive that uses RMW instructions into a hybrid one. We then provide experimental evidence on the effectiveness of using hybrid primitives in the implementation of spin locks, barriers and lock-free queues, in microbenchmarks and parallel applications on a SGI Origin 2000.

关键词： Hardware Software performance Application software Scalability Information systems Laboratories high performance computing Informatics computer architecture Concurrent computing

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Optimization of high-performance superscalar architectures for energy efficiency

Optimization of high-performance superscalar architectures f...

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International symposium on Low Power Electronics and Design (ISLPED)

作者： V. Zyuban P. Kogge Computer Science & Engineering Department University of Notre Dame IN USA

In recent years reducing power has become a critical design goal for high-performance microprocessors. this work attempts to bring the power issue to the earliest phase of high-performance microprocessor development. We propose a methodology for power-optimization at the micro-architectural level. First, major targets for power reduction are identified within superscalar microarchitecture, then an optimization of a superscalar micro-architecture is performed that generates a set of energy-efficient configurations forming a convex hull in the power-performance space. the energy-efficient families are then compared to find configurations that dissipate the lowest power given a performance target, or, conversely, deliver the highest performance given a power budget. Application of the developed methodology to a superscalar microarchitecture shows that at the architectural level there is a potential for reducing power up to 50%, given a performance requirement, and for up to 15% performance improvement, given a power budget.

关键词： Energy efficiency Microprocessors Out of order Registers Microarchitecture Permission computer architecture computer science Optimization methods Power generation

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A cost-effective load balanced adaptive routing scheme for mesh-connected networks

A cost-effective load balanced adaptive routing scheme for m...

引用

International symposium on Modeling, Analysis and Simulation of computer and Telecommunication Systems (MASCOTS)

作者： Xicheng Liu Sijing Zhang T.J. Li Centre for Communications Systems Research University of Cambridge Cambridge UK SPS Motorola Electronics Company Limited USA

A highly cost-effective adaptive routing algorithm for n-D meshes is designed. It employs only two virtual channels. the planar routing and the 2D VBMAR are used as constructs for it. Routing freedom is greatly enhanced to improve performance. As a result, the algorithm features load balance and high adaptivity. Deadlock freedom of the algorithm is proved. Extensive simulations show that it not only outperforms an algorithm with equal virtual channels, but also excels the fully routing algorithm with much more virtual channels.

关键词： Routing Multiprocessor interconnection networks Algorithm design and analysis System recovery computer architecture Computational modeling Load modeling Power system modeling Concurrent computing Parallel processing

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Wattch: a framework for architectural-level power analysis and optimizations

Wattch: a framework for architectural-level power analysis a...

引用

Annual International symposium on computer architecture, ISCA

作者： D. Brooks V. Tiwari M. Martonosi Department of Electrical Engineering Princeton University USA Intel Corporation USA

Power dissipation and thermal issues are increasingly significant in modern processors. As a result, it is crucial that power/performance tradeoffs be made more visible to chip architects and even compiler writers, in addition to circuit designers. Most existing power analysis tools achieve high accuracy by calculating power estimates for designs only after layout or floorplanning are complete. In addition to being available only late in the design process, such tools are often quite slow, which compounds the difficulty of running them for a large space of design possibilities. this paper presents Wattch, a framework for analyzing and optimizing microprocessor power dissipation at the architecture-level. Wattch is 1000X or more faster than existing layout-level power tools, and yet maintains accuracy within 10% of their estimates as verified using industry tools on leading-edge designs. this paper presents several validations of Wattch's accuracy. In addition, we present three examples that demonstrate how architects or compiler writers might use Wattch to evaluate power consumption in their design process. We see Wattch as a complement to existing lower-level tools; it allows architects to explore and cull the design space early on, using faster, higher-level tools. It also opens up the field of power-efficient computing to a wider range of researchers by providing a power evaluation methodology within the portable and familiar SimpleScalar framework.

关键词： Energy consumption Power dissipation Microprocessors Circuits Process design Portable computers Cooling Permission Accuracy Embedded computing

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Symbolic graph matching using the EM algorithm and singular value decomposition

Symbolic graph matching using the EM algorithm and singular ...

引用

International Conference on Pattern Recognition

作者： B. Luo E.R. Hancock Department of Computer Science University of York York UK

ISBN: (纸本)0769507506

this paper describes an efficient algorithm for inexact graph-matching. the method is purely structural, i.e., it uses only the edge or connectivity structure of the graph and does not draw on node or edge attributes. We make two contributions: 1) commencing from a probability distribution for matching errors, we show how the problem of graph-matching can be posed as maximum likelihood estimation using the apparatus of the EM algorithm; and 2) casting the recover of correspondences matches between the graph-nodes in a matrix framework. this allows us to efficiently recover correspondence matches using singular value decomposition. We experiment with the method on both real-world and synthetic data. We demonstrate that the method offers comparable performance to more computationally demanding methods.

关键词： Singular value decomposition Matrix decomposition Probability distribution Robustness Statistical analysis computer science computer vision high performance computing Image segmentation Distributed computing

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