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xBGAS: A Global Address Space Extension on RISC-V for high performance computing 35

xBGAS: A Global Address Space Extension on RISC-V for High P...

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35th IEEE International Parallel and Distributed Processing symposium (IPDPS)

作者： Wang, Xi Leidel, John D. Williams, Brody Ehret, Alan Mark, Miguel Kinsy, Michel A. Chen, Yong Texas Tech Univ Lubbock TX 79409 USA Tact Comp Labs Muenster TX USA Texas A&M Univ College Stn TX USA

ISBN: (纸本)9781665440660

the tremendous expansion of data volume has driven the transition from monolithic architectures towards systems integrated with discrete and distributed subcomponents in modern scalable high performance computing (HPC) systems. As such, multi-layered software infrastructures have become essential to bridge the gap between heterogeneous commodity devices. However, operations across synthesized components with divergent interfaces inevitably lead to redundant software footprints and undesired latency. therefore, a scalable and unified computing platform, capable of supporting efficient interactions between individual components, is desirable liar large-scale data-intensive applications. In this work, we introduce the Extended Base Global Address Space, or xBGAS, microarchitecture extension to the RISC-V instruction set architecture (ISA) for scalable high performance computing. the xBGAS extension provides native ISA-level support for direct accesses to remote shared memory by mapping remote data objects into a system's extended address space. We perform both software and hardware evaluations of the xBGAS design. the results show that xBGAS reduces instruction count generated by interprocess communication by 69.26% on average. Overall, xBGAS achieves an average performance gain of 21.96% (up to 37.29%) across the tested workloads.

关键词： Microarchitecture Runtime library high performance computing Instruction sets computer architecture Programming performance gain

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Towards performance Portability of an Oil and Gas Application on Heterogeneous architectures

Towards Performance Portability of an Oil and Gas Applicatio...

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International symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Arthur F. Lorenzon Phillipe O. A. Navaux Alexandre Sardinha Bronson Messer Institute of Informatics - UFRGS Porto Alegre Brazil Petróleo Brasileiro S.A. Rio de Janeiro Brazil Oak Ridge National Laboratory Oak Ridge USA

ISBN: (数字)9798350356168

ISBN: (纸本)9798350356175

With the widespread use of graphic processing units (GPUs) from different vendors in oil and gas companies, it has become increasingly important to achieve code portability. this allows for evaluating performance across diverse GPU vendors, enabling informed decisions. this capability enables companies to assess hardware solutions based on cost, performance, or energy efficiency, promoting competition and potentially driving innovation and cost reduction in GPU technologies. With that in mind, we address the challenge of achieving performance portability for Fletcher, an anisotropic wave propagation modeling application across various GPU architectures from NVIDIA and AMD. Hence, our first contribution is the parallel implementation of Fletcher on GPUs using eleven variations of portable programming models, including HIP, CUDA, Kokkos, RAJA, and OpenMP Target. Our second contribution is a comprehensive evaluation of these implementations across five generations of GPU from NVIDIA and AMD, assessing performance, performance-portability, and power-performance efficiency. through an extensive set of experiments, we demonstrate that HIP outperforms the assessed programming models in terms of performance portability across all evaluated GPUs. Specifically, it performs 7.9% better than Kokkos, 8.8% better than RAJA, and 67.8% better than OpenMP Target. We also show that while the automatic translation of CUDA to HIP code allows for execution on AMD GPUs, optimizing for high performance is necessary. Additionally, we show that the programming models’ impact on Fletcher’s performance is heavily influenced by the size of the GPU’s L2 cache, especially given that this is a memory-intensive application.

关键词： Technological innovation Costs Codes Oils Propagation Graphics processing units computer architecture Companies Programming Hip

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Yolo-based Deep Learning Techniques for Identifying Floating Bottles in Inland Water: A Comprehensive Analysis

Yolo-based Deep Learning Techniques for Identifying Floating...

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International Conference on computing and Networking Technology (ICCNT)

作者： B Saranya Devi Deepa Gupta Rimjhim Padam Singh Department of Computer Science and Engineering Amrita School of Computing Bengaluru Amrita Vishwa Vidyapeetham India

ISBN: (数字)9798350370249

ISBN: (纸本)9798350370270

Floating trash like bottles are one of the main causes of the serious environmental threat posed by the growing pollution of inland water bodies. Conservation efforts are hampered by the lack of effective and affordable techniques for locating and retrieving these bottles. Real-time object detection algorithms in conjunction with unmanned boats can offer ways to remove floating trash from rivers. A popular real-time object detection model is the You Only Look Once (Yolo) Series. Based on efficacy and accuracy rate, each YOLO model gets better than the other. the study presents an extensive analysis of YOLO designs, such as YOLOv5, YOLOv7, YOLOv8, and YOLO-NAS, for bottle identification in inland water. the dataset used is a floating trash in the river, and the performance metrics such as precision, recall and mean average precision are employed, to compare and experimentally validate each algorithm’s detection efficiency and accuracy. the methodology trains each architecture for 200 epochs. Regarding the precision of detection, the experimental results shows that YOLOv8-x model has high value of $85.5 \%$ and $\mathrm{mAP} \text{@}[I o U=0.5: 0.95]$ of 43.5%. YOLO-NAS variations have high recall, they are applicable for minimizing missed detection. YOLO-NAS m has a higher recall value of $90 \%$.

关键词： YOLO Measurement Deep learning Accuracy Boats computer architecture Water conservation Water pollution Real-time systems Rivers

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Towards Energy-Efficient and Real-Time Cloud computing 15

Towards Energy-Efficient and Real-Time Cloud Computing

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15th IEEE International Conference on Networking, architecture and Storage (NAS)

作者： Tekreeti, Taha Cao, Ting Peng, Xiaopu Bhattacharya, Tathagata Mao, Jianzhou Qin, Xiao Ku, Wei-Shinn Auburn Univ Dept Comp Sci & Software Engn Auburn AL 36849 USA

ISBN: (纸本)9781728177441

In modern cloud computing environments, there is a tremendous growth of data to be stored and managed in data centers. Large-scale data centers demand high utilization of computing and storage resources, which lead to expensive operational cost for energy usage. Evidence shows that consolidating virtual machines (VMs) can conserve energy consumption in clouds through VM migrations. VM-consolidation techniques, however, inevitably induce a burden on performance. To address this issue, we propose a holistic solution - EGRET - to boost energy efficiency of cloud computing platforms by seamlessly integrating the DVFS scheme with the VM-consolidation technique. EGRET dynamically determines the most energy-efficient strategy by issuing a command to either scale CPU frequencies on a VM or marking the VM as underutilized. We conduct extensive experiments to evaluate the performance of EGRET. the experimental results show that EGRET substantially improves the energy efficiency of cloud computing platforms.

关键词： Lead acid batteries Cloud computing Data centers Energy consumption Costs Conferences computer architecture

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Enhanced Multi-Model Feature Fusion for Categorizing Diabetic Retinopathy Severity level

Enhanced Multi-Model Feature Fusion for Categorizing Diabeti...

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International Conference on computing and Networking Technology (ICCNT)

作者： Deepika Lakshmi Kanumuri Gopika Ayinampudi Madhuri Kamma Somitha Anna B. Suvarna Department of Computer Science and Engineering Vignan’s Foundation for Science Technologyand Research (Deemed to be University) Guntur AP India

ISBN: (数字)9798350370249

ISBN: (纸本)9798350370270

Diabetic Retinopathy (DR), is a major concern for long-term diabetic individuals, leading to damage of eyesight if diagnosis is delayed. In this study, it aims to propose a multi-model fusion of two pre-trained models VGG19 and ResNet50, that leverages important details from the retinal fundus images. these are fused using a cross-pooling technique to capture significant image details, which are crucial for precise diagnosis. A neural network architecture is employed to classify DR severity levels with remarkable accuracy. this proposed model is experimented on the Kaggle APTOS 2019 dataset, which is a benchmark dataset. the results of Proposed model were impressive, achieving an accuracy of $83.33 \%$. this high accuracy demonstrates the effectiveness of our methodology and shows the potential of fusion-based method in diagnosing *** proposed model offers a promising path for early intervention and preserving vision in diabetic patients and also demonstrates remarkable performance, especially in categorizing normal, mild, and moderate stages of retinal fundus images.

关键词： Training Diabetic retinopathy Accuracy Computational modeling Neural networks computer architecture Medical services Benchmark testing Retina Residual neural networks

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A Charge-Digital Hybrid Compute-In-Memory Macro with full precision 8-bit Multiply-Accumulation for Edge computing Devices

A Charge-Digital Hybrid Compute-In-Memory Macro with full pr...

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IEEE International symposium on Embedded Multicore Socs (MCSoC)

作者： Jinwu Chen Tianzhu Xiong Xin Si National ASIC Center Southeast University Nanjing China

ISBN: (纸本)9781665465007

Compute-in-memory (CIM) is emerging as a new computing architecture to overcome the high energy consumption of edge-side AI and IoT devices. When performing high-precision neural network calculations, analog CIM and digital CIM have their own advantages and disadvantages. In this paper, we combine the advantages of high energy efficiency of analog CIM and high accuracy of digital CIM to propose a charge-digital hybrid CIM (CDH-CIM) macro. By placing the high bits in the digital domain and the low bits in the charge domain, the multiply-accumulation (MAC) operation of 8b input activations (lAs) and 8b weights is achieved with no precision loss. the proposed CDH-CIM macro is designed using 22nm FDSOI CMOS process. Simulation shows that the macro achieves 6.98~11.0 TOPS/W at 0.8V and 71.92% inference accuracy when performing CIFAR-100 dataset.

关键词： performance evaluation Semiconductor device modeling Energy consumption Multicore processing Neural networks Silicon-on-insulator computer architecture

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Against the Current: Introducing Reversibility to Superscalar Processors via Reversible Branch Predictors

Against the Current: Introducing Reversibility to Superscala...

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International Green computing Conference

作者： Byron Gregg Christof Teuscher Dept. of Electrical and Computer Engineering Portland State University Portland OR USA

ISBN: (数字)9798331507862

ISBN: (纸本)9798331507879

Although highly energy efficient, adiabatic and reversible systems suffer from performance drawbacks inherent to the physical operations that make them so efficient. Superscalar processors provide high performance through out-of-order speculative work of which an effective branch predictor is a key component in those performance gains. In the context of reversibility, a branch predictor is a design focal point because any fully reversible system must also be able to predict branch outcomes when in reverse mode. Taking advantage of Temporal Streaming techniques, this paper introduces several reversible branch predictor implementations which enable reversible and out-of-order instruction execution. these first-of-their-kind designs allow for a superscalar architecture that would maintain both a high level of performance and a high level of energy efficiency with the ability to un-compute obsolete data stored in memory. Testing our designs using the SimpleScalar out-of-order simulator, we estimate possible additional savings of 24 fJ per MB of data recovered at room temperature and at reverse prediction rates 2.27% higher than the forward. this work opens new avenues for designing and developing what we are calling Fully Adiabatic, Reversible, and Superscalar (FARS) Processor architectures and is the first of many adaptations of conventional superscalar components to a reversible system.

关键词： Out of order Context Temperature distribution Program processors Memory management performance gain Energy efficiency Testing

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A Decentralized Vehicle-to-Vehicle Energy Trading System Based on Efficient Sharding Services 21

A Decentralized Vehicle-to-Vehicle Energy Trading System Bas...

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21st IEEE International symposium on Parallel and Distributed Processing with Applications, 13th IEEE International Conference on Big Data and Cloud computing, 16th IEEE International Conference on Social computing and Networking and 13th International Conference on Sustainable computing and Communications, ISPA/BDCloud/SocialCom/SustainCom 2023

作者： Meng, Kun Sun, Lijun Chen, Xiao Wu, Haiqin Li, Shuaiyong Qingdao University of Science and Technology College of Information Science and Technology Shandong China University of Leicester School of Computing and Mathematical Sciences Leicester United Kingdom Software Engineering Institute Shanghai Key Laboratory of Trustworthy Computing East China Normal University Shanghai China Key Laboratory of Industrial Internet of Things and Networked Control Ministry of Education Chongqing China

ISBN: (纸本)9798350329223

Vehicle-to-vehicle (V2V) energy trading stands as a significant technology, allowing electric vehicles (EVs) to share energy. this balances energy demand and supply, reducing pressure on the power grid. However, two substantial challenges require attention: 1) Creating a standardized protocol universally adoptable by EV manufacturers and energy trading participants to establish a common secure and reliable platform for real-time energy trading between EVs. 2) Determining a fair and transparent pricing and transaction management mechanism, accounting for factors such as energy demand and supply, location, and user preferences. To tackle these hurdles, this paper proposes a decentralized V2V energy trading system (VETS) based on a novel high-performance sharding blockchain framework. VETS incorporates a standard energy trading management protocol, achieving trustless and transparent transaction processing. It employs a blockchain sharding and parallel architecture for high transaction throughput, catering to a large number of EVs. Furthermore, an efficient consensus algorithm is developed to minimize service delays and adapt to real-time transaction demands. A practical testbed operationalizes VETS, facilitating experimental analysis within a real-world cloud environment. © 2023 IEEE.

关键词： Blockchain

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Unlimited Vector Extension with Data Streaming Support 21

Unlimited Vector Extension with Data Streaming Support

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ACM/IEEE 48th Annual International symposium on computer architecture (ISCA)

作者： Domingos, Joao Mario Neves, Nuno Roma, Nuno Tomas, Pedro Univ Lisbon Inst Super Tecn INESC ID Lisbon Portugal INESC ID Inst Telecomunicacoes Lisbon Portugal

ISBN: (纸本)9781665433334

Unlimited vector extension (UVE) is a novel instruction set architecture extension that takes streaming and SIMD processing together into the modern computing scenario. It aims to overcome the shortcomings of state-of-the-art scalable vector extensions by adding data streaming as a way to simultaneously reduce the overheads associated with loop control and memory access indexing, as well as with memory access latency. this is achieved through a new set of instructions that pre-configure the loop memory access patterns. these attain accurate and timely data prefetching on predictable access patterns, such as in multidimensional arrays or in indirect memory access patterns. Each of the configured data streams is associated to a general-purpose vector register, which is then used to interface with the streams. In particular, iterating over a given stream is simply achieved by reading/writing to the corresponding input/output stream, as the data is instantly consumed/produced. To evaluate the proposed UVE, a proof-of-concept gem5 implementation was integrated in an out-of-order processor model, based on the ARM Cortex-A76, thus taking into consideration the typical speculative and out-of-order execution paradigms found in high-performance computing processors. the evaluation was carried out with a set of representative kernels, by assessing the number of executed instructions, its impact on the memory bus and its overall performance. Compared to other state-of-the-art solutions, such as the upcoming ARM Scalable Vector Extension (SVE), the obtained results show that the proposed extension attains average performance speedups over 2.4x for the same processor configuration, including vector length.

关键词： Scalable SIMD/Vector Processing Data Streaming Instruction Set Extension Processor Microarchitecture high-performance computing

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DYAD: Locality-aware Data Management for accelerating Deep Learning Training

DYAD: Locality-aware Data Management for accelerating Deep L...

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International symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Hariharan Devarajan Ian Lumsden Chen Wang Konstantia Georgouli Tom Scogland Jae-Seung Yeom Michela Taufer Lawrence Livermore National Laboratory University of Tennessee Knoxville

ISBN: (数字)9798350356168

ISBN: (纸本)9798350356175

Deep Learning (DL) is increasingly applied across various fields to solve complex scientific challenges in modern high-performance computing (HPC) systems that are beyond the reach of traditional algorithms. Training DL models for scientific applications involves processing multi-terabyte datasets in each epoch. the data access behavior during DL training exposes optimization opportunities to cache these datasets in near-compute storage accelerators in HPC systems, enhancing I/O throughput. However, current middleware solutions employ near-compute storage accelerators primarily as exclusive caches, which limits the effectiveness of cache access locality. To address this problem, we introduce DYAD, a system designed to maximize sample locality in the cache, thereby significantly increasing I/O throughput in HPC *** optimizes I/O for DL training based on three key features. First, DYAD boosts inter-node access speeds by using a novel streaming RPC with RDMA protocol, achieving a 1.25x performance gain over state-of-the-art solutions. Second, DYAD further enhances inter-node access by coordinating data movement, which mitigates network congestion and increases throughput for inter-node accesses by up to 8.78x. Last, DYAD uses smart metadata caching that outperforms traditional global metadata access methods by several orders of magnitude in terms of lookup throughput. We demonstrate how DYAD accelerates large-scale DL training on a high-end HPC cluster with 512 GPUs by up to 10.82x faster epochs compared to UnifyFS by performing locality-aware caching on near-compute storage accelerators.

关键词： Training Deep learning Protocols high performance computing Redundancy Termination of employment Metadata performance gain throughput Resource management

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