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Optimizing message aggregation for parallel simulation on high performance clusters

Optimizing message aggregation for parallel simulation on hi...

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Proceedings of the 1999 7th International symposium on Modeling, Analysis and Simulation of computer and Telecommunication Systems - MASCOTS '99

作者： Pham, C.D. Albrecht, C. Universite Claude Bernard Lyon I France

high performance clusters (HPCs) based on commodity hardware are becoming more and more popular in the parallel computing community. these new platforms offer a hardware capable of a very low latency and a very high throughput at an unbeatable cost, making them attractive for a large variety of parallel and distributed applications. With adequate communication software, HPCs have the potential to achieve a level of performance similar to massively parallel computers. However, for parallel applications that present a high communication/computation ratio, it is still essential to provide the lowest latency in order to minimize the communication overhead. In this paper, we are investigating message aggregation techniques to improve parallel simulations of fine-grain ATM communication network models. Even if message aggregation is a well-known solution for improving the communication performance of high latency interconnection networks, the complex interaction between message aggregation and the underlying communication software is often ignored. We show that message aggregation must carefully take into account the characteristics of the communication software to be efficient on an HPC. this methodology can be applied as a preliminary step to tune a message aggregation algorithm for a given combination of hardware architecture and communication software layer.

关键词： Parallel processing systems

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Building dependable distributed applications using AQUA 4

Building dependable distributed applications using AQUA

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4th IEEE International symposium on high-Assurance Systems Engineering, HASE 1999

作者： Ren, Jennifer Cukier, Michel Rubel, Paul Sanders, William H. Bakken, David E. Karr, David A. Center for Reliable and High-Performance Computing Coordinated Science Laboratory Department of Electrical and Computer Engineering University of Illinois at Urbana-Champaign UrbanaIL61801 United States BBN Technologies CambridgeMA02138 United States

ISBN: (纸本)0769504183

Building dependable distributed systems using ad hoc methods is a challenging task. Without proper support, an application programmer must face the daunting requirement of having to provide fault tolerance at the application level, in addition to dealing with the complexities of the distributed application itself. this approach requires a deep knowledge of fault tolerance on the part of the application designer, and has a high implementation cost. What is needed is a systematic approach to providing dependability to distributed applications. Proteus, part of the AQuA architecture, fills this need and provides facilities to make a standard distributed CORBA application dependable, with minimal changes to an application. Furthermore, it permits applications to specify, either directly or via the Quality Objects (QuO) infrastructure, the level of dependability they expect of a remote object, and will attempt to configure the system to achieve the requested dependability level. Our previous papers have focused on the architecture and implementation of Proteus. this paper describes how to construct dependable applications using the AQuA architecture, by describing the interface that a programmer is presented with and the graphical monitoring facilities that it provides. © 2017 IEEE.

关键词： Fault tolerance

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Dodo: A user-level system for exploiting idle memory in workstation clusters

Dodo: A user-level system for exploiting idle memory in work...

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Proceedings of the 1999 8th IEEE International symposium on high performance Distributed computing - HPDC-8

作者： Koussih, Samir Acharya, Anurag Setia, Sanjeev George Mason Univ Fairfax United States

In this paper, we present the design and implementation of Dodo, an efficient user-level system for harvesting idle memory in off-the-shelf clusters of workstations. Dodo enables data-intensive applications to use remote memory in a cluster as an intermediate cache between local memory and disk. It requires no modifications to the operating system and/or processor firmware and is hence portable to multiple platforms. Further, the memory recruitment policy used by Dodo is designed to minimize any delays experienced by the owner of desktop machines whose memory is harvested by Dodo. Our implementation of Dodo is operational and currently runs on Linux 2.0.35. For communication, Dodo can use either UDP/IP or U-Net. the low-latency user-level network architecture developed by von Eicken et al. We evaluated the performance improvements that can be achieved by using Dodo for two real applications and three synthetic benchmarks. Our results show that speedups obtained for an application are highly dependent on its I/O access pattern and data set sizes. Significant speedups (between 2 and 3) were obtained for applications whose working sets are larger than the local memory on a workstation but smaller than aggregate memory available on the cluster and for applications that can benefit from the zero-seek nature of remote memory.

关键词： Distributed computer systems

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MorphoSys: A reconfigurable processor targeted to high performance image application 13th

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13th International Parallel Processing symposium, IPPS 1999 Held in Conjunction with the 10th symposium on Parallel and Distributed Processing, SPDP 1999

作者： Lu, Guangming Lee, Ming-Hau Singh, Hartej Bagherzadeh, Nader Kurdahi, Fadi J. Filho, Eliseu M. Department of Electrical and Computer Engineering University of California IrvineCA92715 United States Department of Systems and Computer Engineering Federal University of Rio de Janeiro P.O.BOX 68511 Rio de JaneiroRJ21945-970 Brazil

ISBN: (纸本)3540658319

this paper addresses the design idea of the MorphoSys Reconfigurable processor developed by the researchers in the UC, Irvine. With the demand to perform the multimedia operations efficiently, it is one of the directions that general processor needs to incorporate with some reconfigurable computing units, like FPGA. In MorphoSys project, we successfully propose a prototype to fulfill the above trend, which is comprised of a simplified general purpose MIPS-like RISC processor, called TinyRISC and 8×8 coarse grained reconfigurable cells, organized as SIMD architecture. MorphoSys is realized using 0.35urn technology, and runs at 100Mhz with impressive performance enhancement compared with other architectures. © Springer-Verlag Berlin Heidelberg 1999.

关键词： Reconfigurable architectures

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Hardwired-clusters partial-crossbar: A hierarchical routing architecture for multi-FPGA systems 13th

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13th International Parallel Processing symposium, IPPS 1999 Held in Conjunction with the 10th symposium on Parallel and Distributed Processing, SPDP 1999

作者： Khalid, Mohammed A.S. Rose, Jonathan Quicktum Design Systems 55 West Trimble Road San JoseCA95131-1013 Canada Department of Electrical and Computer Engineering University of Toronto TorontoONM5S 3G4 Canada

ISBN: (纸本)3540658319

Multi-FPGA systems (MFSs) are used as custom computing machines, logic emulators and rapid prototyping vehicles. A key aspect of these systems is their programmable routing architecture which is the manner in which wires, FPGAs and Field-Programmable Interconnect Devices (FPIDs) are connected. Several routing architectures for MFSs have been proposed [Amo92] [Butt92] [Hauc94] [Apti96] [Vui196] [Babb97] and previous research has shown that the partial crossbar is one of the best existing architectures [Kim96] [Kha197]. Recently, the Hybrid Complete-Graph Partial-Crossbar architecture (HCGP) was proposed [Kha198], which was shown to be superior to the Partial Crossbar. In this paper we propose a new routing architecture, called the Hardwired-Clusters Partial-Crossbar (HWCP) which is better suited for large MFSs implemented using multiple boards. the HWCP architecture is compared to the HCGP and Partial Crossbar and we show that it gives substantially better manufacturability. We compare the performance and cost of the HWCP, HCGP and Partial Crossbar architectures experimentally, by mapping a set of 15 large benchmark circuits into each architecture. We show that the HWCP architecture gives reasonably good cost and speed compared to the HCGP and Partial Crossbar architectures. © Springer-Verlag Berlin Heidelberg 1999.

关键词： Field programmable gate arrays (FPGA)

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Fast hardware compilation of behaviors into an FPGA-based dynamic reconfigurable computing system 12

Fast hardware compilation of behaviors into an FPGA-based dy...

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12th Brazilian symposium on Integrated Circuits and Systems Design, SBCCI 1999

作者： Cardoso, Joéo M. P. Neto, Horácio C. INESC Univ. of Algarve Lisbon Portugal

ISBN: (纸本)076950387X

this paper presents new techniques for architecture and performance driven compilation of SW programs into RW (reconfigurable HW). these new techniques effectively improve on the complex resource sharing approaches typical of high-level synthesis algorithms, which are efficient for layout flexible ASICs but are clearly not adequate for reconfigurable devices with predefined architectures. the compilation flow takes advantage of a specialized library of circuit-generators and only resorts to logic synthesis for the generation of the data-path's control unit. the algorithms under development are being integrated onto an HW compiler that accepts programs previously compiled to JavaTM Bytecodes. A series of experiments has been performed using a number of practical examples and the results achieved so far are very promising and indicate that the RW compilation techniques proposed can provide significant improvements over currently available methods. © 2017 IEEE.

关键词： high level synthesis

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Parallelizing applications into silicon

Parallelizing applications into silicon

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Proceedings of the 7th Annual IEEE symposium on Field-Programmable Custom computing Machines (FCMM 1999)

作者： Babb, Jonathan Rinard, Martin Moritz, Csaba Andras Lee, Walter Frank, Matthew Barua, Rajeev Amarasinghe, Saman Laboratory for Computer Science Massachusetts Inst. of Technology Cambridge MA 02139 United States

the next decade of computing will be dominated by embedded systems, information appliances and application-specific computers. In order to build these systems, designers will need high-level compilation and CAD tools that generate architectures that effectively meet the needs of each application. In this paper we present a novel compilation system that allows sequential programs, written in C or FORTRAN, to be compiled directly into custom silicon or reconfigurable architectures. the capability is also interesting because trends in computer architecture are moving towards more reconfigurable hardware-like substrates, such as FPGA based systems. Our system works by successfully combining two resource-efficient computing disciplines: Small Memories and Virtual Wires. For a given application, the compiler first analyzes the memory access patterns of pointers and arrays in the program and constructs a partitioned memory system made up of many small memories. the computation is implemented by active computing elements that are spatially distributed within the memory array. A space-time scheduler assigns instructions to the computing elements in a way that maximizes locality and minimizes physical communication distance. It also generates an efficient static schedule for the interconnect. Finally, specialized hardware for the resulting schedule of memory accesses, wires, and computation is generated as a multi-process state machine in synthesizable Verilog. With this system, implemented as a set of SUIF compiler passes, we have successfully compiled programs into hardware and achieve specialization performance enhancements by up to an order of magnitude versus a single general-purpose processor. We also achieve additional parallelization speedups similar to those obtainable using a tightly-interconnected multiprocessor.

关键词： Program compilers

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Proceedings - Frontiers 1999, 7th symposium on the Frontiers of Massively Parallel Computation

Proceedings - Frontiers 1999, 7th Symposium on the Frontiers...

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7th symposium on the Frontiers of Massively Parallel Computation, Frontiers 1999

ISBN: (纸本)0769500870

the proceedings contain 35 papers. the topics discussed include: scalability analysis of multidimensional wavefront algorithms on large-scale SMP clusters;a system for evaluating performance and cost of SIMD array designs;design trade-offs of low-cost multicomputer network switches;the cactus computational collaboratory: enabling technologies for relativistic astrophysics, and a toolkit for solving PDEs by communities in science and engineering;the PETSc library for scientific software;distributed applet-based certifiable processing in client/server environments;large-scale distributed computational fluid dynamics on the information power grid using Globus;a framework for generating task parallel programs;HPF implementation of ARC3D;efficient VLSI layouts of hypercubic networks;adapting to load on workstation clusters;parallel simulation of two-phase flow problems using the finite element method;a data-parallel algorithm for iterative tomographic image reconstruction;parallel rendering of 3D AMR data on the SGUCray T3E;a recursive PVM implementation of an image segmentation algorithm with performance results comparing the hive and the Cray T3E;Delphi: an integrated, language-directed performance prediction, measurement and analysis environment;poems-end to end performance models for dynamic parallel and distributed systems;MPI: the only programming model for managing memory;distributed control parallelism for multidisciplinary design of a high speed civil transport;implementing MM5 on NASA Goddard space flight center computing systems: a performance study;and material science electronic structure calculations on massively parallel systems: an algorithmic and computational challenge.

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A Framework for Scheduling and Context Allocation in Reconfigurable computing 12

A Framework for Scheduling and Context Allocation in Reconfi...

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12th International symposium on System Synthesis, ISSS 1999

作者： Maestre, R. Fernandez, M. Hermida, R. Bagherzadeh, N. Departamento de Arquitectura de Computadores y Automática Universidad Complutense Madrid28040 Spain Department of Electrical and Computer Engineering University of California IrvineCA92697 United States

ISBN: (纸本)076950356X

Reconfigurable computing is emerging as a viable design alternative to implement a wide range of computationally intensive applications. the scheduling problem becomes a really critical issue in achieving the high performance that these kind of applications demands. this paper describes the different aspects regarding the scheduling problem in a reconfigurable architecture. We also propose a general strategy in order to perform at compilation time a scheduling that includes all possible optimizations regarding context (configuration) and data transfers. In particular, we focus especially on the methodology and mechanisms to solve the context scheduling. Some experimental results are presented to validate our assumptions. Finally, the problem of data transfers is only formulated and will be addressed in future work.

关键词： Scheduling

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Starfish: fault-tolerant dynamic MPI programs on clusters of workstations

Starfish: fault-tolerant dynamic MPI programs on clusters of...

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International symposium on high performance Distributed computing

作者： A.M. Agbaria R. Friedman Department of Computer Science Technion-Israel Institute of Technology Haifa Israel

this paper reports on the architecture and design of Starfish, an environment for executing dynamic (and static) MPI-2 programs on a cluster of workstations. Starfish is unique in being efficient, fault-tolerant, highly available, and dynamic as a system internally, and in supporting fault-tolerance and dynamicity for its application programs as well. Starfish achieves these goals by combining group communication technology with checkpoint/restart, and uses a novel architecture that is both flexible and portable and keeps group communication outside the critical data path, for maximum performance.

关键词： Fault tolerance Workstations Concurrent computing Communications technology computer networks Portable computers Operating systems Bandwidth computer science computer architecture

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