检索结果-内蒙古大学图书馆

International Conference on Data Engineering

作者： S.M. Baker B. Moon Department of Computer Science University of Arizona Tucson Tucson AZ USA

With the explosive popularity of the internet and the world wide web (WWW), there is a rapidly growing need to provide unprecedented access to globally distributed data sources through the internet. Web accessibility will be an essential component of the services that future digital libraries should provide for clients. this need has created a strong demand for database access capability through the internet, and high performance scalable web servers. As most popular web sites are experiencing overload from an increasing number of users accessing the sites at the same time, it is desired that scalable web servers should adapt to the changing access characteristics and should be capable of handling a large number of concurrent requests simultaneously, with reasonable response times and minimal request drop rates.

关键词： Web server Internet Load management Home computing Network servers Moon Explosives Web sites World Wide Web Databases

来源：评论

学校读者我要写书评

暂无评论

Series approximation methods for divide and square root in the Power3/sup TM/ processor

Series approximation methods for divide and square root in t...

引用

computer Arithmetic (ARIth)

作者： R.C. Agarwal F.G. Gustavson M.S. Schmookler Research Division IBM Corporation Yorktown NY USA Server Development IBM Corporation Austin TX USA

the Power3 processor is a 64-bit implementation of the PowerPC/sup TM/ architecture and is the successor to the Power2/sup TM/ processor for workstations and servers which require high performance floating point capability. the previous processors used Newton-Raphson algorithms for their implementations of divide and square root. the Power3 processor has a longer pipeline latency, which would substantially increase the latency for these instructions. Instead, new algorithms based on power series approximations were developed which provide significantly better performance than the Newton-Raphson algorithm for this processor. this paper describes the algorithms, and then shows how both the series based algorithms and the Newton-Raphson algorithms are affected by pipeline length. For the Power3, the power series algorithms reduce the divide latency by over 20% and the square root latency by 35%.

关键词： Approximation methods Delay Pipelines Frequency Hardware Table lookup Silicon Reduced instruction set computing Microprocessor chips Algorithm design and analysis

来源：评论

学校读者我要写书评

暂无评论

Building dependable distributed applications using AQUA

Building dependable distributed applications using AQUA

引用

IEEE International Symposim on high Assurance Systems Engineering

作者： J. Ren M. Cukier P. Rubel W.H. Sanders D.E. Bakken D.A. Karr Center for Reliable and High-Performance Computing Coordinated Science Laboratory and Department of Electrical and Computer Engineering University of Illinois Urbana IL USA BBN Technologies GTE Cambridge MA USA

Building dependable distributed systems using ad hoc methods is a challenging task. Without proper support, an application programmer must face the daunting requirement of having to provide fault tolerance at the application level, in addition to dealing with the complexities of the distributed application itself. this approach requires a deep knowledge of fault tolerance on the part of the application designer, and has a high implementation cost. What is needed is a systematic approach to providing dependability to distributed applications. Proteus, part of the AQuA architecture, fills this need and provides facilities to make a standard distributed CORBA application dependable, with minimal changes to an application. Furthermore, it permits applications to specify, either directly or via the Quality Objects (QuO) infrastructure, the level of dependability they expect of a remote object, and will attempt to configure the system to achieve the requested dependability level. Our previous papers have focused on the architecture and implementation of Proteus. this paper describes how to construct dependable applications using the AQuA architecture, by describing the interface that a programmer is presented with and the graphical monitoring facilities that it provides.

关键词： Electrical capacitance tomography Fault tolerance Buildings Application software Quality of service Contracts Hardware Runtime Object detection Tellurium

来源：评论

学校读者我要写书评

暂无评论

Efficient VLSI implementation of modulo (2/sup n//spl plusmn/1) addition and multiplication

Efficient VLSI implementation of modulo (2/sup n//spl plusmn...

引用

computer Arithmetic (ARIth)

作者： R. Zimmermann Swiss Federal Institute of Technology (ETH) Integrated Circuits and Systems Laboratory Zurich Switzerland

New VLSI circuit architectures for addition and multiplication modulo (2/sup n/-1) and (2/sup n/+1) are proposed that allow the implementation of highly efficient combinational and pipelined circuits for modular arithmetic. It is shown that the parallel-prefix adder architecture is well suited to realize fast end-around-carry adders used for modulo addition. Existing modulo multiplier architectures are improved for higher speed and regularity. these allow the use of common multiplier speed-up techniques like Wallace-tree addition and Booth recoding, resulting in the fastest known modulo multipliers. Finally, a high-performance modulo multiplier-adder for the IDEA block cipher is presented. the resulting circuits are compared qualitatively and quantitatively, i.e., in a standard-cell technology, with existing solutions and ordinary integer adders and multipliers.

关键词： Very large scale integration Arithmetic Concurrent computing Logic Equations Data preprocessing

来源：评论

学校读者我要写书评

暂无评论

A hardware-driven profiling scheme for identifying program hot spots to support runtime optimization 99

A hardware-driven profiling scheme for identifying program h...

引用

Proceedings of the 26th annual international symposium on computer architecture

作者： Matthew C. Merten Andrew R. Trick Christopher N. George John C. Gyllenhaal Wen-mei W. Hwu Center for Reliable and High-Performance Computing Department of Electrical and Computer Engineering University of Illinois Urbana IL

ISBN: (纸本)9780769501703

this paper presents a novel hardware-based approach for identifying, profiling, and monitoring hot spots in order to support runtime optimization of general purpose programs. the proposed approach consists of a set of tightly coupled hardware tables and control logic modules that are placed in the retirement stage of a processor pipeline removed from the critical path. the features of the proposed design include rapid detection of program hot spots after changes in execution behavior, runtime-tunable selection criteria for hot spot detection, and negligible overhead during application execution. Experiments using several SPEC95 benchmarks, as well as several large WindowsNT applications, demonstrate the promise of the proposed design.

关键词：

来源：评论

学校读者我要写书评

暂无评论

the program decision logic approach to predicated execution 99

The program decision logic approach to predicated execution

引用

Proceedings of the 26th annual international symposium on computer architecture

作者： David I. August John W. Sias Jean-Michel Puiatti Scott A. Mahlke Daniel A. Connors Kevin M. Crozier Wen-mei W. Hwu Center for Reliable and High-Performance Computing University of Illinois Urbana-Champaign IL Logic Systems Laboratory (DI-LSL) Swiss Federal Institute of Technology of Lausanne (EPFL) CH-1015 Lausanne Switzerland Hewlett-Packard Laboratories Hewlett-Packard Palo Alto CA

ISBN: (纸本)9780769501703

Modern compilers must expose sufficient amounts of Instruction-Level Parallelism (ILP) to achieve the promised performance increases of superscalar and VLIW processors. One of the major impediments to achieving this goal has been inefficient programmatic control flow. Historically, the compiler has translated the programmer's original control structure directly into assembly code with conditional branch instructions. Eliminating inefficiencies in handling branch instructions and exploiting ILP has been the subject of much research. However, traditional branch handling techniques cannot significantly alter the program's inherent control structure. the advent of predication as a program control representation has enabled compilers to manipulate control in a form more closely related to the underlying program logic. this work takes full advantage of the predication paradigm by abstracting the program control flow into a logical form referred to as a program decision logic network. this network is modeled as a Boolean equation and minimized using modified versions of logic synthesis techniques. After minimization, the more efficient version of the program's original control flow is re-expressed in predicated code. Furthermore, this paper proposes extensions to the HPL PlayDoh predication model in support of more effective predicate decision logic network minimization. Finally, this paper shows the ability of the mechanisms presented to overcome limits on ILP previously imposed by rigid program control structure.

关键词：

来源：评论

学校读者我要写书评

暂无评论

Proceedings - symposium on computer architecture and high performance computing

Proceedings - Symposium on Computer Architecture and High Pe...

引用

5th International Conference on high performance computing, HiPC 1998

ISBN: (纸本)0818691948

the proceedings contain 61 papers. the topics discussed include: new number representation and conversion techniques on reconfigurable mesh;precise control of instruction caches;more on arbitrary boundary packed arithmetic;more on arbitrary boundary packed arithmetic;PERL - a registerless architecture;design alternatives for shared memory multiprocessors;a simple optimal list ranking algorithm;a parallel skeletonization algorithm and its VLSI architecture;improving error bounds for multipole-based treecodes;computation of penetration measures for convex polygons and polyhedra for graphics applications;extrapolation in distributed adaptive integration;and java data parallel extensions with runtime system support.

关键词：

来源：评论

学校读者我要写书评

暂无评论

A multipole accelerated desingularized method for computing nonlinear wave forces on bodies

引用

JOURNAL OF OFFSHORE MECHANICS AND ARCTIC ENGINEERING-TRANSACTIONS OF thE ASME 1998年第2期120卷 71-76页

作者： Scorpio, SM Beck, RF Univ Michigan Dept Naval Architecture & Marine Engn Ann Arbor MI 48103 USA

Nonlinear wave farces on offshore structures are investigated. the fluid motion is computed using a Euler-Lagrange time-domain approach. Nonlinear free surface boundary conditions are stepped forward in time using an accurate and stable integration technique. the field equation with mixed boundary conditions that result at each time step are salved at N nodes using a desingularized boundary integral method with multipole acceleration Multipole accelerated solutions require O(N) computational effort and computer storage, while conventional solvers require O(N-2) effort and storage for an iterative solution and O(N-3) effort for direct inversion of the influence matrix. these methods are applied to the three-dimensional problem of wave diffraction by a vertical cylinder.

关键词： Offshore structures Fluid motion Body WAVE FORCES FIELD EQUATIONS computer storage nonlinearity MULTIPOLES wave diffraction Nonlinear waves Vertical cylinder iterative solution Boundary conditions

来源：评论

学校读者我要写书评

暂无评论

FPGA based custom computing machines for irregular problems

FPGA based custom computing machines for irregular problems

引用

Proceedings of the 1998 4th International symposium on high-performance computer architecture, HPCA

作者： Abramson, David Logothetis, Paul Postula, Adam Randall, Marcus Monash Univ Clayton Australia

Over the past few years there has been increased interest in building custom computing machines (CCMs) as a way of achieving very high performance on specific problems. the advent of high density field programmable gate arrays (FPGAs), in combination with new synthesis tools, have made it relatively easy to produce programmable custom machines without building specific hardware. In many cases, the performance achieved by a FPGA based custom computer is attributed to the exploitation of massive concurrency in the underlying application. In this paper we explore the sources of speedup for irregular problems in which is difficult to exploit such parallelism. We highlight 5 main sources of speedup that we have observed, namely the provision of high memory bandwidth, the use of flexible address generation hardware, the use of gather-scatter array operations, the use of lookup tables and the use of multiple tailored arithmetic units. By considering some representative examples of such irregular problems, the paper illustrates that good performance is possible given the current generation of FPGA devices and RISC processors. the paper then explores whether this performance gain will be possible given the next generation of RISC processors and FPGAs. It concludes that the only way to maintain the speedup is to alter the architecture of CCMs in combination with architectural changes to the FPGAs themselves.

关键词： Parallel processing systems

来源：评论

学校读者我要写书评

暂无评论

ACEcardTM: A high-performance architecture for run-time reconfiguration 1

ACEcardTM: A high-performance architecture for run-time reco...

引用

Proceedings of the 1998 12th International Parallel Processing symposium and 9th symposium on Parallel and Distributed Processing

作者： Davis, Don Harris, Jonathan TSI TelSys Inc Columbia United States

ISBN: (纸本)0818684038

Recent FPGA architectures have shown an increased emphasis on run-time reconfiguration, or the ability to rapidly change the functionality of the FPGA to sequentially accommodate large processing tasks. In addition, partial reconfiguration allows for the reconfiguration of a portion of the FPGA while the remainder is running. these two features enable the use of reconfigurable computing in high-performance multi-threaded multi-user environments. However, current board designs are not optimized to provide the processing support required to maintain this run-time environment which includes management of the reconfigurable resources, interface to the host processor and data movement. In this paper, we will describe the architecture, design and applicability of the ACEcard, a high performance reconfigurable co-processor. the ACEcard contains reconfigurable resources as well as an embedded processor to manage the runtime reconfiguration of those resources. We will provide details of the architecture of the card as well as a description of the current and future Java-based runtime environment.

关键词： computer architecture

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：