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Modeling the effects of contention on the performance of heterogeneous applications 96

Modeling the effects of contention on the performance of het...

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International symposium on high performance Distributed computing

作者： S.M. Figueira F. Berman Computer Science and Engineering Department University of California San Diego USA

ISBN: (纸本)9780818675829

Fast networks have made it possible to coordinate distributed heterogeneous CPU, memory and storage resources to provide a powerful platform for executing high-performance applications. However, the performance of these applications on such systems is highly dependent on the allocation and efficient coordination of application tasks. A key component for a performance-efficient allocation strategy is a predictive model which provides a realistic estimate of application performance under varying resource loads. In this paper, we present a model for predicting the effects of contention on application behavior in heterogeneous systems. In particular, our model calculates the slowdown imposed on communication and computation for non-dedicated two-machine heterogeneous platforms. We describe the model for the Sun/CM2 and Sun/Paragon coupled heterogeneous systems. We present experiments on production systems with emulated contention which show the predicted communication and computation costs to be within 15% on average of the actual costs.

关键词： Application software Predictive models Central Processing Unit Workstations computer science Power engineering and energy Resource management Power system modeling Production systems Computational efficiency

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Preliminary insights on shared memory PIC code performance on the Convex Exemplar SPP1000

Preliminary insights on shared memory PIC code performance o...

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Frontiers of Massively Parallel Computation

作者： P. MacNeice C.M. Mobarry J. Crawford T.L. Sterling Goddard Space Flight Center Hughes STX Greenbelt MD USA Goddard Space Flight Center NASA USA USRA California Institute of Technology USA

We implement a 3D Electrostatic Particle in Cell (PIC) code on the HP-Convex Exemplar SPP1000. Our principal goals are to identify the best PIC algorithm for this architecture and capture its performance, and to explore whether the architecture and system software achieve an efficient and scalable shared memory programming environment. We show that PIC codes can achieve good performance on the Exemplar. However to achieve this performance great care is required in minimizing long latencies to remote memory and in maximizing cache reuse. Combined, these two requirements for avoiding performance degradation due to latency resulted in a complex programming task and diminished significantly many advantages that the shared memory hardware provided towards ease-of-use. Our best performing code avoided stressing the cache coherency hardware. Best performance was achieved by storing the particle data in 'processor local' memory blocks, and by intermittent sorting of the particle data to improve processor cache reuse.

关键词： Space technology computer architecture Electrostatics Plasma simulation high performance computing Concurrent computing NASA Software algorithms System software Programming environments

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Modeling and analysis of task migration in shared-memory multiprocessor computer systems

Modeling and analysis of task migration in shared-memory mul...

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International symposium on Modeling, Analysis and Simulation of computer and Telecommunication Systems (MASCOTS)

作者： R.D. Nelson M.S. Squillante OTA Limited Partnership Purchase NY USA IBM Research Division IBM Thomas J. Watson Research Center Yorktown Heights NY USA

In this paper we study a tradeoff between keeping the system workload balanced and scheduling tasks where they run most efficiently in shared-memory multiprocessor commercial environments. We formulate a general model of receiver-initiated task migration and derive a mathematical analysis of the model. Our results yield insights and information that can be used to design and develop adaptive scheduling policies for high-performance computing and telecommunication systems.

关键词： Processor scheduling Mathematical model Mathematical analysis System performance Adaptive scheduling Telecommunication computing computer architecture Costs Multiprocessing systems

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the core Legion object model 96

The core Legion object model

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International symposium on high performance Distributed computing

作者： M. Lewis A. Grimshaw Department of Computer Science University of Virginia Charlottesville VA USA University of Virginia Charlottesville VA US Dept. of Comput. Sci. Virginia Univ. Charlottesville VA USA

ISBN: (纸本)9780818675829

the Legion project at the University of Virginia is an architecture for designing and building system services that provide the illusion of a single virtual machine to users, a virtual machine that provides secure shared object and shared name spaces, application adjustable fault tolerance, improved response time, and greater throughput. Legion targets wide area assemblies of workstations, supercomputers, and parallel supercomputers. Legion tackles problems not solved by existing workstation based parallel processing tools; the system will enable fault tolerance, wide area parallel processing, interoperability, heterogeneity, a single global name space, protection, security, efficient scheduling, and comprehensive resource management. the paper describes the core Legion object model, which specifies the composition and functionality of Legion's core objects-those objects that cooperate to create, locate, manage, and remove objects in the Legion system. the object model facilitates a flexible extensible implementation, provides a single global name space, grants site autonomy to participating organizations, and scales to millions of sites and trillions of objects.

关键词： Virtual machining Fault tolerant systems Workstations Supercomputers Parallel processing Buildings Delay throughput Assembly Protection

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Hierarchical processors-and-memory architecture for high performance computing

Hierarchical processors-and-memory architecture for high per...

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Frontiers of Massively Parallel Computation

作者： Z.B. Miled R. Eigenmann J.A.B. Fortes V. Taylor School of ECE Purdue University West Lafayette IN USA Department of EECS Northwestern University Evanston IL USA

this paper outlines a cost-effective multiprocessor architecture that takes into consideration the importance of hardware and software costs as well as delivered performance in the context of real applications. the proposed architecture, HPAM, is organized as a hierarchy of processors-and-memory subsystems. Each subsystem contains a homogeneous parallel machine. Across the levels of the hierarchy, processor speeds and interconnection technology vary. the HPAM design is driven by several considerations: the observed characteristics of real applications, cost-efficiency considerations and the need for ease-of-usage. Rationales and the results of a preliminary study that motivated the design of this architecture are presented. these results include benchmark data that expose the advantages of HPAM over other architectures. Technology trends that support the desirability and viability of the proposed machine organization are also presented. Two classes of applications that demand 100 Teraops computation rates and that will drive future HPAM work are discussed. Furthermore a flexible software environment is proposed for this architecture, which facilitates several programming scenarios: automatic program translation, library based programming and performance-guided coding by expert programmers.

关键词： computer architecture Software performance Application software Automatic programming Hardware Costs Parallel machines Drives Software libraries Programming profession

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Simulation of heterogeneous networks of workstations

Simulation of heterogeneous networks of workstations

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International symposium on Modeling, Analysis and Simulation of computer and Telecommunication Systems (MASCOTS)

作者： Zhichen Xu Computer Sciences Department University of Wisconsin Madison Madison WI USA

ISBN: (纸本)0818672358

A network of workstations (NOW) has become an important distributed platform for large-scale scientific computations. A practical NOW system is heterogeneous and nondedicated, where computing power varies among the workstations and multiple jobs may interact with each other during execution. I present the design and implementation of a simulation system for a nondedicated heterogeneous NOW. this simulator provides many options to users to specify and quantify system architectures, network heterogeneity and time-sharing factors, such as speeds of different processors, memory organizations, network topology, communication structures, and workload distributions. the simulator also supports execution of message-passing parallel programs written in C and the PVM library. the software structure of the simulator is well-modularized and highly extensible, which makes it easy to integrate other existing processor, memory and network simulators.

关键词： Workstations Computational modeling Distributed computing computer networks Time sharing computer systems computer architecture Network topology Software libraries high performance computing Scheduling

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Architectural simulation system for M.f.a.s.t

Architectural simulation system for M.f.a.s.t

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Annual symposium on Simulation

作者： C.H.L. Moller G.G. Pechanek Microelectronics Division IBM Research Triangle Park NC USA

the paper discusses the simulation system used to verify the architecture of the Mwave folded array signal transform (M.f.a.s.t.) processor, a single chip scalable very long instruction word (VLIW) processor array being developed by IBM Microelectronics. M.f.a.s.t. simulation, at this stage of development of the architecture, is at a very high abstract level and is intended to meet the requirements of being implementation independent and permit investigation of the architecture itself, as opposed to simply verifying the congruence of the architecture and an implementation of it. the M.f.a.s.t. simulator uses a collection of functional models, implemented in C, to represent the M.f.a.s.t. architecture. the models, each reflecting the behaviour of a component of the architecture, run as independent processes and communicate among themselves using a socket mechanism. this paper discusses the merits and mechanics of this approach, and the reasons it was adopted. Two large applications and many small test cases have been written for the M.f.a.s.t. architecture and run on the M.f.a.s.t simulator. While it is difficult, for reasons that are discussed, to make easily interpretable statements about the performance of the simulator, data from these examples indicate that the simulator will emulate the execution, under average conditions, of approximately 3000 execution-unit operations per second.

关键词： Parallel processing Computational modeling VLIW Microelectronics Testing Digital signal processing Video compression computer aided instruction Concurrent computing computer architecture

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A low-complexity parallel system for gracious scalable performance. Case study for near PetaFLOPS computing

A low-complexity parallel system for gracious scalable perfo...

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Frontiers of Massively Parallel Computation

作者： S.G. Ziavras H. Grebel A. Chronopoulos Department of Electrical and Computer Engineering New Jersey Institute of Technology Newark NJ USA New Jersey Institute of Technology Newark NJ US Department of Computer Science Wayne State University Detroit MI USA

this paper presents a "point design" for an MIMD distributed shared-memory parallel computer capable of achieving gracious 100 TeraFLOPS performance with technology that will definitely become feasible/viable in less than a decade. Its scalability guarantees a lifetime extending well into the next century. the design takes advantage of free-space optical technologies, with simple guided-wave concepts, to produce a 1-D building block (BB) that implements efficiently a large, fully-connected system of processors. Designing fully-connected, large systems of electronic processors could be an immediate impact of optics on massively-parallel processing. A 2-D structure is proposed for the complete system, where the aforementioned 1-D BB is extended into two dimensions. this architecture behaves like a 2-D generalized hypercube, which is characterized by outstanding performance and extremely high wiring complexity that prohibits its electronic implementation. With readily available technology, a mesh of clear plastic bars in our design facilitate bit-parallel transmissions that utilize wavelength-division multiplexing and follow dedicated optical paths. Each processor is mounted on a card. Each card contains eight processors interconnected locally via an electronic crossbar. Taking advantage of higher-speed optical technologies all eight processors share the same interface to the optical medium. Encouraging, preliminary results prove that our conservative design could have a tremendous, positive impact on massively-parallel computing in the near future.

关键词： Optical design Optical interconnections Concurrent computing Distributed computing Scalability Process design Two dimensional displays Hypercubes Ultraviolet sources Wiring

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Fault/failure analysis of the Tandem NonStop-UX operating system

Fault/failure analysis of the Tandem NonStop-UX operating sy...

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Conference on Digital Avionics Systems (DASC)

作者： R.K. Iyer Mei-Chen Hsueh I. Lee Center for Reliable and High-Performance Computing Coordinated Science Laboratory University of Illinois Urbana IL USA Systems Development Group Tandem Computers Inc.orporated Cupertino CA USA

this paper presents the results of an analyse's of failures in several releases of Tandem's NonStop-UX operating system. NonStop-UX is based on UNIX System V. the analysis covers software failures from the field and failures reported by Tandem's test center. Faults are classified based on the status of the reported failures, the locations of the code that detected the problems, the panic messages generated by the systems, the faulty source modules, and the types of developer's mistakes. We present distributions of the failure and repair times for unique and duplicate failures. We also discuss how the analysis results can be used for assessing the dependability of the operating system and guiding improvement efforts.

关键词： Failure analysis Operating systems Kernel System testing computer crashes Software testing Fault detection Hardware Data structures Information analysis

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U-Net: A user-level network interface for parallel and distributed computing 95

U-Net: A user-level network interface for parallel and distr...

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15th ACM symposium on Operating Systems Principles, SOSP 1995

作者： Von Eicken, thorsten Basu, Anindya Buch, Vineet Vogels, Werner Department of Computer Science Cornell University Ithaca NY 14853 United States

ISBN: (纸本)0897917154

the U-Net communication architecture provides processes with a virtual view of a network interface to enable user-level access to high-speed communication devices. the architecture, implemented on standard workstations using off-the-shelf ATM communication hardware, removes the kernel from the communication path, while still providing full protection. the model presented by U-Net allows for the construction of protocols at user level whose performance is only limited by the capabilities of network. the architecture is extremely flexible in the sense that traditional protocols like TCP and UDP, as well as novel abstractions like Active Messages can be implemented efficiently. A U-Net prototype on an 8-node ATM cluster of standard workstations offers 65 microseconds round-trip latency and 15 Mbytes/sec bandwidth. It achieves TCP performance at maximum network bandwidth and demonstrates performance equivalent to Meiko CS-2 and TMC CM-5 supercomputers on a set of Split-C benchmarks. © 1995 ACM.

关键词： Bandwidth

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