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Integrating networks and memory hierarchies in a multicomputer node architecture

Integrating networks and memory hierarchies in a multicomput...

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International symposium on Parallel Processing

作者： L. Choi A.A. Chien CSRD University of Illinois Urbana IL USA Department of Computer Science University of Illinois Urbana IL USA

We propose a new multicomputer node architecture, the DI-multicomputer, which can provide higher memory and communication performance than existing multicomputer architectures. By integrating a router onto each processor chip and eliminating the memory bus interface, each processor uses packet routing for both local memory access and internode communication. Multi-packet handling mechanisms are used to implement a high performance memory interface based on packet routing. the DI-multicomputer network interface directs different types of messages to an appropriate level of the memory hierarchy, providing efficient communication for both short and long messages. Trace-driven simulations show that the communication mechanisms of the DI-multicomputer can achieve up to four times speedup when compared to existing architectures.< >

关键词： Intelligent networks Routing computer architecture Bandwidth Network interfaces computer networks Concurrent computing Application software Delay Computational modeling

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the effect of speculative execution on cache performance

The effect of speculative execution on cache performance

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International symposium on Parallel Processing

作者： J. Pierce T. Mudge University of Michigan USA

Superscalar microprocessors obtain high performance by exploiting parallelism at the instruction level. To effectively use the instruction-level parallelism found in general purpose, non-numeric code, future processors will need to speculatively execute far beyond instruction fetch limiting conditional branches. One result of this deep speculation is an increase in the number of instruction and data memory references due to the execution of mispredicted paths. Using a tool we developed to generate speculative traces from Intel architecture Unix binaries, we examine the differences in cache performance between speculative and non-speculative execution models. the results pertaining to increased memory traffic mispredicted path reference effects, allocation strategies, and speculative write buffers are discussed.< >

关键词： Parallel processing computer architecture Concurrent computing Pipelines Microprocessors Traffic control computer aided instruction Pollution Prefetching Instruments

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Simulation and performance evaluation of a parallel architecture for signal processing

Simulation and performance evaluation of a parallel architec...

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Southeastern symposium on System theory

作者： S. Howard W. Alexander Electrical and Computer Engineering North Carolina State University Raleigh NC USA

the authors have developed a conceptual design for a multiprocessor system to implement multidimensional digital signal processing applications. their approach is to develop an application specific computing system instead of a specific hardware solution. the application specific computing system can be used as a research tool for exploring new approaches to problems. In addition, it can be used to achieve high performance at reasonable costs since it can use commercially available processors. they present a performance evaluation of our system using the 2-D FIR filter as an example. they explain their approach to implementing the 2-D FIR filter by first reviewing their previous implementation of the 2-D IIR filter.< >

关键词： Parallel architectures computer applications Finite impulse response filter Computational modeling Signal design Multiprocessing systems Multidimensional signal processing Digital signal processing Hardware Costs

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A scalable sharing architecture for a parallel database system

A scalable sharing architecture for a parallel database syst...

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International symposium on Parallel and Distributed Processing (IPDPS)

作者： V. Gottemukkala E. Omiecinski U. Ramachandran College of Computing Georgia Institute of Technology Atlanta GA USA

Exploiting parallelism is a key to building high-performance database systems. Several approaches to building database systems that support both inter- and intra-query parallelism have been proposed. these approaches can be broadly classified as either Shared Nothing (SN) or Shared Everything (SE). Although the SN approach is highly scalable, it requires complex data partitioning and tuning to achieve good performance whereas the SE approach suffers from non-scalability. We propose a scalable sharing approach which combines the advantages of both SN and SE. We propose a comprehensive database architecture that includes the underlying hardware, and data partitioning and scheduling strategies, to promote scalable sharing. We analyze the performance and scalability of our approach and compare with that of a SN system. We find that for a variety of workloads and data skew our approach performs and scales at least as well as a SN system that uses the best possible data partitioning strategy.< >

关键词： Database systems Tin Scalability Parallel processing Hardware Scheduling computer architecture Educational institutions Concurrent computing Buildings

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Distributed image edge detection methods and performance

Distributed image edge detection methods and performance

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International symposium on Parallel and Distributed Processing (IPDPS)

作者： Xiaodong Zhang Hong Deng High-Performance Computing and Software Laboratory University of Texas San Antonio San Antonio TX USA

ISBN: (纸本)0818664274

An edge detection process in computer vision and image processing detects any types of significant features appearing as discontinuities in intensities. this paper presents our experience with parallelizing an edge detection application algorithm that reduces noise and unnecessary detail in a gray-scale image from a coarse level to a fine level of resolution by using an edge focusing technique. Numerical methods and parallel implementations of edge focusing are presented. the image detection algorithms are implemented on three representative message-passing architectures: a low-cost heterogeneous PVM network, an Intel iPSC/860 hypercube, and a CM-5 massively parallel multicomputer. Our objectives are to provide insight into implementation and performance issues for image processing applications on general-purpose message-passing architectures, to investigate implications an network variations, and to evaluate the computing scalabilities on the three network systems by examining execution and communication patterns of the image edge detection application.< >

关键词： Image edge detection Image processing Focusing computer architecture computer vision Application software Noise reduction Noise level Gray-scale Image resolution

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An efficient dynamic processor allocation algorithm for adaptive mesh applications

An efficient dynamic processor allocation algorithm for adap...

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International symposium on Parallel and Distributed Processing (IPDPS)

作者： R. Varadarajan Injae Hwang Department of Mathematics University of Puerto Rico Rio Piedras Puerto Rico CIS Department University of Florida Gainesville FL USA

In numerical algorithms based on adaptive mesh refinement, the computational workload changes during their execution. In mapping such algorithms on to distributed memory architectures, it is necessary to balance the workload among the processors dynamically in order to obtain high performance. In this paper, we propose a dynamic processor allocation algorithm for a mesh architecture that reassigns the workload in an attempt to minimize both the computational and communication costs. Our algorithm is based on a heuristic for a 2D packing problem that gives provably close to optimal solutions for special cases of the problem. We also demonstrate through experiments how our algorithm provides good quality solutions in general.< >

关键词： Heuristic algorithms Costs Load management Distributed computing computer architecture Finite difference methods Mathematics Memory architecture Concurrent computing Very large scale integration

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A class of scalable architectures for high-performance, cost-effective parallel computing

A class of scalable architectures for high-performance, cost...

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International symposium on Parallel and Distributed Processing (IPDPS)

作者： S.G. Ziavras Department of Electrical and Computer Engineering New Jersey Institute of Technology Newark NJ USA

the family of reconfigurable generalized hypercube (RGH) architectures is proposed for the construction of scalable parallel computers. the objective is to reduce the high VLSI complexity of generalized hypercubes while maintaining to high extent their outstanding performance. Generalized hypercubes are versatile topologies of very high cost that optimally emulate binary hypercubes and k-ary n-cubes. RGH's, which are lower-cost reconfigurable systems, emulate efficiently generalized hypercubes for application algorithms that use regular communication patterns. RGH's generally perform better than binary hypercubes and k-ary n-cubes with the same number of nodes. To illustrate the viability of RGH's, extensive cost analysis and comparisons with relevant systems are carried out. the hardware cost of RGH's is shown to be even lower than that of fat trees. therefore, scalable RGH's are viable candidates for the construction of versatile parallel computers.< >

关键词： computer architecture Parallel processing Hypercubes Very large scale integration Topology Concurrent computing Cost function Emulation Nearest neighbor searches Hardware

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performance of SPEC92 on prime-mapped vector cache

Performance of SPEC92 on prime-mapped vector cache

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International symposium on Parallel and Distributed Processing (IPDPS)

作者： Tong Sun Qing Yang Department of Electrical and Computer Engineering University of Rhode Island USA

ISBN: (纸本)0818664274

In this paper, we use execution-driven simulation to study and compare vector processing performances, in terms of the total execution time of an application program, of cache-based vector computers with that of uncached vector computers having a large number of interleaved memory banks. the cache memory used here is a new cache organization called prime-mapped cache. Simulation results on SPEC92 benchmarks show that the cache-based vector computers perform significantly better than the vector computers with no cache. the performance improvement is getting larger as the speed gap between processors and memories grows. Meanwhile, the cache-based vector computers are also cost-effective because of the reduction of large number of interleaved memory banks otherwise needed by vector computers with no cache.< >

关键词： Computational modeling Registers Cache memory computer architecture computer simulation high performance computing Analytical models Vector processors performance analysis Sun

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Application-specific array processors for binary prefix sum computation

Application-specific array processors for binary prefix sum ...

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International symposium on Parallel and Distributed Processing (IPDPS)

作者： R. Lin S. Olariu Department of Computer Science SUNY at Geneseo NY USA Department of Computer Science Old Dominion University Norfolk VA USA

the main contribution of this work is to propose two application-specific bus architectures for computing the prefix sums of a binary sequence. Our architectures feature the following characteristics: all broadcasts occur on buses of length 15 or 63; we use a new technique that we call shift switching which allows switches to cyclically permute an incoming signal, dramatically improving the performance of the reconfigurable bus system. As it turns out, our special-purpose architectures improve the performance of the best algorithms known to date by a significant factor. Specifically, our solutions require no adders, are faster, and use less VLSI area than the architectures of the state of the art.< >

关键词： Switches computer architecture Broadcasting Delay computer science Very large scale integration Optical arrays Arithmetic Computational modeling Binary sequences

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Cyclo-static multiprocessing model and simulation results

Cyclo-static multiprocessing model and simulation results

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Annual symposium on Simulation

作者： Sukhamoy Som Lockheed Eng. & Sci. Co. Hampton VA USA

ISBN: (纸本)0818656204

the Algorithm To architecture Mapping Model (ATAMM) is a scheduling strategy for predictable performance in real-time multiprocessor dataflow architectures. the architecture under consideration consists of either heterogeneous or homogeneous processors and implements dataflow models of real-time applications with a cyclo-static assignment scheme. Terminology is developed for graph partitioning, heterogeneous computing, and assignment classifications. A design methodology is described for partitioning dataflow graphs into blocks of nodes (operations) for the purpose of cyclo-static node-to-processor assignment while satisfying a design objective. A theorem is developed and proved to provide cyclo-static assignment of node blocks and illustrated by simulation results.< >

关键词： computer architecture Partitioning algorithms Predictive models Very high speed integrated circuits Steady-state Data engineering NASA Scheduling algorithm Processor scheduling Terminology

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