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Processor mapping techniques toward efficient data redistribution

Processor mapping techniques toward efficient data redistrib...

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International symposium on Parallel Processing

作者： E.T. Kalns L.M. Ni Department of Computer Science Michigan State University East Lansing MI USA

Run-time data redistribution can affect algorithm performance in distributed-memory machines. Redistribution of data can be performed between algorithm phases when a different data decomposition is expected to deliver increased performance for a subsequent phase of computation. Additionally, data redistribution can occur at subprogram boundaries. Redistribution, however, represents increased program overhead as algorithm computation is necessarily discontinued while data are exchanged among processor memories. In this paper, we present a technique for data-processor mapping, applicable to data redistribution, that minimizes the total amount of data that must be communicated among processors. the mapping technique is architecture-independent and represents our initial work toward achieving efficient redistribution in distributed-memory machines.< >

关键词： Runtime Distributed computing computer science System performance US Department of Energy high level languages Memory Costs

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A 48,000 pixel, 590,000 transistor silicon retina in current-mode subthreshold CMOS

A 48,000 pixel, 590,000 transistor silicon retina in current...

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Midwest symposium on Circuits and Systems (MWSCAS)

作者： A.G. Andreou K.A. Boahen Electrical and Computer Engineering Johns Hopkins University Baltimore MD USA CNS Program Caltech Pasadena CA USA

A second generation, contrast sensitive silicon retina is reported in this paper. the architecture and organization is inspired by the outer plexiform processing in the vertebrate retina. Current-mode subthreshold MOS design techniques are employed to obtain high performance and energetic efficiency. the system has been fabricated with 230/spl times/210 pixels on a 1/spl times/1 cm die in a 1.2 /spl mu/m n-well double metal, double poly, digital oriented CMOS technology. the chip incorporates 590,000 transistors, 48,000 pixels, operating in subthreshold/transition region with power dissipation of 50 mW when powered from a 5 V power supply. the pixel has a frequency response of 100 kHz.

关键词： Silicon Retina Physics computing MOSFETs Voltage CMOS technology throughput Very large scale integration computer networks computer architecture

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performance evaluation of parallel fast Walsh transform algorithms on a shared-memory multiprocessor computer

Performance evaluation of parallel fast Walsh transform algo...

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Southeastern symposium on System theory

作者： E.T. Ososanya Jung-Chi Chen Reyes Poo Department of Electrical Engineering Tennessee Technological University Cookeville TN USA Department of Electrical Engineering Michigan Technological University Houghton MI USA

the Walsh transforms have been used in various digital signal processing applications, such as high definition television (HDTV), processing ultrasonic or X-ray images of the heart in medicine, target tracking and object identification in military applications, and many more image processing applications. As the area of computer applications has broadened, the quantity of data to be transformed has greatly increased. One way of achieving fast transform is to parallelize the transform algorithms used in these applications. the author present the parallelization of three fast Walsh transform algorithms on the Alliant FX/2800 Supercomputer. they examine different parallelization techniques to optimize the computational time, and show how the Alliant architecture may be efficiently used for parallel computation.< >

关键词： Application software Signal processing algorithms HDTV Concurrent computing Digital signal processing TV X-ray imaging Heart Biomedical imaging Target tracking

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An environment for importance sampling based on stochastic activity networks

An environment for importance sampling based on stochastic a...

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Reliable Distributed Systems

作者： W.D. Obal W.H. Sanders Department of Electrical and Computer Engineering University of Arizona Tucson Tucson AZ USA Center for Reliable and High-Performance Computing Coordinated Science Laboratory University of Illinois Urbana-Champaign Urbana IL USA

Model-based evaluation of reliable distributed and parallel systems is difficult due to the complexity of these systems and the nature of the dependability measures of interest. the complexity creates problems for analytical model solution techniques, and the fact that reliability and availability measures are based on rare events makes traditional simulation methods inefficient. Importance sampling is a well-known technique for improving the efficiency of rare event simulations. However, finding an importance sampling strategy that works well in general is a difficult problem. the best strategy for importance sampling depends on the characteristics of the system and the dependability measure of interest. this fact motivated the development of an environment for importance sampling that would support the wide variety of model characteristics and interesting measures. the environment is based on stochastic activity networks, and importance sampling strategies are specified using the new concept of the importance sampling governor. the governor supports dynamic importance sampling strategies by allowing the stochastic elements of the model to be redefined based on the evolution of the simulation. the utility of the new environment is demonstrated by evaluating the unreliability of a highly dependable fault-tolerant unit used in the well-known MARS architecture. the model is non-Markovian, with Weibull distributed failure times and uniformly distributed repair times.< >

关键词： Monte Carlo methods Stochastic processes Analytical models Discrete event simulation Availability Sampling methods Stochastic systems computer network reliability computer networks Concurrent computing

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Network interface for message-passing parallel computation on a workstation cluster

Network interface for message-passing parallel computation o...

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Hot Interconnects

作者： J.C. Hoe Laboratory for Computer Science Massachusetts Institute of Technology Cambridge MA USA

As commercial microprocessors become increasingly popu- lar in current MPP architectures, high-performance com mercial workstations have also received increased attention as cost-effective building@blo&s for large parallel-processing systems. the Fast User-level Network (FUNet) project (111 is an attempt at constructing an inexpensive workstation based parallel system capable of supporting efficient ex ecution of message-passing parallel programs. Based on MIT's Arctic 15) network technology, FUNet connects stock configured commodity workstations with a high-bandwidth packet-switched routing network. the Past User-level Net work Interface (FUNi) is the custom hardware network interface device that provides access to FUNet for both message passing and remote direct-memory-access (DMA) block transfers between parallel peer processes on FUNet connected workstations. the FUNi hardware mechanisms allow direct low-overhead user-level accesses to FUNet while maintaining secure and transparent sharing of FUNet among multiple parallel applications. FUNi can be realized as SBus peripheral cards to allow compatibility with a variety of workstation platforms. the relaxed clock speed (25MHz max.) of SBus allows FUNi to be inexpensively imple mented using FPGA parts that are synthesized from de sips captured in Verilog Hardware Description Language [15]. SBus's Direct Virtual Memory Access (DVMA)[8J also assists FUNi in overcoming the performance limitations im posed by existing workstation designs. Simulation results have shown that FUNet with FUNi, when coupled with latency-hiding software techniques, is effective in supporting fine-gra@ined parallel processing on a workstation cluster.

关键词： Network interfaces computer interfaces computer networks Concurrent computing Workstations Hardware Costs Delay computer architecture Routing

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Proceedings of the 20th Annual International symposium on computer architecture

Proceedings of the 20th Annual International Symposium on Co...

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Proceedings of the 20th Annual International symposium on computer architecture

ISBN: (纸本)0818638109

this conference proceedings contain 32 papers. the main topics are architectural characteristics of scientific applications, TLBs and memory management, input/output systems, fault-tolerant computer architecture, multiprocessor caches, high-performance computing from the application perspective, multithreading support, shared memory systems, cache designs,and multiprocessor memory systems and interconnections.

关键词： computer architecture

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GaAs opportunities in high performance computing and communications

GaAs opportunities in high performance computing and communi...

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Proceedings of the 15th Annual IEEE GaAs IC symposium

作者： Toole, John C. Brown, Richard B. Advanced Research Projects Agency Arlington United States

ISBN: (纸本)0780313933

high performance computing and networking are becoming the backbone of the scientific and information infrastructure, incorporating emerging technologies into productive applications at an accelerating pace. these technologies are important both for our national security and as the basis of our future economic competitiveness. the Federal high performance computing and Communications Program provides an innovative and coordinated research agenda for the US in these areas. the question of greatest interest to the III/V community is, 'What role will emerge for compound semiconductors as computing reinvents itself?' this paper presents some insights, and a sample of the GaAs-related research funded by the Advanced Research Projects Agency. Results of these efforts will significantly contribute to the future role these semiconductors will play in mainstream computing.

关键词： Semiconducting gallium arsenide

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Heterogeneous by design: An environment for exploiting heterogeneity 7

Heterogeneous by design: An environment for exploiting heter...

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1993 Workshop on Heterogeneous Processing, VVHP 1993, Held in conjunction with the 7th International Parallel Processing symposium

作者： LaRowe, Richard P. Probert, thomas H. Center for High Performance Computing Worcester Polytechnic Institute United States

ISBN: (纸本)0818635312

Heterogeneity in computing environments is becoming increasingly common. Some consider this a problem, while others (including ourselves) prefer to think of it as a benefit. By exploiting the different features and capabilities of computer nodes in a heterogeneous computing network, higher levels of performance can be attained than is possible using any single type of computer found in the network. In this paper, we present the preliminary design of a heterogeneous computing environment being developed at CHPC. the environment includes a high-speed interconnection architecture capable of supporting shared memory, as well as a new programming environment for developing heterogeneous applications that exploit the available hardware. © 1993 IEEE.

关键词： computer programming

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GaAs opportunities in high performance computing and communications

GaAs opportunities in high performance computing and communi...

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Annual IEEE symposium on Gallium Arsenide Integrated Circuit (GaAs IC)

作者： J. Toole R. Brown Computing Systems Technology of fice Advanced Research Projects Agency Arlington VA USA Electrical Engineering and Computer Science Department University of Michigan Ann Arbor MI USA

high performance computing and networking are becoming the backbone of the scientific and information infrastructure, incorporating emerging technologies into productive applications at an accelerating pace. these technologies are important both for the national security and as the basis of the future economic competitiveness. the Federal high performance computing and Communications Program provides an innovative and coordinated research agenda for the US in these areas. the question of greatest interest to the III/V community is, "What role will emerge for compound semiconductors as computing reinvents itself?". the authors present some insights, and a sample of the GaAs-related research funded by the Advanced Research Projects Agency. Results of these efforts will significantly contribute to the future role these semiconductors will play in mainstream computing.< >

关键词： Gallium arsenide high performance computing Biological system modeling CMOS technology Application software Prototypes high temperature superconductors Packaging Speech Humans

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EXTENDING thE performance ENVELOPE OF 0.5-MU-M IMPLANTED SAG-MESFETS FOR SUPERcomputer APPLICATIONS

EXTENDING THE PERFORMANCE ENVELOPE OF 0.5-MU-M IMPLANTED SAG...

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15th Annual IEEE Gallium Arsenide Integrated Circuit (GaAS IC) symposium

作者： WILSON, MR CHASSON, DE KRONGARD, BS ROSENBERRY, RW SHAH, NA WELCH, BM CRAY COMP CORP INC GAAS OPERATCOLORADO SPRINGSCO 80906

ISBN: (纸本)0780313933

the implementation, optimization, and evaluation of an ion implanted, 0.5μm refractory self-aligned gate GaAs MESFET process for DCFL digital IC's for supercomputer applications is described. the MESFET performance has been optimized for minimal short channel effects, ultra high performance, minimal backgating, and improved manufacturability. this device process has been coupled together with a three or four level metal interconnect process for producing 1GHz clock rate LSI to VLSI digital computer IC's. the interconnect process makes use of up to four levels of CVD Tungsten via fill for planarity throughout the interconnect process. this process yields typical propagation delays of 25pS for a 2/4μm inverter with unity fan-out. Four input NOR gates with a fan-out of 4 have a typical delay of 65pS. Moreover, a 4 input NOR buffer driving a fan-out of 7 through 500μm of minimum geometry metal has a delay of 63pS. this delay increases to 93pS when the metal length is increased to 1500μm. this process is being used to produce 5 to 10K gate digital circuits for the 1GHz clock rate Cray-4 supercomputer. this work has resulted in a manufacturing process which produces devices and circuits with world class performance.

关键词： MESFET devices

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