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Demo: A Multi-Perspective Video Streaming System with Privacy Preservation in Trauma Room

Demo: A Multi-Perspective Video Streaming System with Privac...

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IEEE/ACM symposium on Edge computing (SEC)

作者： Zhengyong Ren Yuxin Yang Kambiz Ghazinour Sara Bayramzadeh Qiang Guan Department of Computer Science Kent State University School of Science Health and Criminal Justice State University of New York at Canton College of Architecture and Environmental Design Kent State University

ISBN: (数字)9781665486118

ISBN: (纸本)9781665486125

More and more hospitals are now deploying mul-tiple cameras in trauma room for a multi-perspective remote observation. but video surveillance system can cause privacy breach by showing and storing sensitive information of patients and staff. We use OpenPose which is a state-of-the-art human body skeletons estimation framework to extract 18 human key skeleton points. For privacy preservation, we can apply the image obfuscation techniques to human heads, we also can use human skeleton to replace the human body in the truth background. we proposed a head detection method based on the 5 key points of each head output from OpenPose. We applied the st-gcn algorithm to recognize human actions, we propose a interactive algorithm for multiple cameras to recognize and trace the same person in different cameras, Based on multi-view action recognition for the same person, we can take action recognition accuracy to a high level. Our experiment results prove that our proposed technique has a high performance in privacy protection applications. Now we focus on the interactive algorithm for multiple cameras.

关键词： Head Image recognition Hospitals Estimation Streaming media Cameras Video surveillance

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Shortening Design Time through Multiplatform Simulations with a Portable OpenCL Golden-model: the LDPC Decoder Case

Shortening Design Time through Multiplatform Simulations wit...

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Annual IEEE symposium on Field-Programmable Custom computing Machines (FCCM)

作者： G. Falcao M. Owaida D. Novo M. Purnaprajna N. Bellas C.D. Antonopoulos G. Karakonstantis A. Burg P. Ienne Instituto de Telecomunicações Department of Electrical and Computer Engineering University of Coimbra Portugal Department of Computer and Communications Engineering University of Thessaly Greece École Polytechnique Fédérale de Lausanne Switzerland

Hardware designers and engineers typically need to explore a multi-parametric design space in order to find the best configuration for their designs using simulations that can take weeks to months to complete. For example, designers of special purpose chips need to explore parameters such as the optimal bit width and data representation. this is the case for the development of complex algorithms such as Low-Density Parity-Check (LDPC) decoders used in modern communication systems. Currently, high-performance computing offers a wide set of acceleration options, that range from multicore CPUs to graphics processing units (GPUs) and FPGAs. Depending on the simulation requirements, the ideal architecture to use can vary. In this paper we propose a new design flow based on Open CL, a unified multiplatform programming model, which accelerates LDPC decoding simulations, thereby significantly reducing architectural exploration and design time. Open CL-based parallel kernels are used without modifications or code tuning on multicore CPUs, GPUs and FPGAs. We use SOpen CL (Silicon to Open CL), a tool that automatically converts Open CL kernels to RTL for mapping the simulations into FPGAs. To the best of our knowledge, this is the first time that a single, unmodified Open CL code is used to target those three different platforms. We show that, depending on the design parameters to be explored in the simulation, on the dimension and phase of the design, the GPU or the FPGA may suit different purposes more conveniently, providing different acceleration factors. For example, although simulations can typically execute more than 3× faster on FPGAs than on GPUs, the overhead of circuit synthesis often outweighs the benefits of FPGA-accelerated execution.

关键词： Kernel Parity check codes Field programmable gate arrays Computational modeling Decoding Hardware Algorithm design and analysis

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Vacuum packing: extracting hardware-detected program phases for post-link optimization

Vacuum packing: extracting hardware-detected program phases ...

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IEEE/ACM International symposium on Microarchitecture (MICRO)

作者： R.D. Barnes E.M. Nystrom M.C. Merten W.W. Hwu Center for Reliable and High-Performance Computing Department of Electical and Computer Engineering University of Illinois Urbana-Champaign USA

this paper presents Vacuum Packing, a new approach to profile-based program optimization. Instead of using traditional aggregate or summarized execution profile weights, this approach uses a transparent hardware profiler to automatically detect execution phases and record branch profile information for each new phase. the code extraction algorithm then produces code packages that are specially formed for their corresponding phases. the algorithm compensates for the incomplete and often incoherent branch profile information that arises due to the nature of hardware profilers. the technique avoids unnecessary code replication by focusing on hot code, making efficient connections between the original code and the new code, linking code packages at select points to facilitate phase transitions, and providing a platform for efficient optimization. We demonstrate that using a concise set of profile information from a hardware profiler, we can generate code packages, specialized for each phase of execution, that capture more than 80% of the average total program execution. We further show that the approach is very effective in extracting code regions that capture the phasing behavior of programs, that the code size increase is moderate, and that the code regions benefit from sample optimizations.

关键词： Data mining Packaging Reliability engineering Aggregates Phase detection Joining processes computer architecture Java Emulation Libraries

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A low-power carry skip adder with fast saturation

A low-power carry skip adder with fast saturation

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International Conference on Application Specific Systems (ASAP), architectures and Processors

作者： M.J. Schulte K. Chirca J. Glossner H. Wang S. Mamidi P. Balzola S. Vassiliadis Sandbridge Technologies Inc. White Plains NY USA Dept. of ECE University of Wisconsin Madison WI USA Delft University of Technology Computer Engineering Laboratory The Netherlands

We present the design of a carry skip adder that achieves low power dissipation and high-performance operation. the carry skip adder's delay and power dissipation are reduced by dividing the adder into variable-sized blocks that balance the delay of inputs to the carry chain. this grouping reduces active power by minimizing extraneous glitches and transitions. Each block also uses highly optimized complementing carry look-ahead logic to reduce delay. Compared to previous designs, the adder architecture decreases power consumption by reducing the number of transistors, logic levels, and glitches. A 32-bit carry skip adder design that uses our approach has been implemented in 130 nm CMOS technology. At 1.2 V and 25 C, the 32-bit adder has a critical path delay of 921 ps and average power dissipation normalized to 600 MHz operation of 0.786 mW. We also present a technique to quickly perform saturating addition, which is useful in a variety of digital signal processing and multimedia applications. Our technique for fast saturation is based on techniques for carry select addition and works particularly well when the input and output operands can have different formats. A 40-bit carry skip adder that uses our technique for fast saturation has critical path delays of 1149 ps in 130 nm technology at 1.2 V and 25 C and 560 ps in 90nm technology at 1.0 V and 25 C. the 40-bit adder's average power dissipation normalized to 600 MHz operation is 0.928 mW in 130 nm technology and 0.335 mW in 90 nm technology.

关键词： CMOS logic circuits Power dissipation Added delay Energy consumption CMOS technology Adders Power engineering computing Design engineering Power engineering and energy Laboratories

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Managing performance and efficiency of a processor

Managing performance and efficiency of a processor

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Southeastern symposium on System theory

作者： Aditi Shinde Vishwani D. Agrawal Department of Electrical and Computer Engineering Auburn University Auburn AL USA

ISBN: (纸本)9781479900374

the performance of a processor generally means how fast it can execute a task. For a given architecture we can measure the size of a task as the number of clock cycles it will take to execute. then clock frequency (f) will determine the execution time. Normally, the frequency can be raised if the supply voltage V dd is increased. this, however, increases the power and energy used. We introduce a new measure, cycle efficiency (η) as cycles per joule that gives the rate of computational work per unit energy. Similar to f, η is also a function of V dd . We provide a method of characterizing a processor in terms of its f and η versus V dd characteristics. Intel Pentium M processor with an assumed 90nm CMOS PTM (predictive technology model) is used as an example. For a demonstration of performance and energy management, we consider a program that executes in 1.8 billion clock cycles. At the nominal operating supply of 1.2V we have f = 1.8GHz and η = 15 megacycles/joule. the program executes in 1 second and uses 120 joules. For operation at 0.6V, f = 277MHz and η = 70 megacycles/joule, resulting in a run time of 6.5 seconds and consumption of 25 joules. We also find a subthreshold voltage extreme of 200mV, f = 54.5MHz and η = 660 megacycles/joule. Now the program will take 33 seconds but will consume only 2.27 joules. thus, using cycle efficiency and clock frequency one can manage the time and energy performances according to the requirements of a computing task.

关键词： Clocks CMOS integrated circuits Delays Time-frequency analysis Semiconductor device modeling Integrated circuit modeling Educational institutions

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Workflow Design Analysis for high Resolution Satellite Image Analysis

Workflow Design Analysis for High Resolution Satellite Image...

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IEEE International Conference on e-Science and Grid computing

作者： Ioannis Paraskevakos Matteo Turilli Bento Collares Gonçalves Heather J. Lynch Shantenu Jha Department of Electrical and Computer Engineering Rutgers University Piscataway New Jersey Rutgers University Piscataway NJ USA Stony Brook University Stony Brook NY USA Department of Ecology and Evolution Brookhaven National Laboratory Stony Brook NY USA

ISBN: (数字)9781728124513

ISBN: (纸本)9781728124520

Ecological sciences are using imagery from a variety of sources to monitor and survey populations and ecosystems. Very high Resolution (VHR) satellite imagery provide an effective dataset for large scale surveys. Convolutional Neural Networks have successfully been employed to analyze such imagery and detect large animals. As the datasets increase in volume, O(TB), and number of images, O(1k), utilizing high performance computing (HPC) resources becomes necessary. In this paper, we investigate a task-parallel data-driven workflows design to support imagery analysis pipelines with heterogeneous tasks on HPC. We analyze the capabilities of each design when processing a dataset of 3,000 VHR satellite images for a total of 4~TB. We experimentally model the execution time of the tasks of the image processing pipeline. We perform experiments to characterize the resource utilization, total time to completion, and overheads of each design. Based on the model, overhead and utilization analysis, we show which design approach to is best suited in scientific pipelines with similar characteristics.

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Energy efficient distributed algorithms for sensor target coverage based on properties of an optimal schedule 08

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Proceedings of the 15th international conference on high performance computing

作者： Akshaye Dhawan Sushil K. Prasad Georgia State University Department of Computer Science Atlanta GA

ISBN: (纸本)9783540898931

A major challenge in Wireless Sensor Networks is that ofmaximizing the lifetime while maintaining coverage of a set of targets,a known NP-complete problem. In this paper, we present theoretically-grounded, energy-efficient, distributed algorithms that enable sensors toschedule themselves into sleep-sense cycles. We had earlier introduceda lifetime dependency (LD) graph model that captures the interdependenciesbetween these cover sets by modeling each cover as a node andhaving the edges represent shared sensors. the key motivation behindour approach in this paper has been to start with the question of whatan optimal schedule would do with the lifetime dependency graph. Weprove some basic properties of the optimal schedule that relate to theLD graph. Based on these properties, we have designed algorithms whichchoose the covers that exhibit these optimal schedule like properties. Wepresent three new sophisticated algorithms to prioritize covers in thedependency graph and simulate their performance against state-of-art algorithms. the net effect of the 1-hop version of these three algorithmsis a lifetime improvement of more than 25-30% over the competing algorithmsof other groups, and 10-15% over our own; the 2-hop versionshave additional improvements, 30-35% and 20-25%, respectively.

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Accelerating mutual information-based 3D medical image registration with An FPGA computing platform (abstract only) 05

Accelerating mutual information-based 3D medical image regis...

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Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays

作者： Jianchun Li Christos Papachristou Raj Shekhar Case Western Reserve University Cleveland OH University of Maryland Baltimore MD

ISBN: (纸本)9781595930293

Mutual information-based 3D image Registration algorithm is shown to be an accurate, robust and more general registration method for medical image processing. However, its potential application in clinic is jeopardized by its high computational costs. Like many other 3D imaging algorithms, 3D registration needs to process vast amount of image data. the intrinsic computing characteristics of the mutual information-based registration algorithm make it even more difficult to manage and cache the input data. In this paper, we introduce our FPGA-based computing platform and detail its application in accelerating the mutual information-based 3D image registration. this platform is designed to accelerate a series of 3D medical imaging algorithms dominated by local operations. It is a System-on-Chip (SoC) architecture with an intelligent data caching system for efficient data fetching and buffering. A reconfigurable multi-pipeline execution unit in the platform is designed to perform high-speed parallel computation. this unit can be customized according to different algorithm requirements to achieve high performance. the simulation results for accelerating the mutual information based registration with our platform show that a speed-up of about 30 can be achieved when compared to a single-CPU computer. Moreover, the platform can be easily reconfigured to accelerate other 3D medical imaging algorithms.

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Leveraging Advanced Machine Learning Algorithms for Loan Repayment Prediction

Leveraging Advanced Machine Learning Algorithms for Loan Rep...

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International Conference on computing and Networking Technology (ICCNT)

作者： Akshat Ranjan Mahendra Kumar Gourisaria Jay Prakash Singh Amiya Ranjan Panda Soumya Ranjan Mishra Varutri Parihar School of Computer Engineering KIIT Deemed to be University Bhubaneshwar Odisha India Dept of Computer Science & Engineering Manipal University Jaipur Jaipur Rajasthan India

ISBN: (数字)9798350370249

ISBN: (纸本)9798350370270

Accurately predicting loan repayment behavior is a critical challenge for financial institutions, which often face high default rates and financial instability due to inaccurate credit assessments. In order to address these problems, this study looks into the application of sophisticated machine learning methods such Random Forests, Decision Trees, Support Vector Machines, and Stacking Classifiers. the models, trained on diverse client variables, significantly outperform traditional credit scoring methods. the findings suggest that integrating these sophisticated models can enhance financial performance, reduce default risks, and enable more informed lending decisions. the study also examines potential avenues for future research, including the application of increasingly sophisticated machine learning techniques and the integration of new data sources to enhance models. this study advances the field of machine learning in finance by providing business and academics with insightful information that could result in stronger and more secure financial systems.

关键词： Support vector machines Machine learning algorithms Soft sensors Computational modeling Stacking Finance Data models Decision trees Random forests Faces

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Dynamic thermal-Aware Scheduling Using Physics-Informed POD-Galerkin thermal Simulation Model for Multi-Core Processors : Invited Paper

Dynamic Thermal-Aware Scheduling Using Physics-Informed POD-...

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International Green computing Conference

作者： Anthony Dowling Ming-Cheng Cheng Yu Liu Department of Electrical and Computer Engineering Clarkson University

ISBN: (数字)9798331507862

ISBN: (纸本)9798331507879

Handling heavy computing tasks in real-time systems requires substantial power, leading to significant heat generation. this can cause serious thermal problems like rising temperatures, high thermal gradients, and hot spots. these issues can reduce chip performance, accelerate device aging, and cause premature failure. thermal-Aware Scheduling (TAS) optimizes heat management to maintain a safe temperature. In this work, we evaluate RT-TAS, an advanced TAS algorithm using a steady-state thermal model, and compare it with our proposed dynamic physics-informed POD-based TAS algorithm. POD-TAS utilizes a reduced order thermal model with a dynamic predictive approach, allowing precise temperature control during task scheduling. this reduces peak temperatures and thermal variations. Our tests on a multi-core processor demonstrate that POD-TAS significantly improves thermal performance. It reduces the average spatial thermal variance by 6.18%, the variance of the maximum CPU temperature over time by 59.68%, and the variance of the average temperature by 13.05% due to its ability to maintain the chip temperature within a set threshold.

关键词： Heating systems Processor scheduling Multicore processing Heuristic algorithms Predictive models Dynamic scheduling Prediction algorithms thermal management Real-time systems Steady-state

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