检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

4,547 篇 会议
83 篇 期刊文献
15 册 图书

馆藏范围

4,645 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

2,559 篇 工学
- 2,365 篇 计算机科学与技术...
- 1,163 篇 软件工程
- 494 篇 电气工程
- 407 篇 信息与通信工程
- 212 篇 电子科学与技术（可...
- 212 篇 控制科学与工程
- 98 篇 网络空间安全
- 80 篇 动力工程及工程热...
- 80 篇 生物工程
- 68 篇 光学工程
- 65 篇 机械工程
- 56 篇 生物医学工程（可授...
- 36 篇 建筑学
- 30 篇 化学工程与技术
- 29 篇 环境科学与工程（可...
614 篇 理学
- 375 篇 数学
- 144 篇 物理学
- 93 篇 生物学
- 74 篇 系统科学
- 69 篇 统计学（可授理学、...
465 篇 管理学
- 346 篇 管理科学与工程(可...
- 134 篇 图书情报与档案管...
- 129 篇 工商管理
- 65 篇 公共管理
111 篇 法学
- 103 篇 社会学
104 篇 医学
- 73 篇 公共卫生与预防医...
- 31 篇 临床医学
- 29 篇 基础医学(可授医学...
65 篇 文学
- 65 篇 新闻传播学
39 篇 经济学
- 38 篇 应用经济学
17 篇 教育学
10 篇 农学
1 篇 艺术学

主题

1,194 篇 computer archite...
426 篇 hardware
344 篇 high performance...
295 篇 computational mo...
255 篇 concurrent compu...
236 篇 application soft...
214 篇 computer science
205 篇 parallel process...
179 篇 distributed comp...
178 篇 costs
171 篇 delay
170 篇 grid computing
168 篇 bandwidth
164 篇 field programmab...
154 篇 resource managem...
153 篇 cloud computing
144 篇 computer network...
142 篇 throughput
129 篇 processor schedu...
125 篇 scalability

机构

22 篇 institute of com...
16 篇 graphic era deem...
14 篇 chitkara univers...
13 篇 university of ch...
11 篇 college of compu...
10 篇 school of comput...
10 篇 computer science...
9 篇 georgia inst tec...
9 篇 computer systems...
9 篇 intel corp santa...
8 篇 department of co...
8 篇 department of el...
8 篇 ibm thomas j. wa...
8 篇 barcelona superc...
8 篇 mathematics and ...
8 篇 quantum universi...
8 篇 中国电子科技集团...
8 篇 mathematics and ...
8 篇 key laboratory o...
8 篇 univ fed rio gra...

作者

14 篇 navaux philippe ...
10 篇 satvik vats
9 篇 vats satvik
9 篇 i. foster
9 篇 d.k. panda
8 篇 dhabaleswar k. p...
8 篇 dongarra jack
8 篇 loh gabriel h.
8 篇 guedes dorgival
8 篇 viktor k. prasan...
8 篇 prasanna viktor ...
8 篇 mutlu onur
7 篇 shiva mehta
7 篇 borin edson
7 篇 chong frederic t...
7 篇 torrellas josep
7 篇 kim nam sung
7 篇 li chao
7 篇 zhou huiyang
7 篇 ferreira renato

语言

4,523 篇 英文
100 篇 其他
20 篇 中文
3 篇 葡萄牙文
1 篇 法文

检索条件"任意字段=15th Symposium on Computer Architecture and High Performance Computing"

共 4645 条记录，以下是441-450 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Distance Aware Compression for Low Latency high Bandwidth Interconnection Network 15

Distance Aware Compression for Low Latency High Bandwidth In...

引用

15th IEEE International symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2022

作者： Yuqing, Zhou Niwa, Naoya Amano, Hideharu Keio University Dept. of Information and Computer Science 3-14-1 Hiyoshi Yokohama223-8522 Japan

ISBN: (纸本)9781665464994

NoC(Network-on-Chip)s is an essential component of recent multi-core systems. When the number of wires available on a chip is limited, it is sometimes congested and increased la-tency can degrade the parallel application performance. the selective data compression has been proposed to mitigate such network congestion by compressing and decompressing packets based on the packet length and traffic situation. However, since the algorithm does not care the location of nodes, the compression and decompression are performed even when the packet is transferred between neighboring nodes. this paper proposes a distance aware (DA) compression mechanism to select whether the packet should be compressed by the distance to the destination. the packets to the nodes whose distance is larger than threshold level are compressed with a run-length loss-less compression at the sender's network interface and de-compressed at the receiver's network interface. Cycle level network simulation results show that the selective compression method achieves up to 45% bandwidth improve-ment with 1.26 times increase of the latency. © 2022 IEEE.

关键词： Data compression

来源：评论

学校读者我要写书评

暂无评论

Comparative Study of Low Bit-width DNN Accelerators: Opportunities and Challenges 66

Comparative Study of Low Bit-width DNN Accelerators: Opportu...

引用

2023 IEEE 66th International Midwest symposium on Circuits and Systems, MWSCAS 2023

作者： Vungarala, Deepak Morsali, Mehrdad Tabrizchi, Sepehr Roohi, Arman Angizi, Shaahin New Jersey Institute of Technology Department of Electrical and Computer Engineering NewarkNJ United States School of Computing University of Nebraska-Lincoln LincolnNE United States

ISBN: (纸本)9798350302103

Digital Processing-in-Memory (PIM) architectures have recently unleashed significant potential in Deep Neural Network (DNN) acceleration not only by addressing memory-wall bottlenecks but also by offering impressive performance improvement compared to the von-Neumann architecture. Different flavors of DNN ASIC accelerators have also been developed and fabricated, with remarkable performance and efficiency. this paper conducts a comparative study of PIM and Gemmini-generated accelerators for low-bit-width DNN inference and underscores their key architectural constraints, opportunities, and security challenges. To this end, we compare multiple low-power accelerators with our recently taped-out PIM macro to provide a guideline for the community. © 2023 IEEE.

关键词： accelerator ASIC processing-in-memory

来源：评论

学校读者我要写书评

暂无评论

Collaborative Cloud - Edge: A Declarative API orchestration model for the NextGen 5G Core 15

Collaborative Cloud - Edge: A Declarative API orchestration ...

引用

15th IEEE International Conference on Service-Oriented System Engineering (SOSE)

作者： Ungureanu, Oana-Mihaela Vladeanu, Calin Kooij, Robert Univ Politehn Bucuresti Bucharest Romania Delft Univ Technol Delft Netherlands

ISBN: (纸本)9781665434775

As the edge computing era matures, it encompasses a broader range of applications that will be able to opportunistically use both the edge and the cloud mainly determined by the location constraints or the mission-critical reasons. Moreover, the convergence of verticals with the next generation mobile network will lead to an imminent edge-cloud collaboration that needs to be carefully addressed by Mobile Network Operators (MNOs). this paper proposes a novel approach to orchestrate the next-generation 5G core running as Cloud-Native Network Functions (CNFs) closer to the edge network while offloading the computation power required to ensure on-demand processing to a central cloud infrastructure. In this manner, full service isolation and network segmentation can be achieved independently from the geographical region with a high degree of scalability. Our main objective is to automate the CNFs provisioning in a declarative API-style in order to easily manage the deployment of applications and services across multiple clusters. therefore, in our setup we considered crucial to assess the benefits of running the 5G Service-Based architecture (SBA) in the cloud with multi-tenancy capabilities and evaluate the performance in terms of latency, while keeping the network control at the edge.

关键词： edge computing CNF SBA multi-tenancy network slicing

来源：评论

学校读者我要写书评

暂无评论

A reinforcement learning-based network load balancing mechanism 5

A reinforcement learning-based network load balancing mechan...

引用

5th International Conference on computer Information Science and Artificial Intelligence, CISAI 2022

作者： Wang, Jiawei School of Computer Science University of Birmingham BirminghamB15 2TT United Kingdom

ISBN: (纸本)9781510662520

With the exponential growth of cloud computing demands, load balancing gradually becomes the infrastructure of high concurrency applications. the increased demand makes load balancing the cornerstone of large-scale systems’ stability and efficiency. Due to the diversity of modern client-server architecture, irregular fluctuations in cluster system resource allocation gradually become significant. the existing load balancing algorithms are rule-based, leading to a gap between operational and practical scenarios. the phenomenon causes noticeable tribulations in cluster resource utilization optimization. this research proposes a reinforcement learning-based load balancing model optimization approach. this paper modelled the load balancing problem as a Markov Decision Process and implemented the conjecture with the Q-learning algorithm. this paper performs a load balancer that can efficiently utilize the resources in the cluster system by observing the association between the packet body and node resource utilization rate in the cluster system. the experiment demonstrated that the author’s mechanism substantially improves the average cluster system resource utilization efficiency and reduces the Round-Trip Time performance in real network environments. © 2023 SPIE.

关键词： Reinforcement learning

来源：评论

学校读者我要写书评

暂无评论

Facial Emotion Recognition Using computer Vision Techniques

Facial Emotion Recognition Using Computer Vision Techniques

引用

International Conference on computing and Networking Technology (ICCNT)

作者： Pradeep Kumar Gupta Nayantara Varadharajan Keerthana Ajith Tripty Singh Payel Patra Dept. of Computer Science and Engineering Amrita School of Computing Amrita Vishwa Vidyapeetham Bengaluru India DISIM Department University of L’Aquila L’Aquila Italy

ISBN: (数字)9798350370249

ISBN: (纸本)9798350370270

the ability to recognize facial emotions through computer vision has become a challenging yet crucial task in the field of image classification. this paper introduces a method for detecting facial emotions, focusing on the classification of seven distinct emotions which are neutral, sadness, anger, disgust, fear, happiness, and surprise. Using recent advancements in computer vision and machine learning, the proposed approach employs three distinct models: Convolutional Neural Network (CNN), ResNet50, and InceptionV3. Facial expression recognition poses unique challenges in image classification, and the adoption of deep learning has gained prominence for its effectiveness in solving this complex problem. the key challenge addressed in this research is the design of architectures that balance both simplicity and effectiveness. A simple architecture ensures quick training and easy implementation, while an effective one yields high accuracy on the test data. this research contributes to the ongoing efforts in advancing computer vision applications related to human emotions and highlights the potential for practical implementation in areas like affective computing and human computer interaction. the findings offer valuable insights into designing effective and efficient deep-learning architectures for facial emotion recognition with a multiclass approach.

关键词： Emotion recognition computer vision Analytical models Accuracy Image recognition Face recognition Computational modeling computer architecture Convolutional neural networks Residual neural networks

来源：评论

学校读者我要写书评

暂无评论

12-stage FFT Implementation using cordic-based pipelined SDF architecture

12-stage FFT Implementation using cordic-based pipelined SDF...

引用

International Conference on computing and Networking Technology (ICCNT)

作者： Priya Mule Sudhakar Mande Department of Electronics and Telecommunication Ramrao Adik Institute of Technology Navi Mumbai India Department of Electronics and Telecommunication Don Bosco Institute of Technology Mumbai India

ISBN: (数字)9798350370249

ISBN: (纸本)9798350370270

In this present work, a high-speed cordic-based realtime Single-delay feedback FFT processor is realized on FPGA. the Cordic algorithm will eliminate the hardware complexity of the complex multipliers in the butterflies. the logic behind this implementation is to replace the twiddle factors in conventional SDF processors with recursive Cordic rotations thereby eliminating the usage of ROM. Cordic is utilized as it provides a simpler way of computing complex multiplications and it is considered the best alternative. the present cordic sdf architecture is proposed to implement and scale to the variable length of FFT size $N=2^{m}$. where $\mathbf{N}$ belongs to FFT size and $\mathbf{m}$ indicates no of stages. Memory utilization in cordic pipelined SDF fft is 4% as compared to conventional SDF fft which takes 21%. the maximum operating frequency in the case of Cordic-based SDF FFT is $\mathbf{1 2 8. 4 M H Z}$ resulting in low latency and high throughput. the present architecture offers a variety of applications in signal and communication systems where high speed is employed for faster data transfer.

关键词： computer architecture throughput Data transfer Hardware Logic Iterative methods Low latency communication Read only memory Field programmable gate arrays Pipeline processing

来源：评论

学校读者我要写书评

暂无评论

Area-Delay-Power Efficient VLSI architecture of OTFS Transceiver in Multipath Fading Channel

Area-Delay-Power Efficient VLSI Architecture of OTFS Transce...

引用

International Conference on computing and Networking Technology (ICCNT)

作者： Ashish Ranjan Shadangi Suvra Sekhar Das Indrajit Chakrabarti B V Sudhakar Reddy GSSST Indian Institute of Technology Kharagpur India E & ECE Indian Institute of Technology Kharagpur India

ISBN: (数字)9798350370249

ISBN: (纸本)9798350370270

Orthogonal Time-Frequency Space (OTFS) modulation, an innovative communication protocol designed for high-speed vehicle communication, has demonstrated its stability and efficacy. this technique works with a new delay-Doppler domain waveform, offering significant performance advantages over traditional approaches such as Orthogonal Frequency Division Multiplexing (OFDM), especially in swiftly changing wireless environments. the initial phase of our research outlines the input-output dynamics of OTFS signals inside the domain of delay-time. Additionally, using the Lower-Upper (LU) decomposition technique, we present a novel and resource-efficient Very-large-scale Integration (VLSI) architecture of the OTFS transceiver. A comparative analysis with recent state-of-the-art is done, which demonstrates our optimized transmitter’s superior performance, boasting a $1.977 \%$ faster with ${6 7 . 4 7 2 \%}$ fewer Lookup Tables (LUTs) and 66.580% less Flip-Flops (FFs), indicating optimized latency and resource utilization and ${9 . 3 9 4 5 \%}$ less power. Moreover, we present timing analysis, resource utilization, and functionality testing for our suggested optimized receiver architecture, which shows that optimized architecture uses $39.193 \%$ less LUTs and 37.295% Digital-Signal-Processing blocks (DSPs) and $35.087 \%$ less power compared to existing recent work. We checked the sanity of our architecture output with MATLAB output.

关键词： Wireless communication Transmitters OFDM computer architecture Receivers Very large scale integration Transceivers Table lookup Resource management Testing

来源：评论

学校读者我要写书评

暂无评论

Reconfigurable Streaming architecture for AI-Based Fault Prediction of Power Equipment: Initial Analysis and Discussion

Reconfigurable Streaming Architecture for AI-Based Fault Pre...

引用

IEEE Asia Power and Energy Engineering Conference (APEEC)

作者： Tian Lan Qinwei He Guoliang Zhang Peng Zhang Yuanliang Lan Peng Li Global Energy Interconnection Research Institute Europe GmbH Berlin Germany China Electric Power Research Institute Co. Ltd Beijing China State Grid Jibei Electric Power Co. Ltd EHV Power Transmission Company Beijing China

ISBN: (数字)9798331517540

ISBN: (纸本)9798331517557

high voltage power equipment, such as transformers, presents highly complex structures, operational conditions, and mechanisms. Effective condition monitoring and fault prediction for these systems require the integration of vast multimodal datasets, including electrical, mechanical, thermal, and environmental signals. this complexity places strong demands on lightweight computation and high-performance edge computing devices capable of real-time processing. In this study, current popular computing architectures, including CPU, Nvidia GPGPU and Google TPU, are firstly reviewed. the strength and the drawbacks of these architectures are discussed considering the requirements from the application of AI-based fault detection in power equipment. In the end, reconfigurable streaming architecture is highlighted and suggested to overcome the limitations of current popular computing architectures.

关键词： Energy consumption Fault detection Power system dynamics computer architecture high-voltage techniques Electrical fault detection Real-time systems Hardware Power transformers Streams

来源：评论

学校读者我要写书评

暂无评论

Rearchitecting Linux Storage Stack for μs Latency and high throughput 15

Rearchitecting Linux Storage Stack for μs Latency and High ...

引用

USENIX Annual Technical Conference / 15th USENIX symposium on Operating Systems Design and Implementation (OSDI)

作者： Hwang, Jaehyun Vuppalapati, Midhul Peter, Simon Agarwal, Rachit Cornell Univ Ithaca NY 14853 USA UT Austin Austin TX USA

ISBN: (纸本)9781939133229

this paper demonstrates that it is possible to achieve mu s-scale latency using Linux kernel storage stack, even when tens of latency-sensitive applications compete for host resources with throughput-bound applications that perform read/write operations at throughput close to hardware capacity. Furthermore, such performance can be achieved without any modification in applications, network hardware, kernel CPU schedulers and/or kernel network stack. We demonstrate the above using design, implementation and evaluation of blk-switch, a new Linux kernel storage stack architecture. the key insight in blk-switch is that Linux's multi-queue storage design, along with multi-queue network and storage hardware, makes the storage stack conceptually similar to a network switch. blk-switch uses this insight to adapt techniques from the computer networking literature (e.g., multiple egress queues, prioritized processing of individual requests, load balancing, and switch scheduling) to the Linux kernel storage stack. blk-switch evaluation over a variety of scenarios shows that it consistently achieves mu s-scale average and tail latency (at both 99th and 99.9th percentiles), while allowing applications to near-perfectly utilize the hardware capacity.

关键词： Queueing theory

来源：评论

学校读者我要写书评

暂无评论

A Shared Memory SMC Sampler for Decision Trees

A Shared Memory SMC Sampler for Decision Trees

引用

International symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Efthyvoulos Drousiotis Alessandro Varsi Paul G. Spirakis Simon Maskell Department of Electrical Engineering and Electronics University of Liverpool Liverpool UK Department of Computer Science University of Liverpool Liverpool UK

Modern classification problems tackled by using Decision Tree (DT) models often require demanding constraints in terms of accuracy and scalability. this is often hard to achieve due to the ever-increasing volume of data used for training and testing. Bayesian approaches to DTs using Markov Chain Monte Carlo (MCMC) methods have demonstrated great accuracy in a wide range of applications. However, the inherently sequential nature of MCMC makes it unsuitable to meet both accuracy and scaling constraints. One could run multiple MCMC chains in an embarrassingly parallel fashion. Despite the improved run-time, this approach sacrifices accuracy in exchange for strong scaling. Sequential Monte Carlo (SMC) samplers are another class of Bayesian inference methods that also have the appealing property of being parallelizable without trading off accuracy. Nevertheless, finding an effective parallelization for the SMC sampler is difficult, due to the challenges in parallelizing its bottleneck, redistribution, in such a way that the workload is equally divided across the processing elements, especially when dealing with variable-size models such as DTs. this study presents a parallel SMC sampler for DTs on Shared Memory (SM) architectures, with an $O(log_{2} N)$ parallel redistribution for variable-size samples. On an SM machine mounting 32 cores, the experimental results show that our proposed method scales up to a factor of 16 compared to its serial implementation, and provides comparable accuracy to MCMC, but 51 times faster.

关键词：

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共465页 << < 41 42 43 44 45 46 47 48 49 50 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：