the implementation, optimization, and evaluation of an ion implanted, 0.5μm refractory self-aligned gate GaAs MESFET process for DCFL digital IC's for supercomputer applications is described. the MESFET performan...
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ISBN:
(纸本)0780313933
the implementation, optimization, and evaluation of an ion implanted, 0.5μm refractory self-aligned gate GaAs MESFET process for DCFL digital IC's for supercomputer applications is described. the MESFET performance has been optimized for minimal short channel effects, ultra highperformance, minimal backgating, and improved manufacturability. this device process has been coupled together with a three or four level metal interconnect process for producing 1GHz clock rate LSI to VLSI digital computer IC's. the interconnect process makes use of up to four levels of CVD Tungsten via fill for planarity throughout the interconnect process. this process yields typical propagation delays of 25pS for a 2/4μm inverter with unity fan-out. Four input NOR gates with a fan-out of 4 have a typical delay of 65pS. Moreover, a 4 input NOR buffer driving a fan-out of 7 through 500μm of minimum geometry metal has a delay of 63pS. this delay increases to 93pS when the metal length is increased to 1500μm. this process is being used to produce 5 to 10K gate digital circuits for the 1GHz clock rate Cray-4 supercomputer. this work has resulted in a manufacturing process which produces devices and circuits with world class performance.
In this paper, we will describe applications of large scale computer modeling and simulation to a class of direct and inverse bioelectric volume-conductor problems which arise in electrocardiography and electroencepha...
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ISBN:
(纸本)0780313771
In this paper, we will describe applications of large scale computer modeling and simulation to a class of direct and inverse bioelectric volume-conductor problems which arise in electrocardiography and electroencephalography. To tackle these problems we have developed 1) programs to construct, manipulate, and display large scale, three-dimensional geometric models, 2) a three-dimensional, adaptive, finite element program for elliptic partial differential equations with general boundary conditions and source terms, 3) programs that apply global and local regularization and solve the system of equations, and 4) visualization tools for displaying the results. Due to the large size of the problems, much of the software development has been designed to take advantage of parallel processing via distributed systems of RISC workstations.
F-RISC/I, a reduced version of a fast RISC microprocessor, has been designed and fabricated using IBM's SBFL standard cell library and Rockwell International's 0.7 /spl mu/m HMESFET technology. F-RISC/I was de...
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F-RISC/I, a reduced version of a fast RISC microprocessor, has been designed and fabricated using IBM's SBFL standard cell library and Rockwell International's 0.7 /spl mu/m HMESFET technology. F-RISC/I was designed in six months by two designers using commercial design automation tools. Simulations have shown 400 MHz operation. the chip contains 92,340 transistors on a 7/spl times/7 mm/sup 2/ die and dissipates 3.8 W. the F-RISC/I processor exemplifies the CPU architecture, circuit design, and testing developed to fully take advantage of GaAs technology for high speed computing.< >
Telecommunication systems require high availability of primary backup power supplies, consisting of generators intended to secure the system against failures of the public mains. In the context of a national program o...
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Telecommunication systems require high availability of primary backup power supplies, consisting of generators intended to secure the system against failures of the public mains. In the context of a national program of refurbishment, France Telecom has developed new generators consisting of turbo-alternators designed with a single objective in mind: availability. the authors describe the architecture of a turbo-alternator based power system and its performance.< >
Communications latency forms a major obstacle to effective parallel processing. the bottlenecks of interprocessor communication can be caused by characteristics of a particular architecture or a particular application...
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Communications latency forms a major obstacle to effective parallel processing. the bottlenecks of interprocessor communication can be caused by characteristics of a particular architecture or a particular application, and especially by the relationship between the two. We believe that efficient parallel processing requires serious attention to this intersection of architecture and application. In this paper we report: our analysis of the execution behavior of three programs from the SPLASH set, using two multiprocessor systems and a simulator; our identification of one program as especially hostile to multiprocessors; and the results of our efforts to improve the performance of that program by applying our detailed knowledge of the relationship between application and architecture.< >
the poloidal field system for Alcator C-Mod (a high-field compact tokamak) can generate elongated, single or double null diverted plasmas. the shape control system consists of hardware (hybrid multiplier, real-time co...
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the poloidal field system for Alcator C-Mod (a high-field compact tokamak) can generate elongated, single or double null diverted plasmas. the shape control system consists of hardware (hybrid multiplier, real-time control computer, and associated electronics), the user interface (a set of X-Windows applications), and the underlying algorithms used by the interface to calculate the control matrices. the shape control computer generates demands to the power supplies, based on programmed waveforms and feedback from the diagnostics. Beginning in April 1993 we have used the shape control computer to program and/or feed-back control coil currents, power supply voltages, magnetic field quantities and gas pressure during plasma breakdown, and to tailor the fields during the current ramp. Representative data from the 1993 run and an evaluation of the overall performance of the shape control computer will be presented.
Generating local addresses and communication sets is an important issue in distributed-memory implementations of data-parallel languages such as highperformance Fortran. We show that for an array A affinely aligned t...
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ISBN:
(纸本)0897915895
Generating local addresses and communication sets is an important issue in distributed-memory implementations of data-parallel languages such as highperformance Fortran. We show that for an array A affinely aligned to a template that is distributed across p processors with a cyclic(κ) distribution, and a computation involving the regular section A(: h: s), the local memory access sequence for any processor is characterized by a finite state machine of at most κ;states. We present fast algorithms for computingthe essential information about these state machines, and extend the framework to handle multidimensional arrays. We also show how to generate communication sets using the state machine approach. performance results show that this solution requires very little runtime overhead and acceptable preprocessing time.
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