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7th International symposium on Innovative Approaches in Smart Technologies, ISAS 2023

作者： Singh, Kamred Udham Kumar, Ankit Kumar, Gaurav Choudhury, Tanupriya Kotecha, Ketan Graphic Era Hill University School of Computing Dehradun India GLA University Department of Computer Engineering & Applications UP Mathura India Maharashtra Pune412115 India Symbiosis Centre for Applied Artificial Intelligence Symbiosis Institute of Technology Maharashtra Pune412115 India

ISBN: (纸本)9798350383065

Mobile Ad hoc Networks (MANETs) may self-configure and rely on wireless connections rather than a permanent infrastructure;hence this research delves into their intricacies. this research aims to better understand how MANETs function. MANETs are characterized by their high degree of dynamism and adaptability to changes in network architecture. these networks are made up of mobile nodes that are independent and can perform the functions of both a host and a router. Having said that, this flexibility does provide a number of substantial issues, notably in the area of routing. the unexpected and fluid nature of MANET topology, which is related to the mobility of the nodes, makes routing a hard process. the effectiveness of the network is strongly reliant on the efficacy of the routing protocols that are implemented;therefore this is an important consideration. Our study analyses the capabilities of three popular MANET routing protocols: DSDV, AODV, and DSR. these protocols must be compared using end-to-end latency, packet delivery percentage, and lost packet ratio across different network densities and mobility patterns. In our simulations, we seek to replicate a wide variety of situations that can occur in the real world by altering the number of nodes, the connection counts, and the pause periods. these simulations are carried out with the help of the Network Simulator 2 (version 2.35), a programme that is well-known for its use in network research. Additionally, the graphical representation of the data is carried out with the assistance of gnuplot. Our first findings suggest that AODV has a significant advantage over DSDV and DSR when it comes to handling the dynamic networking environment of MANETs more effectively. this is especially true in situations characterised by high node mobility and variable network density. this research not only highlights the necessity of selecting the appropriate routing protocol in MANETs, but it also offers a thorough framework for

关键词： Routing protocols

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LazyBatching: An SLA-aware Batching System for Cloud Machine Learning Inference 27

LazyBatching: An SLA-aware Batching System for Cloud Machine...

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27th IEEE International symposium on high-performance computer architecture (HPCA)

作者： Choi, Yujeong Kim, Yunseong Rhu, Minsoo Korea Adv Inst Sci & Technol Sch Elect Engn Daejeon South Korea

ISBN: (纸本)9781665422352

In cloud ML inference systems, batching is an essential technique to increase throughput which helps optimize total-cost-of-ownership. Prior graph batching combines the individual DNN graphs into a single one, allowing multiple inputs to be concurrently executed in parallel. We observe that the coarse-grained graph batching becomes suboptimal in effectively handling the dynamic inference request traffic, leaving significant performance left on the table. this paper proposes LazyBatching, an SLA-aware batching system that considers both scheduling and batching in the granularity of individual graph nodes, rather than the entire graph for flexible batching. We show that LazyBatching can intelligently determine the set of nodes that can be efficiently batched together, achieving an average 15x, 1.5x, and 5.5x improvement than graph batching in terms of average response time, throughput, and SLA satisfaction, respectively.

关键词： computer architecture machine learning deep learning inference server batching

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Parallel Intelligent computing in Algebraic Problems 15th

Parallel Intelligent Computing in Algebraic Problems

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15th International Scientific Conference on Parallel Computational Technologies (PCT)

作者： Il'in, Valery Novosibirsk State Univ Inst Computat Math & Math Geophys SB RAS Novosibirsk Russia

ISBN: (纸本)9783030816919;9783030816902

We consider the issues associated with the creation of an intelligent computing environment for the high-performance solution of a wide class of large algebraic problems, which makes up the most resource-intensive stage of mathematical modeling. the first area of research is devoted to automating the construction of parallel algorithms and their mapping onto supercomputer architecture by investigating the problem of classification and identification of matrix statements and selecting algorithms for specific situations relying on optimization methods. the second aspect is related to the creation of intelligent interfaces, both for internal inter-module interactions and for end-users from various professional backgrounds. the rich functionality of the high-tech software under discussion requires an advanced system content to manage machine experiments. the scale of this development puts on the agenda the creation of an integrated tool environment or ecosystem, as well as the concept of a mathematical knowledge base.

关键词： Algebraic problems Large sparse matrices Classification and identification of statements Selection of optimal parallel algorithms Intelligent computing environment

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Bridging the Gap: Accelerating Random Forests on FPGAs with high-Bandwidth Memory

Bridging the Gap: Accelerating Random Forests on FPGAs with ...

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IEEE Latin American symposium on Circuits and Systems (LASCAS)

作者： Icaro Moreira Lucas Bragança Olavo Silva Alysson Silva Ricardo S. Ferreira José Augusto M. Nacif Universidade Federal de Viçosa Brazil

ISBN: (数字)9798331522124

ISBN: (纸本)9798331522131

In memory-bound problems, Field Programmable Gate Arrays (FPGAs) have traditionally underperformed compared to Graphics Processing Units (GPUs) due to their lower memory bandwidth. However, high bandwidth memory (HBM) in FPGAs has significantly enhanced their performance, achieving bandwidths up to 425 GB/s. Additionally, FPGAs offer the advantage of customizable accelerators for domain-specific tasks, potentially outperforming general-purpose GPU architectures. this work focuses on accelerating random forest algorithms on FPGAs, leveraging their customization capabilities to manage control flow structures such as decision branches efficiently. Despite these advancements, FPGAs remain challenging to program, requiring a deep understanding of hardware design. We propose a new hardware generator that integrates necessary tools into a cohesive workflow to address this, simplifying FPGA development. We validated the design on a Xilinx Alveo FPGA, using 32 HBM channels and reaching a performance of 8 billion samples per second. this work offers a practical solution for memory-bound machine learning tasks in high-performance computing environments.

关键词： Circuits and systems high performance computing Graphics processing units Bandwidth computer architecture Logic gates Hardware Generators Field programmable gate arrays Random forests

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Towards a Personalized LLM-Based Daily Edge Memory Aid

Towards a Personalized LLM-Based Daily Edge Memory Aid

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International Conference on Information and Communication Technology Convergence (ICTC)

作者： Sangil Ha Dongbeom Ko Joon-Ho Lim Sungjoo Kang Hyeon Soo Kim AI Lab Tutorus Labs Inc. Deajeon Republic of Korea AI Computing System SW Research Section Electronics and Telecommunications Research Institute (ETRI) Deajeon Republic of Korea Department of Computer Science and Engineering Chungnam National University (CNU) Deajeon Republic of Korea

ISBN: (数字)9798350364637

ISBN: (纸本)9798350364644

this paper introduces a personalized memory aid system that combines a high-performance cloud-based large language model (LLM) with a low-power edge device running a small language model (sLM) to enhance user productivity by processing and summarizing daily conversations in real-time. the system optimizes efficiency and user experience while ensuring privacy through localized data handling. By combining cloud and edge resources, the system provides scalable, real-time memory support without compromising data security. the research highlights the system's architecture, its role in protecting user data, and its potential to seamlessly integrate into daily life, offering a sustainable and efficient approach to personalized artificial intelligence applications.

关键词： performance evaluation Productivity Data privacy Systems architecture Oral communication Data processing Real-time systems Hardware User experience Resource management

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Dynamic Input Pruning-Based Low-Power and Error-Optimized Approximate Adder

Dynamic Input Pruning-Based Low-Power and Error-Optimized Ap...

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International Conference on computing and Networking Technology (ICCNT)

作者： Lalit Bandil Bal Chand Nagar Electronics and Communication Engineering National Institute of Technology Patna Patna India

ISBN: (数字)9798350370249

ISBN: (纸本)9798350370270

this paper proposes a new low-power and error-optimized approximate adder that leverages the dynamic input pruning technique and a reduced bit width adder. Traditional Ripple Carry Adder and Carry Look-ahead Adder suffer from large delays and high power consumption, respectively, particularly in applications where accuracy can be traded off for performance. the proposed dynamic input pruning technique carefully selects significant bits from input operands and passes them to a reduced-width exact adder, thereby shortening the critical path and improving performance metrics such as power consumption, delay, and accuracy. the design is implemented using Verilog-HDL on an Artix-7 FPGA platform in Xilinx Vivado EDA tool, enabling efficient hardware realization and evaluation. Experimental results demonstrate 36% reductions in dynamic power consumption and 9.6% shorter path delay compared to conventional adder while improving error metrics up to 47% compared to the state-of-the-art approximate adder. A trade-off analysis confirms the effectiveness of the proposed adder with available approximate adders.

关键词： Measurement Power demand Accuracy Runtime computer architecture Hardware Delays Hardware design languages Adders Field programmable gate arrays

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An Overview of Adaptive Dynamic Deep Neural Networks via Slimmable and Gated architectures

An Overview of Adaptive Dynamic Deep Neural Networks via Sli...

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International Conference on Information and Communication Technology Convergence (ICTC)

作者： Timothy K Johnsen Ian Harshbarger Marco Levorato University of California Irvine USA

ISBN: (数字)9798350364637

ISBN: (纸本)9798350364644

Deep Neural Networks (DNN) are omnipresent in systems that are developed for processing vast quantities of data, most particularly images, for tasks such as perception, navigation, classification, detection, and segmentation. Such DNNs can be computationally demanding from the high number, upwards to hundreds of billions, of computations required during execution. Dynamic Deep Neural Networks (DDNN) are an evolution that allow the number of computations in a DNN to be scaled down. However, lacking in DDNN methodologies is the functionality to control online when and how to scale down the number of computations. To respond to this need, Adaptive Dynamic Deep Neural Networks (ADDNN) are an evolving class of deep learning models used in high performance computing that attempt to minimize resources usage - memory and power - and latency while maintaining an acceptable task performance by adapting the model architecture in response to the current context. thus, ADDNNs are a State-of-the-Art evolution that perceive context, on a case-by-case basis, and adapt the number of computations to that required by the difficulty of the problem at hand. this positional paper is not only a survey of current DDNN methods in literature, but also an analysis into the considerations, design principles and challenges in developing robust ADDNN systems and applications.

关键词： Training Surveys Adaptation models Runtime Adaptive systems Navigation Computational modeling Artificial neural networks computer architecture Context modeling

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SMALL BUT UNWIELDY: A LOWER BOUND ON ADJACENCY LABELS FOR SMALL CLASSES

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SIAM Journal on computing 2024年第5期53卷 1578-1601页

作者： Bonnet, Édouard Duron, Julien Sylvester, John Zamaraev, Viktor Zhukovskii, Maksim Université de Lyon ENS de Lyon UCBL CNRS LIP Lyon France Department of Computer Science University of Liverpool Liverpool United Kingdom Department of Computer Science University of Sheffield Sheffield United Kingdom

We show that for any natural number s, there is a constant γ and a subgraph-closed class having, for any natural n, at most γn graphs on n vertices up to isomorphism, but no adjacency labeling scheme with labels of size at most s log n. In other words, for every s, there is a small—even tiny—monotone class without universal graphs of size ns. Prior to this result, it was not excluded that every small class has an almost linear universal graph, or equivalently a labeling scheme with labels of size (1 + o(1)) log n. the existence of such a labeling scheme, a scaled-down version of the recently disproved Implicit Graph Conjecture, was repeatedly raised [Gavoille and Labourel, Proceedings of the 15th Annual European symposium on Algorithms, Lecture Notes in Comput. Sci. 4698, Springer, 2007, pp. 582-593;Dujmović et al., J. ACM, 68 (2021), pp. 1-33;Bonamy, Gavoille, and Pilipczuk, SIAM J. Discrete Math., 36 (2022), pp. 2082-2099;Bonnet et al., Comb. theory, 2 (2022)]. Furthermore, our small monotone classes have unbounded twin-width and thus simultaneously disprove the already-refuted Small conjecture, but this time with a self-contained proof, not relying on elaborate group-theoretic constructions. As our main ingredient, we show that with high probability an Erd"os-Rényi random graph G(n, p) with p = O(1/n) has, for every k ≤ n, at most 2O(k) subgraphs on k vertices, up to isomorphism. As a barrier to our general method of producing even more complex tiny classes, we show that when p = ω(1/n), the latter no longer holds. More concretely, we provide an explicit lower bound on the number of unlabeled k-vertex induced subgraphs of G(n, p) when 1/n ≤ p ≤ 1 - 1/n. We thereby obtain a threshold for the property of having exponentially many unlabeled induced subgraphs: if min{p, 1 - p} ∘(n), whereas if C/n θ(n). this result supplements the study of counting unlabeled induced subgraphs that was initiated by Erd" os and Rényi with a question on the number of unlabeled induced s

关键词： Group theory

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Circular Reconfigurable Parallel Processor for Edge computing : Industrial Product ✶

Circular Reconfigurable Parallel Processor for Edge Computin...

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Annual International symposium on computer architecture, ISCA

作者： Yuan Li Jianbin Zhu Yao Fu Yu Lei Toshio Nagata Ryan Braidwood Haohuan Fu Juepeng Zheng Wayne Luk Hongxiang Fan AzurEngine Technologies Tsinghua University Sun Yat-Sen University Imperial College London University of Cambridge

ISBN: (数字)9798350326581

ISBN: (纸本)9798350326598

Graphics Processing Units (GPUs) have emerged as the predominant hardware platforms for massively parallel computing. However, their inherent von-Neumann architecture still suffers performance inefficiency stemming from the sequential instruction execution and frequent data transfer overheads within the memory system. these intrinsic architectural flaws lead to heavy overhead on the latency, area, and energy efficiency, rendering GPUs suboptimal for edge computing applications. To tackle these challenges, this paper introduces a novel circular Reconfigurable Parallel Processor (RPP) to enable massively parallel applications in edge computing with high efficiency. RPP features a novel circular array of reconfigurable compute engines, enabling efficient streaming dataflow processing. In contrast to traditional Coarse Grained Reconfigurable architecture (CGRA), the circular network topology of RPP is formed by linear switch networks with an innovative gasket memory, which reduces complicated network routing overheads while allowing versatile datapath mapping and optimized data reuse. A dedicated hierarchical memory system is proposed to support different memory access patterns and address mapping strategies, enabling flexible data access with high memory efficiency. Several hardware optimizations are further introduced to improve hardware utilization and performance such as concurrent kernel execution, register split&refill and heterogeneous scalar&vector computing. To fully utilize the hardware capability of RPP, we develop an end-to-end software stack consisting of a compiler, runtime environment, and different RPP libraries. this software stack is designed to be compatible with the GPGPU computing paradigm, enhancing its potential for broader adoption. Fabricated in a 14nm process, RPP occupies an area of 119 mm 2 and operates at a maximum power of 15W with a 1GHz clock frequency. From the runtime measurement of various workloads, RPP achieves up to 27.5 × higher

关键词： Runtime environment Memory management Gaskets Full stack Switches Linear algebra Hardware

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Analysis and Design of a Compute-in-Memory System for Epileptic Seizure Detection System

Analysis and Design of a Compute-in-Memory System for Epilep...

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Midwest symposium on Circuits and Systems (MWSCAS)

作者： Mobeen Gulfaraz Sam Johnson Wala Saadeh Electrical Engineering Dept. Lahore University of Management Sciences (LUMS) Lahore Pakistan Engineering and Design Dept. Western Washington University (WWU) Bellingham WA USA

ISBN: (数字)9798350387179

ISBN: (纸本)9798350387186

this paper presents an area and power-efficient design of a dual-channel electroencephalogram (EEG) based digital processor that can identify the onset of seizures with high accuracy. Multiple modules, including feature extraction and classification, constitute the hardware design. Neural networks are employed as classifiers because of their exceptional performance. these networks are data-driven algorithms that cause the system's performance to deteriorate and its power consumption to increase. A compute-in-memory (CIM) architecture has thus been used to address this problem. the performance of the neural network algorithm is evaluated using an open-source database of CHBMIT with 87.1% accuracy, 91.2% sensitivity, and 90.5% specificity. In contrast, the performance of hardware architecture was evaluated using its power, area, and latency. the synthesis and implementation were carried out using the 0.18µm CMOS process. A comparison of two architectures, the fixed point neural network architecture and the CIM neural network architecture, clearly indicated that the CIM processor performed significantly better in terms of power and area while sacrificing latency because of bit serial computing. To detect seizures in real-time, the CIM processor consumes 241µJ/classification while the fixed-point neural network consumes 256µJ/classification of energy.

关键词： Accuracy Sensitivity Neural networks computer architecture In-memory computing Feature extraction Hardware

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