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All-Optical Reconfigurable Activation Function Based on Saturable Absorption

All-Optical Reconfigurable Activation Function Based on Satu...

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IEEE International symposium on Quality Electronic Design

作者： Oceane Destras Felipe Gohring De Magalhaes Sébastien Le Beux Gabriela Nicolescu Département de génie informatique et génie logiciel Polytechnique Montreal Montreal QC Canada Department of Electrical and Computer Engineering Concordia University Montreal QC Canada

ISBN: (数字)9798331509422

ISBN: (纸本)9798331509439

the development of optical neural networks (ONNs) has opened up new possibilities for high-speed and energy-efficient computing. However, the limited range of available optical activation functions poses a significant bottleneck. To address this, we propose an all-optical, reconfigurable activation function circuit based on semiconductor saturable absorber mirrors and Mach-Zehnder interferometers, capable of emulating activation functions such as ReLU, Sigmoid, and Tanh. the reprogrammability of the proposed design allows the same circuit to be reused for multiple tasks by dynamically adjusting the activation function, optimizing both space and energy efficiency in ONNs. through extensive testing, we have identified the most critical parameters of the optical activation function for effective training of ONNs. We demonstrate via numerical simulation that this optical activation function achieves competitive results for the performance of ONNs, reaching up to 98.5% accuracy on the MNIST dataset.

关键词： Integrated optics Training Optical interferometry Optical design Neural networks Optical computing computer architecture Optical fiber networks Nonlinear optics high-speed optical techniques

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A Review of Dew and Edge computing: Two Sides of a Modern Internet of things Solution 15th

A Review of Dew and Edge Computing: Two Sides of a Moder...

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15th International Conference on ICT Innovations, ICT Innovations 2023

作者： Gusev, Marjan Faculty of Computer Science and Engineering Sts Cyril and Methodius University in Skopje Skopje Macedonia

ISBN: (纸本)9783031543203

Dew and edge computing are the sophisticated post-cloud architectural approaches that bring computing closer to the user for applications addressing the Internet of things. In this paper, we analyze the requirements of post-cloud architectures to build such a solution, which clarify the main differences between dew and edge computing approaches. the analysis includes energy consumption, communication and processing requirements, latency, and throughput, and the evaluation shows how these requirements impact performance. In addition, we also analyze architectural approaches, including hardware/software coexistence, scalability, hardwareless computing, virtualization, interoperability, and portability. this research will check the validity of a hypothesis whether the dew and edge computing two sides of the same modern Internet of things solution. © the Author(s), under exclusive license to Springer Nature Switzerland AG 2024.

关键词： Energy utilization

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Evaluating Energy Efficiency of GPUs using Machine Learning Benchmarks

Evaluating Energy Efficiency of GPUs using Machine Learning ...

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IEEE International symposium on Parallel and Distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Brett Foster Shubbhi Taneja Joseph Manzano Kevin Barker Department of Computer Science Worcester Polytechnic Institute High Performance Computing Group Pacific Northwest National Laboratory

As we enter the exascale era, the energy efficiency and performance of high-performance computing (HPC) systems, especially running Machine Learning (ML) applications, are becoming increasingly important. Nvidia recently released its 9th-generation HPC-grade Graphics Processing Unit (GPU) microarchitecture, Ampere, claiming significant improvements over the previous generation’s Volta architecture. In this paper, we perform fine-grained power collection and assess the performance of these two HPC architectures’ performance by profiling ML benchmarks. In addition, we analyze various hyperparameters, primarily the batch size and the number of GPUs, to determine their impact on these systems’ performance and power efficiency. While Ampere is 3.16x more energy-efficient than Volta in isolation, this is counteracted by the PCIe interconnects of the A100s as the ML tasks are parallelized to run on more GPUs.

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SOPHGO BM1684X: A Commercial high performance Terminal AI Processor with Large Model Support

SOPHGO BM1684X: A Commercial High Performance Terminal AI Pr...

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IEEE/ACM International symposium on Microarchitecture (MICRO)

作者： Peng Gao Yang Liu Jun Wang Wanlin Cai Guangchong Shen Zonghui Hong Jiali Qu Ning Wang State Key Laboratory of Networking and Switching Technology Beijing University of Posts and Telecommunications Beijing China SOPHGO TECHNOLOGIES PTE. LTD. Beijing China

ISBN: (数字)9798350350579

ISBN: (纸本)9798350350586

this paper presents BM1684X, a cutting-edge AI processor from SOPHGO designed to meet the demanding requirements of broad AI applications. Firstly, we employ SIMD architecture with very large data width to design our TPU to reduce the area ratio of the instruction unit and greatly improves the computing power density. Secondly, the customization of special acceleration instructions within the EU enables the dynamic pipeline execution, leading to a reduction in the total number of instructions and execution time. this customization enhances the performance of TPU in processing RQ and DQ operations, crucial for AI computations. thirdly, the CUBE array within the TPU implements the multiplication and addition operations of 64 pairs of INT8 operands in the channel dimension of the feature map. By utilizing an addition tree instead of a conventional adder, the implementation significantly reduces both area and power consumption, optimizing the efficiency of TPU. Additionally, the BM1684X processor incorporates a 64-input, 64-output, 8-bit crossbar within the lane, facilitating high-performance data gathering. this crossbar design enhances data gathering capabilities, enabling efficient data processing and manipulation within the TPU architecture. Furthermore, BM1684X offers three distinct memory access modes, showing the processor's versatility in addressing a wide range of AI processing needs and optimizing DRAM utilization for various tasks and workloads. Finally, we design a TPU-MLIR toolchain, highlighting its rich features such as unified processing of multiple frameworks, hierarchical design of model abstractions, correctness guarantees, and traceability of each transformation step. BM1684X excels in providing high-performance computing for a variety of AI models including large models, demonstrating its capabilities through comprehensive evaluations with industry-leading peers.

关键词： Power system measurements Power demand Microarchitecture Single instruction multiple data Computational modeling high performance computing Pipelines Random access memory computer architecture Artificial intelligence

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Functional Validation on Complex Power Integrity Network Design

Functional Validation on Complex Power Integrity Network Des...

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IEEE/CHMT(CPMT) International Electronics Manufacturing Technology symposium

作者： Dilukshan Karunatilaka Fern Nee Tan Mohammad Shahrir Tamrin Sze Geat Pang Client Computing Group Intel Microelectronics Penang Malaysia

ISBN: (数字)9798350388824

ISBN: (纸本)9798350388831

With the recent introduction of disaggregated die architecture, power delivery network (PDN) performance expectations have shifted, from previously self-induced noise to concurrent workload noise. In pre-silicon simulation environment, it is rather challenging to accurately predict such workload conditions. In this paper, a new testing methodology is added to test disaggregated PDN architecture. Knowing that multiple high-Speed Input Output (HSIO) ports like PCIe4 and USB4 when stressed with concurrent traffic will have an impact on receiver (Rx) jitter. Instead of the traditional electrical validation approach, the team used a functional validation test bench, and validated using real world traffic scenarios; to stimulate power management of multiple different HSIOs concurrency for several weeks, while also resulting in a surprisingly small receiver margin degradation. the paper will conclude PDN improvement and validation coverage recommendations for future disaggregated architecture, knowing this is becoming the new computing trend.

关键词： Power system management Noise computer architecture Receivers Packaging Jitter Market research Manufacturing Testing Qualifications

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SNAFU: An Ultra-Low-Power, Energy-Minimal CGRA-Generation Framework and architecture 21

SNAFU: An Ultra-Low-Power, Energy-Minimal CGRA-Generation Fr...

引用

ACM/IEEE 48th Annual International symposium on computer architecture (ISCA)

作者： Gobieski, Graham Atli, Ahmet Oguz Mai, Kenneth Lucia, Brandon Beckmann, Nathan Carnegie Mellon Univ Pittsburgh PA 15213 USA

ISBN: (纸本)9781665433334

Ultra-low-power (ULP) devices are becoming pervasive, enabling many emerging sensing applications. Energy-efficiency is paramount in these applications, as efficiency determines device lifetime in battery-powered deployments and performance in energy-harvesting deployments. Unfortunately, existing designs fall short because ASICs' upfront costs are too high and prior ULP architectures are too inefficient or inflexible. We present SNAFU, the first framework to flexibly generate ULP coarse-grain reconfigurable arrays (CGRAs). SNAFU provides a standard interface for processing elements (PE), making it easy to integrate new types of PEs for new applications. Unlike prior high-performance, high-power CGRAs, SNAFU is designed from the ground up to minimize energy consumption while maximizing flexibility. SNAFU saves energy by configuring PEs and routers for a single operation to minimize switching activity;by minimizing buffering within the fabric;by implementing a statically routed, bufferless, multi-hop network;and by executing operations in-order to avoid expensive tag-token matching. We further present SNAFU-ARCH, a complete ULP system that integrates an instantiation of the SNAFU fabric alongside a scalar RISC-V core and memory. We implement SNAFU in RTL and evaluate it on an industrial sub-28 nm FinFET process across a suite of common sensing benchmarks. SNAFU-ARCH operates at <1 mW, orders-of-magnitude less power than most prior CGRAs. SNAFU-ARCH uses 41% less energy and runs 4.4x faster than the prior state-of-the-art general-purpose ULP architecture. Moreover, we conduct three comprehensive case-studies to quantify the cost of programmability in SNAFU. We find that SNAFU-ARCH is close to ASIC designs built in the same technology, using just 2.6x more energy on average.

关键词： Ultra low power energy-minimal design reconfigurable computing dataflow CGRA Internet of things (IoT)

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HybridTuner: Tuning with Hybrid Derivative-Free Optimization Initialization Strategies 15th

HybridTuner: Tuning with Hybrid Derivative-Free Optimization...

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15th International Conference on Learning and Intelligent Optimization (LION)

作者： Sauk, Benjamin Sahinidis, Nikolaos V. Carnegie Mellon Univ Dept Chem Engn Pittsburgh PA 15213 USA Georgia Inst Technol H Milton Stewart Sch Ind & Syst Engn Atlanta GA 30332 USA Georgia Inst Technol Sch Chem & Biomol Engn Atlanta GA 30332 USA

ISBN: (纸本)9783030921217;9783030921200

To utilize the full potential of advanced computer architectures, algorithms often need to be tuned to the architecture being used. We propose two hybrid derivative-free optimization (DFO) methods to maximize the performance of an algorithm after evaluating a small number of possible algorithmic configurations. Our autotuner (a) reduces the execution time of dense matrix multiplication by a factor of 1.4x compared to state-of-the-art autotuners, (b) identifies high-quality tuning parameters within only 5% of the computational effort required by other autotuners and (c) can be applied to any computer architecture.

关键词： Autotuners Derivative-free optimization GPU computing

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A compact and robust perceptual hashing function through self-supervised learning 11

A compact and robust perceptual hashing function through sel...

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11th Mediterranean Conference on Embedded computing (MECO) / 3rd Summer School on Cyber-Physical + Systems and Internet of things (CPS and IoT)

作者： Fonseca-Bustos, Jesus Ramirez-Gutierrez, Kelsey Alejandra Feregrino-Uribe, Claudia Inst Nacl Astrofis Opt & Electr Comp Sci Dept Santa Maria Tonantzintla Mexico

ISBN: (纸本)9781665468282

thanks to the Internet, it is easy to share and redistribute multimedia items for different purposes. However, to avoid malicious usage of sensitive data, it is desirable to have efficient ways to track and identify relevant items. A hash-based content identification system uses a robust perceptual hashing function to generate a short binary string to match query multimedia items with a set of relevant assets in a database. In low consumption systems, such as in IoT applications, the properties of this function are crucial to reducing the network bandwidth consumption to communicate with a server and efficiently compute the binary identifier with limited computing power. Moreover, it still requires to be adaptive to new scenarios. In this work, we propose to exploit the feature learning capabilities of convolutional neural networks to learn automatically a perceptual hashing function invariant against a set of expected manipulations. To achieve this, we define a compact and efficient architecture and a self-supervised learning pretext task that enforces a perceptual hashing algorithm's robustness and discrimination properties. We evaluate this approach against 15 manipulations with a comprehensive set of intensities in different datasets, achieving high robustness and identification performance.

关键词： perceptual hashing content identification self-supervised learning deep learning computer vision

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Introduction to Quantum Multi-Agent Reinforcement Learning: Concepts and Applications

Introduction to Quantum Multi-Agent Reinforcement Learning: ...

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International Conference on Information and Communication Technology Convergence (ICTC)

作者： Yeryeong Cho Seok Bin Son Soohyun Park Joongheon Kim Department of Electrical and Computer Engineering Korea University Seoul Republic of Korea Division of Computer Science Sookmyung Women's University Seoul Republic of Korea

ISBN: (数字)9798350364637

ISBN: (纸本)9798350364644

Advancements in quantum computer hardware and software have paved the way for the application of quantum computing across various fields. With the development of computers with thousands of qubits, the power of quantum is increasing. Because of efficiency in high action dimensions, quantum computing has advantages in multi-agent fields where the amount of data is huge. At the same time, reinforcement learning (RL) has gained prominence for its potential in unknown environments. Consequently, the integration of quantum computing and multi-agent reinforcement learning (MARL), known as quantum multi-agent reinforcement learning (QMARL), is proposed. this paper introduces the overall concept and applications of quantum computing, MARL, and QMARL. It also shows the current technology trends depending on the application. In conclusion, the paper presents challenges and future research directions for QMARL and shows that QMARL can be utilized in various applications for excellent performance.

关键词： Quantum computing Qubit Reinforcement learning Market research Software Hardware Information and communication technology Convergence

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A Unified Security Framework for RAN-CN Convergence Towards 6G Mobile Networks

A Unified Security Framework for RAN-CN Convergence Towards ...

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International Conference on Information and Communication Technology Convergence (ICTC)

作者： Myung-Eun Kim Namseok Ko Marcos Katz Network Research Division ETRI Daejeon Republic of Korea Centre for Wireless Communication University of Oulu Oulu Finland

ISBN: (数字)9798350364637

ISBN: (纸本)9798350364644

the introduction of mobile cloud computing and network virtualization in 5G technology has significantly enhanced the flexibility and agility of the core network, addressing the limitations inherent in LTE networks. Despite these innovations, 5G mobile networks continued to suffer from high signalling latency due to the adoption of a decoupled architecture, which clearly separates the radio access network (RAN) from the core network (CN). In preparation for the shift to 6G, many recent studies have considered RAN-CN convergence to address issues such as redundant control message processing and high signalling latency. this convergence is further motivated by the shift of both RAN and CN towards cloud-native technologies, aiming to improve agility, resilience, and cost-efficiency. To realize the converged RAN-CN architecture, it is necessary to implement robust security measures to ensure the protection of user privacy and the prevention of data leaks. this paper firstly introduces the converged RAN-CN architecture for next-generation mobile networks. then it proposes a unified security framework for the RAN-CN converged mobile network.

关键词： 6G mobile communication Cloud computing Technological innovation 5G mobile communication computer architecture Security Virtualization Convergence Radio access networks Resilience

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