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Dynamic thermal-Aware Scheduling Using Physics-Informed POD-Galerkin thermal Simulation Model for Multi-Core Processors : Invited Paper

Dynamic Thermal-Aware Scheduling Using Physics-Informed POD-...

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International Green computing Conference

作者： Anthony Dowling Ming-Cheng Cheng Yu Liu Department of Electrical and Computer Engineering Clarkson University

ISBN: (数字)9798331507862

ISBN: (纸本)9798331507879

Handling heavy computing tasks in real-time systems requires substantial power, leading to significant heat generation. this can cause serious thermal problems like rising temperatures, high thermal gradients, and hot spots. these issues can reduce chip performance, accelerate device aging, and cause premature failure. thermal-Aware Scheduling (TAS) optimizes heat management to maintain a safe temperature. In this work, we evaluate RT-TAS, an advanced TAS algorithm using a steady-state thermal model, and compare it with our proposed dynamic physics-informed POD-based TAS algorithm. POD-TAS utilizes a reduced order thermal model with a dynamic predictive approach, allowing precise temperature control during task scheduling. this reduces peak temperatures and thermal variations. Our tests on a multi-core processor demonstrate that POD-TAS significantly improves thermal performance. It reduces the average spatial thermal variance by 6.18%, the variance of the maximum CPU temperature over time by 59.68%, and the variance of the average temperature by 13.05% due to its ability to maintain the chip temperature within a set threshold.

关键词： Heating systems Processor scheduling Multicore processing Heuristic algorithms Predictive models Dynamic scheduling Prediction algorithms thermal management Real-time systems Steady-state

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Heterogeneous Multi-Functional Look-Up-Table-based Processing-in-Memory architecture for Deep Learning Acceleration

Heterogeneous Multi-Functional Look-Up-Table-based Processin...

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IEEE International symposium on Quality Electronic Design

作者： Sathwika Bavikadi Purab Ranjan Sutradhar Amlan Ganguly Sai Manoj Pudukotai Dinakarrao Department of Electrical and Computer Engineering George Mason University Fairfax VA USA Department of Computer Engineering Rochester Institute of Technology Rochester NY USA

Emerging applications including deep neural networks (DNNs) and convolutional neural networks (CNNs) employ massive amounts of data to perform computations and data analysis. Such applications often lead to resource constraints and impose large overheads in data movement between memory and compute units. Several architectures such as Processing-in-Memory (PIM) are introduced to alleviate the bandwidth bottlenecks and inefficiency of traditional computing architectures. However, the existing PIM architectures represent a trade-off between power, performance, area, energy efficiency, and programmability. To better achieve the energy-efficiency and flexibility criteria simultaneously in hardware accelerators, we introduce a multi-functional look-up-table (LUT)-based reconfigurable PIM architecture in this work. the proposed architecture is a many-core architecture, each core comprises processing elements (PEs), a stand-alone processor with programmable functional units built using high-speed reconfigurable LUTs. the proposed LUTs can perform various operations, including convolutional, pooling, and activation that are required for CNN acceleration. Additionally, the proposed LUTs are capable of providing multiple outputs relating to different functionalities simultaneously without the need to design different LUTs for different functionalities. this leads to optimized area and power overheads. Furthermore, we also design special-function LUTs, which can provide simultaneous outputs for multiplication and accumulation as well as special activation functions such as hyperbolics and sigmoids. We have evaluated various CNNs such as LeNet, AlexNet, and ResNet18,34,50. Our experimental results have demonstrated that when AlexNet is implemented on the proposed architecture shows a maximum of 200× higher energy efficiency and 1.5× higher throughput than a DRAM-based LUT-based PIM architecture.

关键词： Deep learning Neural networks computer architecture Programming throughput Energy efficiency Real-time systems

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A Nano-Based high-Speed QCA Circuit for Information Security with Image Masking

A Nano-Based High-Speed QCA Circuit for Information Security...

引用

Conference on Information and Knowledge Technology

作者： Saeid Seyedi Hatam Abdoli Department of Computer Engineering Faculty of Engineering Bu-Ali Sina University Hamedan Iran

ISBN: (数字)9798331522254

ISBN: (纸本)9798331522261

A potential method for nanoscale computing, quantum-dot cellular automata (QCA) makes use of the electron tunneling between quantum dots inside a cell as well as the electrostatic interaction between surrounding dots. QCA technology outperforms traditional complementary metal-oxide semiconductor (CMOS) technology in terms of speed, power consumption, security, and space utilization. Due to the importance of security, this article investigates utilizing QCA to generate picture masks and security in these pictures. the mask picture is created by an encoder circuit, which may also be used as a decoder. Even if the secret key is still unknown, the original picture can be retrieved using the mask image. Improving the security characteristics in nano-communication, which uses QCA cells and nanodevices, is essential. Image masking entails encrypting an image using a random key to generate an encrypted picture, also known as a cipher image. After that, the original picture and the cipher image are merged to create a mask image, a hidden information set for users. With the secret key, this mask picture may obtain an image from another cipher image created with the same set of random keys. To ensure security in this paper, the suggested QCA encoder generates the mask picture. the efficacy of these designs was confirmed by using QCADesigner for functional verification. the simulation results show that the suggested solutions not only work well but also much surpass earlier approaches in terms of speed and space consumption. the higher performance of these optimum designs over other circuit designs highlights the potential of QCA technology to improve picture masking and security.

关键词： Ciphers Microprocessors Quantum dots computer architecture Tunneling Nanoscale devices Decoding Security Digital circuits Standards

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Efficient and high-performance Sparse Matrix-Vector Multiplication on a Many-Core Array

Efficient and High-Performance Sparse Matrix-Vector Multipli...

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IEEE International symposium on Embedded Multicore Socs (MCSoC)

作者： Peiyao Shi Aaron Stillmaker Bevan Baas ECE Department University of California Davis Davis CA USA ECE Department California State University Fresno Fresno CA USA

ISBN: (纸本)9781665465007

Sparse matrix-vector multiplication (SpMV) is a critical operation in scientific computing, engineering, and other applications. Eight functionally-equivalent SpMV implementations are created for a fine-grained many-core platform with independent shared memory modules. these implementations are compared with a general-purpose processor (Intel Core-i7 3720QM) and a graphics processing unit (GPU, NVIDIA Quadro 620) and results are scaled to 32 nm CMOS. the performance (throughput per chip area) for all three platforms is compared when operating on a set of seven unstructured sparse matrices of varying dimensions up to 3.6 billion elements. the many-core implementations show a $54\times$ greater performance than the general-purpose processor, and $40\times$ greater performance than the GPU.

关键词： Scientific computing Multicore processing Area measurement Graphics processing units Memory modules Benchmark testing throughput

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Implementation of Edge-cloud Cooperative CNN Inference on an IoT Platform

Implementation of Edge-cloud Cooperative CNN Inference on an...

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IEEE International symposium on Embedded Multicore Socs (MCSoC)

作者： Yuan Wang Hidetomo Shibamura KuanYi Ng Koji Inoue Graduate School of Information Science and Electrical Engineering Kyushu University Fukuoka Japan Faculty of Information Science and Electrical Engineering Kyushu University Fukuoka Japan

ISBN: (纸本)9781665465007

Since the Internet of things (IoT) has become more widely used in various industrial situations, Artificial Intelligence (AI) programs, particularly Convolutional Neural Network (CNN) applications, are projected to be implemented on edge devices to meet high-accuracy and huge industry computing needs. Offloading computing-intensive workloads to the cloud is a promising solution for compact energy-constrained edge devices, but it tends to incur significant costs in total execution latency. For flexible and fine-grained offloading, this paper aims to design and implement an edge-cloud cooperative CNN inference framework on an IoT platform by targeting TensorFlow Lite. We have confirmed the implementation's feasibility and accuracy through the verification of implementing LeNet, AlexNet, and VGGNet. Intending to perform high-performance edge-cloud AI executions on the presented IoT platform, we evaluate the performance overhead (total execution latency) of the provided implementation and identify the current bottlenecks of the target platform for enhancing it.

关键词： Industries Cloud computing Costs Multicore processing Convolutional neural networks Internet of things Artificial intelligence

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Enhancing Cloud Virtualization Security with a Z-Score Based Conjugate Self-Organizing Migration ML Model

Enhancing Cloud Virtualization Security with a Z-Score Based...

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International Conference on computing and Networking Technology (ICCNT)

作者： Sagar Sidana Sujata Negi thakur Anurag Sinha N Indhumathi Petheru Raj Ahmed Al-Khayyat Vyom Modi Aditya Mishra Anita Kumari Department of computer science and engineering Maharshi Dayanand University Rohtak Haryana India Department of computer science and engineering Graphic Era Hill University India School of Computing and information Science IGNOU New Delhi India Department of Electronics and Communication Engineering Kongu Engineering College Perundurai Erode India Reliance Jio Platforms Ltd Bangalore India Department of computer science and engineering Islamic University Iraq Marwari Education Foundations Group Of Institutions Rajkot India Department of computer science and engineering Applications GLA University Mathura India Department f English Literature RKDF University India

ISBN: (数字)9798350370249

ISBN: (纸本)9798350370270

this study presents a new machine learning model for detecting malware in cloud computing settings called Conjugate Self-Organizing Migration (CSOM), which is based on Z-score. Feature vectors are standardized by the model through the use of Z-score normalization, which improves its flexibility with changing data distributions. By merging self-organizing migratory processes with statistical analysis, the CSOM model effectively reduces the threat of growing malware. Using Z-score normalization to guarantee correct representation of changing data, the imaging approach depicts the cloud environment as a dynamic, self-organizing landscape. through conjugate migration techniques, the CSOM model dynamically modifies synaptic weights to minimize false positives and enable the identification of tiny fluctuations in harmful actions. the Z-score-based CSOM model is effective in detecting malware at high accuracy rates in a variety of dynamic cloud environments, as demonstrated by the experimental results. the model demonstrates its flexibility in responding to changing cyberthreats with its strong performance in real-world settings. Finally, with its better accuracy and adaptability, the suggested Z-score-based CSOM model offers a potential approach for cloud computing virus detection. In order to handle the constantly shifting environment of cloud-based cyber threats, further research may examine scalability and more refinement.

关键词： Cloud computing Adaptation models Accuracy Statistical analysis Computational modeling Scalability Vectors Security Virtualization Viruses (medical)

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Predictive Modeling of Cryptocurrency Prices Using Machine Learning Algorithms

Predictive Modeling of Cryptocurrency Prices Using Machine L...

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International Conference on computing and Networking Technology (ICCNT)

作者： Tanjim Mahmud Tahmina Akter Rishita Chakma Tikle Barua Mohammad Shahadat Hossain Karl Andersson Dept. of Computer Science and Engineering Rangamati Science and Technology University Rangamati Bangladesh Dept. of Computer Science and Engineering Port City International University Chittagong Bangladesh Dept. of Computer Science and Engineering University of Chittagong Chittagong Bangladesh Cybersecurity Laboratory Luleå University of Technology Luleå Sweden

ISBN: (数字)9798350370249

ISBN: (纸本)9798350370270

Cryptocurrencies, such as Bitcoin, Binance, Ethereum, FTX, and XRP, are decentralized digital assets known for their volatile nature and potential as investment instruments. Accurate price prediction is crucial for informed investment decisions. this study explores the feasibility of various modeling techniques on diverse data structures and features for predicting the prices of these cryptocurrencies. We utilize daily and high-frequency price data to classify and predict prices using deep learning and machine learning techniques, including LSTM, Bi-LSTM, GRU, linear regression, and SGD regression. Our findings indicate that daily price projections achieve an accuracy of 0.99, outperforming more complex deep learning and machine learning models. Compared to benchmark results, our approach demonstrates superior performance, with the highest scores achieved by the applied statistical methods and advanced algorithms. this research highlights the effectiveness of deep learning and machine learning models in cryptocurrency price forecasting, offering a foundation for further exploration in the field and emphasizing the significance of sample size in predictive modeling.

关键词： Deep learning Machine learning algorithms Accuracy Statistical analysis Computational modeling Linear regression Predictive models Prediction algorithms Long short term memory Investment

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CLITE: Efficient and QoS-Aware Co-location of Multiple Latency-Critical Jobs for Warehouse Scale computers 26

CLITE: Efficient and QoS-Aware Co-location of Multiple Laten...

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26th IEEE International symposium on high performance computer architecture (HPCA)

作者： Patel, Tirthak Tiwari, Devesh Northeastern Univ Boston MA 02115 USA

ISBN: (纸本)9781728161495

Large-scale data centers run latency-critical jobs with quality-of-service (QoS) requirements, and throughput-oriented background :jobs, which need to achieve high performance. Previous works have proposed methods which cannot co-locate multiple latency-critical jobs with multiple backgrounds jobs while: (I) meeting the QoS requirements of all latency-critical jobs, and (2) maximizing the performance of the background jobs. this paper proposes CLITE, a Bayesian Optimization-based, multi-resource partitioning technique which achieves these goals.

关键词： Latency Critical Jobs Multi Tenancy QoS Delivery Warehouse Scale computing

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Zero-Shot Synth-to-Real Depth Estimation: From Synthetic Street Scenes to Real-World Data

Zero-Shot Synth-to-Real Depth Estimation: From Synthetic Str...

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Brazilian symposium on computer Graphics and Image Processing (SIBGRAPI)

作者： Luís Gustavo Lorgus Decker Jose Luis Flores Campana Marcos Roberto e Souza Helena de Almeida Maia Helio Pedrini Institute of Computing University of Campinas Campinas SP Brazil

ISBN: (数字)9798350376036

ISBN: (纸本)9798350376043

this paper introduces a novel method for estimating depth maps from single images using a convolutional neural network (CNN) architecture. Our approach leverages synthetically generated data that simulates front views from autonomous vehicles. the model employs a ConvNeXt encoder and a U-Net-based decoder, achieving effective depth estimation performance. A scale- and shift-invariant loss function is utilized during training to enhance generalization capabilities. the proposed model demonstrates strong results on real-world datasets without requiring fine-tuning, highlighting the effective transfer of information from synthetic to real-world data. Additionally, we show that high-quality data significantly improves performance compared to larger, low-quality datasets.

关键词： Training Graphics Sensitivity Filtering Data integrity Estimation Feature extraction Data models Convolutional neural networks Synthetic data

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A highly Efficient SGEMM Implementation using DMA on the Intel/Movidius Myriad-2 32

A Highly Efficient SGEMM Implementation using DMA on the Int...

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32nd IEEE International symposium on computer architecture and high-performance computing (SBAC-PAD) / 11th Workshop on Applications for Multi-Core architectures (WAMCA)

作者： Bakshi, Suyash Johnsson, Lennart Univ Houston Dept Comp Sci Main Campus Houston TX 77204 USA

ISBN: (纸本)9781728199245

Reducing energy consumption and achieving high energy efficiency in computation has become the top priority in high performance computing. high energy efficiency generally requires high resource utilization since energy demand for many applications and architectures is dependent on active time. We show that by using DMA the 28nm CMOS node Myriad-2 Vision Processing Unit can achieve 25 GFLOPs/W for FP32 matrix-multiplication. Our main contributions are: (i) An analysis of data transfer needs for inner and outer-product formulations of matrix multiplication with respect to the Myriad-2 memory hierarchy, (ii) An efficient use of DMA for managing matrix block transfers between on-chip and main memory (iii) A detailed analysis of the effects of matrix block shapes and DRAM page faults on performance and energy efficiency.

关键词： DMA DRAM page faults Energy efficiency high bandwidth high performance Matrix multiplication Myriad 2 Outer product formulation SGEMM

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