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International symposium on Modeling, Analysis and Simulation of computer and Telecommunication Systems (MASCOTS)

作者： Wilfredo J. Robinson M. Flavio Esposito Maria A. Zuluaga Computer Science Department Saint Louis University USA Data Science Department Eurecom France

Deep Neural Networks (DNNs) process big datasets achieving high accuracy on incredibly complex tasks. However, this progress has led to a scalability impasse, as DNNs require massive amounts of processing power and local memory to be trained, making them impossible or impractical to be used on a single device. this situation has led to the design of distributed training architectures, where the DNN and the training data can be split among multiple processors. How to choose the appropriate distributed training architecture, however, remains an open question. To help bring insights into this debate, in this work we design a Distributed Training Simulator (DTS) that estimates the training time of a DNN in a distributed architecture through a mathematical model of the distributed architecture and resource-allocation heuristics. We illustrate the power of the proposed DTS through the implementation of five different distributed architectures, Pipeline Learning, Federated Learning, Split Learning, Parallel Split Learning, and Federated Split Learning, and we validate the accuracy of the training estimates using three different datasets of varying complexity and two different DNNs. Finally, we present a trade-off analysis to demonstrate the coherence of DTS estimates for diverse high-performance computing scenarios by comparing these estimates with the behaviors of a real computer cluster.

关键词： Training Deep learning Analytical models Program processors Computational modeling Scalability Neural networks

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FPGA-QHAR: throughput-Optimized for Quantized Two-Stream Human Action Recognition on the Edge

FPGA-QHAR: Throughput-Optimized for Quantized Two-Stream Hum...

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International symposium on high Capacity Optical Networks and Enabling Technologies, HONET

作者： Azzam Alhussain Mingjie Lin College of Engineering and Computer Science University of Central Florida Orlando Florida USA

Accelerating Human Action Recognition (HAR) efficiently for real-time surveillance and robotic systems on edge chips remains a challenging research field, given its high computational and memory requirements. this paper proposed an integrated end-to-end HAR scalable HW/SW accelerator co-design based on an enhanced 8-bit quantized Two-Stream SimpleNet-PyTorch CNN architecture. Our network accelerator was trained on UCF101 and UCF24 datasets and implemented on edge SoC-FPGA. Our development uses partially streaming dataflow architecture to achieve higher throughput versus network design and resource utilization trade-off. We also fused all convolutional, batch-norm, and ReLU operations into a single homogeneous layer and utilized the Lucas-Kanade motion flow method to enable a high parallelism accelerator design and optimized on-chip engine computing. Furthermore, our proposed methodology achieved nearly 81 % prediction accuracy with an approximately 24 FPS real-time inference throughput at 187MHz on ZCU104, which is 1.7x - 1.9x higher than the prior research. Lastly, the designed framework was benchmarked against several hardware chips for higher throughput and performance measurements and is now available as an open-source project on Github for training and implementation on edge platforms.

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A Numerical Assessment of the Efficacy of a Topography Design with Increasing Gradient Complexity for Filtering Biofouling Material through the Membrane Module of a Water Treatment System 15

A Numerical Assessment of the Efficacy of a Topography Desig...

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15th International Engineering and computing Research Conference, EURECA 2021

作者： Felicia, W.Y.M. Esmond, L.M.Z. School of Computer Science and Engineering Faculty of Innovation and Technology Taylor's University 1 Jalan Taylors Selangor Subang Jaya47500 Malaysia

Biofouling can also be defined as the micro-/macro- organisms stuck on the surface that has been submerged in water. this is normally found in marine industry and water treatment industry. there are 3 ways of antifouling where the 3rd method surface modification was the main point to be focused on. Surface modification has high potential for antifouling performance and is not harmful to the ecosystem. In this research study was to find out the efficacy of antifouling performance with increasing the gradient complexity. the 2 models used were smooth topography and circular topography and have been manipulated and simulated with WorkBench 2020, Computational Fluid Dynamic (CFD). the results were simulated with the correct meshed and models. the simulated results were converged and 2 hydrodynamic variables;velocity and wall shear were used to check the efficacy of antifouling performance. © 2021 Institute of Physics Publishing. All rights reserved.

关键词： Topography

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Efficient Error-Bounded Lossy Compression for CPU architectures

Efficient Error-Bounded Lossy Compression for CPU Architectu...

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International symposium on Modeling, Analysis and Simulation of computer and Telecommunication Systems (MASCOTS)

作者： Griffin Dube Jiannan Tian Sheng Di Dingwen Tao Jon C. Calhoun Franck Cappello Department of Computer Science Northwestern University Evanston IL Luddy School of Informatics Computing and Engineering Indiana University Bloomington IN Holcombe Department of Electrical and Computing Engineering Clemson University Clemson SC Mathematics and Computer Science Division Argonne National Laboratory Lemont IL

Modern HPC applications produce increasingly large amounts of data, which limits the performance of current extreme-scale systems. Lossy compression, helps to mitigate this issue by decreasing the size of data generated by these applications. SZ, a current state-of-the-art lossy compressor, is able to achieve high compression ratios, but its prediction/quantization methods contain RAW dependencies that prevent parallelizing this step of the compression. Recent work proposes a parallel dual prediction/quantization algorithm for GPUs which removes these dependencies. However, some HPC systems and applications do not use GPUs, and could still benefit from the fine-grained parallelism of this method. Using the dual-quantization technique, we implement and optimize a SIMD vectorized CPU version of SZ (vecSZ), and create a heuristic for selecting the optimal block size and vector length. We propose a novel block padding algorithm to decrease the number of unpredictable values along compression block borders and find it reduces the number of prediction outliers by up to 100%. We measure performance of our vecSZ against an CPU version of SZ using dual-quantization, pSZ, as well as SZ-1.4. Using real-world scientific datasets, we evaluate vecSZ on the Intel Skylake and AMD Rome architectures. vecSZ results in up to 32% improvement in rate-distortion and up to 15× speedup over SZ-1.4, achieving a prediction and quantization bandwidth in excess of 3.4 GB/s.

关键词： Analytical models Quantization (signal) Computational modeling Rate-distortion computer architecture Bandwidth Prediction algorithms

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Next-Gen IoT: 5G Realities and 6G Possibilities

Next-Gen IoT: 5G Realities and 6G Possibilities

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International Conference on computing and Networking Technology (ICCNT)

作者： Amrita Ticku Sagar Sidana Anurag Sinha S Sathesh Manas Uniyal Biresh Kumar Raj Shekhar Sinha Petheru Raj Ahmed Al-Khayyat Mansi Sikarwar Department of computer science and engineering Bharati Vidyapeeth’s College of Engineering India Department of computer science and engineering Maharshi Dayanand University Rohtak Haryana India School of Computing and information Science IGNOU New Delhi India India Department of Electronics and Communication Engineering Kongu Engineering College Perundurai Tamil Nadu India Department of computer science and engineering Graphic Era Hill University India Department of computer science and IT Amity University Jharkhand India Reliance Jio Platforms Ltd Bangalore India Department of computer science and engineering Islamic University Iraq Department Of Mechanical And Automation Indira Gandhi Technical University For Women India

ISBN: (数字)9798350370249

ISBN: (纸本)9798350370270

In a world where technology reigns supreme, the Internet of things has taken center stage, revolutionizing our lives in countless ways. Augmented reality, crystal-clear video streaming, self-driving cars, intelligent environments, and advanced healthcare are just a few examples of the IoT’s widespread impact. With these groundbreaking ideas in mind, the IoT demands faster data rates, wider bandwidth, increased capacity, swift data transmission, and minimal delays. Addressing these requirements head-on, this paper introduces 5G as the leading-edge technology capable of meeting these challenges. the fifth-generation cellular networks, known as 5G, offer a host of vital features that facilitate the widespread adoption of IoT. these features include device-to-device communication, where devices can directly exchange information without relying on a central server, coordinated multipoint processing to enhance network efficiency, massive machine type communication that enables seamless connectivity for countless IoT devices, ultra-reliable low latency communication to ensure critical data is transmitted swiftly and reliably, and extreme mobile broadband to support high-speed, uninterrupted connectivity on the go. It has paved ways for innovative wireless architecture and intelligent services and 6 G which will be the next step in this evolutionary cycle of wireless networks is expected to amplify this development to new and unimaginable levels. this article gives an extensive overview of the IoT technology, outlining its statistical and architectural trends, application scenarios, challenges and its potential. the research also offers a thorough and in-depth analysis of the current 5G-IoT environment. the use cases for 5 G in IoT systems are also emphasized. As a result, we discuss some of the key 5G IoT research directions and trends. After which we highlight the challenging areas of 5G-IoT and where special emphasis will be a necessity in paving the way for 6 G enabled

关键词： 6G mobile communication 5G mobile communication Wireless networks Transforms Ultra reliable low latency communication Streaming media Market research Telecommunications Internet of things Wireless fidelity

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A Few-Shot Learning for HAR Using 3D Siamese Network

A Few-Shot Learning for HAR Using 3D Siamese Network

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International Conference on computing and Networking Technology (ICCNT)

作者： Hua Guanghui G. Hemantha Kumar V. N. Manjunath Aradhya Punithavalli Dept. of studies in Computer Science University of Mysore Mysuru India Dept. of Computer Applications JSS Science and Technology University Mysuru India Department of Computer Applications Bharathiar University Coimbatore India

ISBN: (数字)9798350370249

ISBN: (纸本)9798350370270

In artificial intelligence, deep learning techniques were applied in a wide field due to their ability to automatically learn complex patterns from raw data, such as image classification, object detection, image generation, and video analysis in computer vision. these applications are just the tip of a substantial iceberg. With the development of deep techniques to achieve state-of-art accuracy, learn precisely relevant features from raw data, and improve the robustness of models to make them versatile solutions. the traditional deep learning techniques require vast computational resources, including high-performance computer GPUs or TPUs, and can be expensive in terms of hardware. In Human Activity Recognition Systems (HARs). the video needs more computational resources than image processing. In this paper, we proposed a few-shot learning approach based on a 3D Siamese Network with depth video sequences to address the action video similarity or dissimilar problem. Convolutional Neural Networks (CNNs) are well-suited for images and spatial data processing. the 3DCNN is an extension of CNNs to incorporate an additional temporal dimension to capture the temporal pattern. From the 3D Siamese network, we extract more effective features with spatial-temporal action information from raw data. We employed the 3DCNNs Siamese Network (3DCNNs+SN) with shared weight to recognize or classify a new class of data without new sample data only based on learning training existing sample constructed model. In addition, we divided the benchmark dataset MSR Action 3D dataset into sub-dataset1 (SD-1), sub-dataset2 (SD-2) and sub-dataset3(SD-3) to train and validate our proposed method. For dissimilar sub-dataset 2 we got a 98.1% accuracy, 33% on high-similar sub-dataset 3 and $\mathbf{63.5\%}$ on merged sub-dataset SD-4 from sub-dataset2 (SD-2) and sub-dataset3(SD-3).

关键词： Solid modeling three-dimensional displays Accuracy Computational modeling Feature extraction Robustness Data models Human activity recognition Data mining Few shot learning

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SnackNoC: Processing in the Communication Layer 26

SnackNoC: Processing in the Communication Layer

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26th IEEE International symposium on high performance computer architecture (HPCA)

作者： Sangaiah, Karthik Lui, Michael Kuttappa, Ragh Taskin, Baris Hempstead, Mark Drexel Univ Dept Elect & Comp Engn Philadelphia PA 19104 USA Tufts Univ Dept Elect & Comp Engn Medford MA 02155 USA

ISBN: (纸本)9781728161495

In this work, we propose and evaluate a Network-on-Chip (NoC) augmented with light-weight processing elements to provide a lean dataflow-style system. We show that contemporary NoC routers can frequently experience long periods of idle time, with less than 10% link utilization in HPC applications. By repurposing the temporal and spatial slack of the NoC, the proposed platform, SnackNoC, is able to compute linear algebra kernels efficiently within the communication layer with minimal additional resource costs. SnackNoC 'Snack' application kernels are programmed with a producer-consumer data model that uses the NoC slack to store and transmit intermediate data between processing elements. SnackNoC is demonstrated in a multi-program environment that continually executes linear algebra kernels on the NoC simultaneously with chip multiprocessor (CMP) applications on the processor cores. Linear algebra kernels are computed up to 6.15x faster on SnackNoC compared to an Intel Haswell EPx86 processing core. the cost of executing 'snack' kernels in parallel to the CMP applications is a minimal runtime impact of 0.01% to 0.83% due to higher link utilization, and an uncore area overhead of 1.1%.

关键词： computer architecture In network processing Network on chip Opportunistic computing

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Blockchain-Powered Pierarchical CP-ABE Ecological Big Data Sharing and Privacy Protection Scheme 19th

Blockchain-Powered Pierarchical CP-ABE Ecological Big Data S...

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19th CCF Conference on computer Supported Cooperative Work and Social computing, ChineseCSCW 2024

作者： Gao, Qiaomei Han, Wenxu Sa, Rula An, Qi Zhao, Yi Zhang, Jin Yu, Meiju College of Computer Science-College of Software Inner Mongolia University Hohhot China

ISBN: (纸本)9789819623754

With the rapid development of the Internet and big data technology, ecological big data, as the key foundation of ecosystem scientific research, has become the core support for solving ecological environment problems at present. therefore, the safe sharing of ecological big data is crucial. Aiming at the problems of "data silo" and easy to be tampered with in the secure sharing of ecological big data, this study proposes a blockchain-based ecological big data secure storage and sharing scheme, which combines the blockchain and the interplanetary file system (IPFS) to carry out distributed storage and constructs a distributed, tamper-resistant system architecture, realizing the secure storage and sharing of ecological big data;for the secure storage and sharing of ecological big data, it is necessary to use blockchain as the key foundation for scientific research on ecosystems, which is the core support for solving ecological problems. For the problem that private ecological data is easily leaked, this study proposes an access control policy and designs a hierarchical ciphertext attribute-based (CP-ABE) encryption algorithm, which divides the attributes of ecological big data according to different sensitivities, and encrypts data with different sensitivities using the designed hierarchical CP-ABE encryption algorithm in order to prevent the leakage of the data. Finally, the smart contract is used to check the data visitors for misbehavior and realize fine-grained access control. the security analysis shows that this architecture can effectively realize the secure storage and sharing of ecological big data. the performance analysis shows that the hierarchical CP-ABE encryption algorithm enhances the protection of high privacy data. © the Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2025.

关键词： Blockchain CP-ABE data sharing privacy preservation

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适用于边缘计算的6H并行计算架构

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计算机工程与科学 2023年第9期45卷 1544-1552页

作者：李磊郑黎明王宏义柴永毅刘培国国防科技大学电子科学学院湖南长沙410073 中国电子科技集团公司第十五研究所北京100083 军委装备发展部体系评估中心北京100009

针对云集中式计算模式在延时、安全、环境信息利用等方面的不足,近年来产业界和学术界提出了雾计算、移动边缘计算、移动云计算等不同边缘计算概念,其主要思想是将计算、存储、I/O等资源迁移到网络边缘,以提升各类应用的服务质量。但是... 详细信息

针对云集中式计算模式在延时、安全、环境信息利用等方面的不足,近年来产业界和学术界提出了雾计算、移动边缘计算、移动云计算等不同边缘计算概念,其主要思想是将计算、存储、I/O等资源迁移到网络边缘,以提升各类应用的服务质量。但是,现有的边缘计算架构通常直接采用云计算架构,存在互操作性差、资源利用率不高、资源管理粒度不够细、动态性不强等问题。深入分析边缘计算的特点,基于轻量级虚拟化、软件定义网络、并行计算等基本理念,提出适用于边缘计算环境的6H并行计算架构,即高性能、高可用、高可扩展、高模块化、高可伸缩、高易用。随后采用Python/C++混合编程模式实现了一个6H计算框架。在边缘计算典型硬件条件下,采用物联网典型用例对该计算框架进行了测试。其结果表明:随着计算进程和计算节点数据增加,计算耗时近似成线性下降,说明该计算框架的可扩展性和可伸缩性较好;在高并发条件下,计算框架表现优异,说明该框架具备高性能;在边缘服务器异常情况下,计算框架恢复时间快,说明该框架的可用性较好。另外,该计算框架采用CMD-Worker-Handler编程模型,高度模块化,二次开发简单方便,具有很好的易用性。

关键词：边缘计算雾计算移动边缘计算 6H 体系架构

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A Lightweight Folded Keccak-Based SHA-3 for Resource-Constrained Embedded Security

A Lightweight Folded Keccak-Based SHA-3 for Resource-Constra...

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IEEE International symposium on Embedded Multicore Socs (MCSoC)

作者： Siqi Xiong Dongsheng Liu Jiahao Lu Aobo Li Tianze Huang Chenjun Yang Ang Hu Yuejun Zhang School of Integrated Circuits Huazhong University of Science and Technology Wuhan China Faculty of Electrical Engineering and Computer Science Ningbo University Ningbo China

ISBN: (数字)9798331530471

ISBN: (纸本)9798331530488

Secure Hash Algorithm 3 (SHA-3) is a crucial component in modern cryptographic systems, particularly in applications demanding high security and efficiency. For example, it is vital in System-on-Chip (SoC) applications and resource-constrained environments like IoT devices and embedded systems. However, existing SHA-3 designs face challenges regarding resource limitations and computational efficiency. this paper presents a slice-oriented folded SHA-3 architecture supporting multiple folding parameters for embedded SoC in FPGA implementations. It targeted crypto engines and other resource-limited cryptographic applications. We identified the optimal folding direction and introduced a round function rescheduling method. We proposed a novel interleaving storage strategy to resolve clock cycle delays caused by data dependencies. Additionally, we proposed a simplified round constant mechanism to minimize area consumption. the slice-based folded architecture across all parameter sets are implemented on Xilinx Virtex-7, controlled by an ARM Cortex-M4 processor. Our design achieved a maximum frequency of 324 MHz and the compact implementation, resulting in the 92% reduction in slices compared to basic design. Furthermore, it offered 70% area reduction, 1.44× throughput improvement, and 1.91× gain in efficiency over the previous state of the art. these results show the potential of our design for resource-limited security applications, providing both hardware resource savings and enhanced performance.

关键词： Trusted computing Program processors Random access memory Process control throughput Computational efficiency System-on-chip Cryptography Field programmable gate arrays Clocks

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