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Should Quantum Processor Design be Considered a Topic in computer architecture Education? 2022

Should Quantum Processor Design be Considered a Topic in Com...

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Proceedings of the 53rd ACM Technical symposium on computer Science Education V. 2

作者： Marcelo Pias Brett Becker Qiao Xiang Mohamed Zahran Monica Anderson Federal University of Rio Grande (FURG) Rio Grande Brazil University College Dublin Dublin Ireland Xiamen University Fujian China New York University New York NY USA University of Alabama Tuscaloosa AL USA

ISBN: (纸本)9781450390712

New trends in computer architecture include non-general purpose architectures, brain-inspired design, agile hardware development and environmentally responsible design. computer Science students need to understand computer architecture to develop programs that can achieve high performance through a programmer's awareness of parallelism and latency. In a re-visit of curriculum guidelines, students could develop skills and competencies in less mature yet cutting-edge topics, including quantum computing. For example, should students understand and appreciate quantum processor design's components and characteristics? In a task to revise curricular guidelines, one faces the decision of which topics may be obsolete and should be dropped or modified. Equally important is deciding the set of topics that must be included. Such questions are hard to address, particularly for a curriculum intended to remain fresh under a 10-years horizon. For example, the danger of not properly promoting the discussion of quantum processor design in the new ACM/IEEE-CS/AAAI CS202X curricula is the long waiting cycle (15 years+) for any new revision. this BOF will foster the participants' interactions into a debate of whether new curricular guidelines should contain quantum processor design as part of the architecture and Organization (AR) Knowledge Area.

关键词： quantum processor design in computer architecture education cs202x curriculum

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Beyond the Black Box: Explainable AI for Glaucoma Detection and Future Improvements

Beyond the Black Box: Explainable AI for Glaucoma Detection ...

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International Conference on computing and Networking Technology (ICCNT)

作者： Avadhani Bindu Senthil Kumar thangavel K Somasundaram Sathyan Parthasaradhi Ram Gopal Pulgurthi Meenakshi Y Dhar Department of Computer Science and Engineering Amrita School of Computing Coimbatore Amrita Vishwa Vidyapeetham India Department of Mathematics Amrita School of Physical Sciences Coimbatore Amrita Vishwa Vidyapeetham India Sathyan Eye Hospital and Coimbatore Glaucoma Foundation Ramanathapuram Coimbatore India Medivista Eye Centre Safilguda Secunderabad India Department of Ophthalmology Amrita Institute of Medical Sciences Faridabad India

ISBN: (数字)9798350370249

ISBN: (纸本)9798350370270

Timely and precise identification of glaucoma is essential to avert irreversible vision loss. Automating glaucoma detection is essential whilst the disease worsens over time and manual screening methods possess limitations. It facilitates early identification and treatment in order to prevent the vision impairment. Machine learning and deep learning algorithms are efficient, nevertheless, they suffer from a lack of interpretability and require a substantial amount of data and computational resources. Transfer learning proves efficient by improving scarcity of data with enhanced performance. this study seeks to examine the operational characteristics of transfer learning approaches and employ XAI (eXplainable Artificial Intelligence) method LIME to achieve clear interpretability of the features obtained by the model for prediction, so as to address the challenges related to interpretability. this study has used a combined dataset consisting of RIMONE, PAPILA, CHAKSU, and AKSHI (a dataset created by the authors) to develop ResNet-50, ResNet50-V2, VGG-16, VGG-19, and EfficientNet-V2S models. Among the developed five models, ResNet-50 and EfficientNet-V2S provide better accuracy as demonstrated in this study with an analysis using metrics and feature visualization. Both models attain a maximum test accuracy of ${91.78\%}$ and the minimum test loss of, with ResNet-50 at 0.24 and EfficientNet-V2S at 0.23. In addition, these models demonstrate superior precision, specificity, sensitivity, and F1-score, all around 92. Further, feature maps and class activation maps for ResNet-50 and EfficientNet-V2S show distinct and concentrated zones of activation, indicating accurate interpretation. thus, in this comparative study, ResNet-50 and EfficientNet-V2S are choosen as the best models for this classification task owing to their high accuracy and reliable interpretability via visual activation patterns. Consequently, the mobile app ANSAN has been integrated with the ideal clinical

关键词： Glaucoma Deep learning Visualization Accuracy Sensitivity Explainable AI Computational modeling Transfer learning Decision making Visual impairment

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architecture Design of Intelligent Campus One-stop Service Platform Based on Middle Platform and Micro Service

Architecture Design of Intelligent Campus One-stop Service P...

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International Conference on Electronic Measurement and Instruments, ICEMI

作者： Manjing Zhu Modern Education Technology Center Jiangxi Open University School of Information Engineering Nanchang University Nanchang China

ISBN: (纸本)9781665444927

With the extensive application of big data, cloud computing, Internet of things, artificial intelligence, block chain and other complex scenarios, frequent switching and login between multiple systems, inconsistent data of various business systems, multiple filling and submission of the same data form and high concurrent applications emerge in an endless stream. To solve the above problems, according to the characteristics of middle platform and micro service architecture and one-stop service platform needs of wisdom campus, it was put forward that wisdom campus one-stop service platform architecture designing based on the concept of middle platform and micro service architecture. Meanwhile, taking Jiangxi Open University as an example, we have finished design and construction and implement. Result shows that the one-stop service platform is highly cohesive, loosely coupled, rapid response, easy to expand and manageable for wisdom teaching and management and service.

关键词： Cloud computing Instruments Education computer architecture Switches Big Data Filling

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Automation of Domain-specific FPGA-IP Generation and Test 21

Automation of Domain-specific FPGA-IP Generation and Test

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11th International symposium on highly Efficient Accelerators and Reconfigurable Technologies, HEART 2021

作者： Nakazato, Yuya Amagasaki, Motoki Zhao, Qian Iida, Masahiro Kuga, Morihiro Kumamoto University Japan Kyushu Institute of Technology Japan

ISBN: (纸本)9781450385497

Multi-access edge computing (MEC) devices that perform processing between the edge and cloud are becoming important in the Internet of things infrastructure. MEC devices are designed to reduce the load on the edge devices, ensure real-time performance, and reduce the communication traffic between the edge and cloud. In this paper, to enable high-performance and low-power hardware-accelerated processing for different application domains in MEC devices, we propose an automated flow for domain-specific field-programmable gate array intellectual property core (FPGA-IP) generation and testing. First, we perform logic cell exploration using a target user application to find the optimal scalable logic module (SLM) structure, and use the optimal SLM instead of a lookup table to reduce the logic area. Second, we perform routing and FPGA array exploration to determine other FPGA-IP architecture parameters. Finally, the proposed flow uses the explored parameters to automatically generate the entire FPGA-IP and LSI test bitstreams. In a case study, we optimized an FPGA-IP for a differential privacy encryption circuit using the proposed flow. We implemented and evaluated the FPGA-IP with a 55nm TEG chip design. Furthermore, the simulation-based LSI test showed that 100% of the stuck-at faults in the routing paths of the FPGA-IP were detected. © 2021 ACM.

关键词： computer aided design

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Part-Aware Attention Network for Person Re-identification 15th

Part-Aware Attention Network for Person Re-identification

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15th Asian Conference on computer Vision, ACCV 2020

作者： Xiang, Wangmeng Huang, Jianqiang Hua, Xian-Sheng Zhang, Lei Department of Computing The Hong Kong Polytechnic University Kowloon Hong Kong Artificial Intelligence Center Alibaba DAMO Academy Hangzhou China

ISBN: (纸本)9783030695378

Multi-level feature aggregation and part feature extraction are widely used to boost the performance of person re-identification (Re-ID). Most multi-level feature aggregation methods treat feature maps on different levels equally and use simple local operations for feature fusion, which neglects the long-distance connection among feature maps. On the other hand, the popular horizon pooling part based feature extraction methods may lead to feature misalignment. In this paper, we propose a novel Part-aware Attention Network (PAN) to connect part feature maps and middle-level features. Given a part feature map and a source feature map, PAN uses part features as queries to perform second-order information propagation from the source feature map. the attention is computed based on the compatibility of the source feature map with the part feature map. Specifically, PAN uses high-level part features of different human body parts to aggregate information from mid-level feature maps. As a part-aware feature aggregation method, PAN operates on all spatial positions of feature maps so that it can discover long-distance relations. Extensive experiments show that PAN achieves leading performance on Re-ID benchmarks Market1501, DukeMTMC, and CUHK03. © 2021, Springer Nature Switzerland AG.

关键词： Feature extraction

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Filipino Sign Language Recognition using Deep Learning 2021

Filipino Sign Language Recognition using Deep Learning

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5th International Conference on E-Society, E-Education and E-Technology, ICSET 2021

作者： Montefalcon, Myron Darrel Padilla, Jay Rhald Llabanes Rodriguez, Ramon College of Computing and Information Technologies National University-Manila Philippines Philippines

ISBN: (纸本)9781450390156

the Filipino deaf community continues to lag behind the fast-paced and technology-driven society in the Philippines. the use of Filipino Sign Language (FSL) has contributed to the improvement of communication of deaf people, however, the majority of the population in the Philippines do not understand FSL. this project utilized computer vision in obtaining the images and Convolutional Neural Network (CNN) ResNet architecture in building the automated FSL recognition model, with the goal of bridging the communication gap between the deaf community and the hearing majorities. In the experimentation, the dataset used are static images generated from a signer which gestured Filipino number signs which range from (0-9). Based on experimentation, the best-achieved performance is on fine-tuned ResNet-50 model which obtained a validation accuracy as high as 86.7% when the epoch value equals 15. For future work, real-time FSL recognition will be implemented and more data will be collected to enable recognition of Filipino alphabets, basic phrases, and common greetings. © 2021 ACM.

关键词： Convolutional neural networks

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Accelerating Non-Negative Matrix Factorization on Embedded FPGA with Hybrid Logarithmic Dot-Product Approximation

Accelerating Non-Negative Matrix Factorization on Embedded F...

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IEEE International symposium on Embedded Multicore Socs (MCSoC)

作者： Yizhi Chen Yarib Nevarez Zhonghai Lu Alberto Garcia-Ortiz School of Electrical Engineering and Computer Science KTH Royal Institute of Technology Stockholm Sweden Institute of Electrodynamics and Microelectronics (ITEM.ids) University of Bremen Bremen Germany

ISBN: (纸本)9781665465007

Non-negative matrix factorization (NMF) is an ef-fective method for dimensionality reduction and sparse decom-position. this method has been of great interest to the scien-tific community in applications including signal processing, data mining, compression, and pattern recognition. However, NMF implies elevated computational costs in terms of performance and energy consumption, which is inadequate for embedded applications. To overcome this limitation, we implement the vector dot-product with hybrid logarithmic approximation as a hardware optimization approach. this technique accelerates floating-point computation, reduces energy consumption, and preserves accuracy. To demonstrate our approach, we employ a design exploration flow using high-level synthesis on an embedded FPGA. Compared with software solutions on ARM CPU, this hardware implementation accelerates the overall computation to decompose matrix by $5.597\times$ and reduces energy consumption by $69.323\times$ . Log approximation NMF combined with KNN(k-nearest neighbors) has only 2.38% decreasing accuracy compared with the result of KNN processing the matrix after floating-point NMF on MNIST. Further on, compared with a dedicated floating-point accelerator, the logarithmic approximation approach achieves $3.718\times$ acceleration and $8.345\times$ energy reduction. Compared with the fixed-point approach, our approach has an accuracy degradation of 1.93% on MNIST and an accuracy amelioration of 28.2% on the FASHION MNIST data set without pre-knowledge of the data range. thus, our approach has better compatibility with the input data range.

关键词： Degradation Energy consumption Visualization Program processors Memory management Hardware Matrix decomposition

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Fulcrum: a Simplified Control and Access Mechanism toward Flexible and Practical In-situ Accelerators 26

Fulcrum: a Simplified Control and Access Mechanism toward Fl...

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26th IEEE International symposium on high performance computer architecture (HPCA)

作者： Lenjani, Marzieh Gonzalez, Patricia Sadredini, Elaheh Li, Shuangchen Xie, Yuan Akel, Ameen Eilert, Sean Stan, Mircea R. Skadron, Kevin Univ Virginia Charlottesville VA 22904 USA Univ Calif Santa Barbara Santa Barbara CA 93106 USA Micron Technol Inc Boise ID USA

ISBN: (纸本)9781728161495

In-situ approaches process data very close to the memory cells, in the row buffer of each subarray. this minimizes data movement costs and affords parallelism across subarrays. However, current in-situ approaches are limited to only row-wide bitwise (or few-bit) operations applied uniformly across the row buffer. they impose a significant overhead of multiple row activations for emulating 32-bit addition and multiplications using bitwise operations and cannot support operations with data dependencies or based on predicates. Moreover, with current peripheral logic, communication among subarrays is inefficient, and with typical data layouts, bits in a word are not physically adjacent. the key insight of this work is that in-situ, single-word ALUs outperform in-situ, parallel, row-wide, bitwise ALUs by reducing the number of row activations and enabling new operations and optimizations. Our proposed lightweight access and control mechanism, Fulcrum, sequentially feeds data into the single-word ALU and enables operations with data dependencies and operations based on a predicate. For algorithms that require communication among subarrays, we augment the peripheral logic with broadcasting capabilities and a previously-proposed method for low-cost inter-subarray data movement. the sequential processor also enables overlapping of broadcasting and computation, and reuniting bits that are physically adjacent. In order to realize true subarray-level parallelism, we introduce a lightweight column-selection mechanism through shifting one-hot encoded values. this technique enables independent column selection in each sub array. We integrate Fulcrum with Compress Express Link (CXL), a new interconnect standard. Fulcrum with one memory stack delivers on average (up to) 23.4 (76) x speedup over a server-class GPU, NVIDIA P100, with three stacks of HBM2 memory, (ii) 70 (228)x speedup per memory stack over the GPU, and (iii) 19 (178.9) x speedup per memory stack over an ideal model of

关键词： processing in memory (PIM) in-situ computing DRAM

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19th symposium on high performance computing Systems, WSCAD 2018

19th Symposium on High Performance Computing Systems, WSCAD ...

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19th symposium on high performance computing Systems, WSCAD 2018

ISBN: (纸本)9783030410490

the proceedings contain 12 papers. the special focus in this conference is on high performance computing Systems. the topics include: Evaluation and Mitigation of Timing Side-Channel Leakages on Multiple-Target Dynamic Binary Translators;A GPU-Based Parallel Reduction Implementation;evaluating Cache Line Behavior Predictors for Energy Efficient Processors;Automatic Minimization of Execution Budgets of SPITS Programs in AWS;analysis of Virtualized Congestion Control in Applications Based on Hadoop MapReduce;improving Oil and Gas Simulation performance Using thread and Data Mapping;SMCis: Scientific Applications Monitoring and Prediction for HPC Environments;video7 Extended architecture: Project Design and Statistical Analysis;Parallel Stream Processing with MPI for Video Analytics and Data Visualization;tangible Assets to Improve Research Quality: A Meta Analysis Case Study.

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Sargantana: A 1 GHz+ In-Order RISC-V Processor with SIMD Vector Extensions in 22nm FD-SOI

Sargantana: A 1 GHz+ In-Order RISC-V Processor with SIMD Vec...

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Euromicro symposium on Digital System Design

作者： Víctor Soria-Pardos Max Doblas Guillem López–Paradís Gerard Candón Narcís Rodas Xavier Carril Pau Fontova–Musté Neiel Leyva Santiago Marco-Sola Miquel Moretó Barcelona Supercomputing Center (BSC) Universitat Politècnica de Catalunya (UPC) Universidad Autònoma de Barcelona (UAB) Codasip

ISBN: (数字)9781665474047

ISBN: (纸本)9781665474054

the RISC-V open Instruction Set architecture (ISA) has proven to be a solid alternative to licensed ISAs. In the past 5 years, a plethora of industrial and academic cores and accelerators have been developed implementing this open ISA. In this paper, we present Sargantana, a 64-bit processor based on RISC-V that implements the RV64G ISA, a subset of the vector instructions extension (RVV 0.7.1), and custom application-specific instructions. Sargantana features a highly optimized 7-stage pipeline implementing out-of-order write-back, register renaming, and a non-blocking memory pipeline. Moreover, Sar-gantana features a Single Instruction Multiple Data (SIMD) unit that accelerates domain-specific applications. Sargantana achieves a 1.26 GHz frequency in the typical corner, and up to 1.69 GHz in the fast corner using 22nm FD-SOI commercial technology. As a result, Sargantana delivers a 1.77× higher Instructions Per Cycle (IPC) than our previous 5-stage in-order DVINO core, reaching 2.44 CoreMark/MHz. Our core design delivers comparable or even higher performance than other state-of-the-art academic cores performance under Autobench EEMBC benchmark suite. this way, Sargantana lays the foundations for future RISC-V based core designs able to meet industrial-class performance requirements for scientific, real-time, and high-performance computing applications.

关键词： Out of order Runtime high performance computing Pipelines computer architecture Benchmark testing Solids

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