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IEEE symposium on high-performance computer architecture

作者： B. Pratheek Neha Jawalkar Arkaprava Basu Indian Institute of Science

GPU (Graphics Processing Unit) architecture has evolved to accelerate parts of a single application at a time. Consequently, several aspects of its architecture, particularly the virtual memory, have embraced a shared-mostly design. this implicitly assumes that a single application and, thus, one address space is resident in the GPU at a time. However, recent trends, e.g., deployment of GPUs in the cloud, necessitate efficient multi-tenancy. Multi-tenancy is needed for sharing the physical resources of a large server-class GPU across multiple concurrent tenants (applications) for resource consolidation while ensuring fairness among the *** first quantify how different components of GPU's virtual memory can impede multi-tenancy. We show that shared page walkers are a key bottleneck under multi-tenancy. We, therefore, propose dynamic page walk stealing that enables soft partitioning of the shared pool of walkers- reducing destructive interference between the tenants while also aggregating resources where possible. Over today's design, we improve throughput by 37%, and weighted IPC by 15%, on average, over 45 workloads.

关键词： Cloud computing Graphics processing units Process control computer architecture Interference throughput Market research

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Design and Implementation of Dynamic Reconfiguration Based on Heterogeneous Arrow Control Platform

Design and Implementation of Dynamic Reconfiguration Based o...

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International Conference on Electronic Measurement and Instruments, ICEMI

作者： Ran Tao Gang Xiang Yue Luo Kun Tian Hui Li Zhaolei Wang Beijing Aerospace Automatic Control Research Institute Beijing China Beijing Inst. Of Electronic System Engineering Beijing China

ISBN: (纸本)9781665444927

Traditional rocket control computing platform use hardware redundancy more ways to promote the reliability, the same hardware redundancy of common cause failure, unable to cope with complex environment against the shortcomings, is proposed based on heterogeneous architecture arrows control platform, by using SOPC, FPGA and DSP three core components to build a new generation of control computing platform, has high reliability, strong adaptability to environment, etc. With SOPC as the core, the heterogeneous platform completes data transmission through high-speed serial transmission, supports dynamic logical reconstruction, and utilizes dynamic reconstruction technology to realize self-recovery under abnormal state. In this paper, the platform architecture, data transmission and synchronization methods, dynamic reconstruction strategy and control methods are described in detail. Finally, the correctness of the platform design is verified by experiments and simulations.

关键词： Rockets Instruments Redundancy computer architecture Hardware Reliability Data communication

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Automated Detection of Cybersecurity threats Using Generative Adversarial Networks (GANs)

Automated Detection of Cybersecurity Threats Using Generativ...

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Open Innovations Association (FRUCT), Conference of

作者： Salam Omar Alo Abeer Salim Jamil Mohammed Jabbar Hussein Mohammed K. H. Al-Dulaimi Sarmad Waleed Taha Anastasiia Khlaponina Alnoor University Nineveh Iraq Al Mansour University College Baghdad Iraq Al Hikma University College Baghdad Iraq Al-Rafidain University College Baghdad Iraq Al-Turath University Baghdad Iraq Kyiv National University of Construction and Architecture Kyiv Ukraine

ISBN: (数字)9789526524627

ISBN: (纸本)9798331507411

Introduction: Traditional network intrusion detection systems (NIDS) face significant challenges in detecting ever-evolving cyber-threats. With the evolution of cyber-attacks, comes a mounting requirement for predictive methods which are competent in identifying both familiar and unknown threats with an effective level of ***: this study is motivated to apply Generative Adversarial Networks (GAN) technology in NIDS for synthetic data generation, so when the NIDS use this technique generates high-quality fake samples which will tremendously increase its accuracy and decrease false positives. In this paper, we aim to evaluate the performance of GAN-boosted NIDS in different environments, such as novel obfuscated and adversarial ***: In this study, was developed and trained a GAN by large datasets like UNSW-NB15 and CICIDS2017 using the proposed methodology. the performance of the GAN model was compared with classical machine learning models — Support Vector Machines (SVM) and Random Forests (RF)— via various evaluation metrics such as detection accuracy, false positive rate, and robustness to attacks. Furthermore, expert interviews were included for the qualitative aspects of how practitioners felt about deploying GAN-enhanced NIDS in ***: Along with enhancing detection capabilities, the study will also explore the computational and operational effects of incorporating GAN into existing cybersecurity systems. Findings indicate that the GAN-based system enhances detection accuracy to 95.8% and reduces false positive rate to 2.4%. We additionally discuss the execution of these systems, the necessary deployment process, computing and real-time performance trade-offs, and offer guidance for maximizing resource utilization. the system displayed a performance better than of detecting novel and obfuscated attacks with an accuracy of 88.2%. It also showed resistance to adversarial attacks, keeping detection rates above 90% for various at

关键词： Training Support vector machines Accuracy Organizations Generative adversarial networks Robustness Resource management computer security Synthetic data Resilience

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REAL: Logic and Arithmetic Operations Embedded in RRAM for General-Purpose computing 15

REAL: Logic and Arithmetic Operations Embedded in RRAM for G...

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15th IEEE/ACM International symposium on Nanoscale architectures, NANOARCH 2019

作者： Xie, Lei Cai, Hao Yang, Jun Southeast University National ASIC Engineering Center China

ISBN: (纸本)9781728155203

As the need of data-intensive applications is growing, it is challenging to scale von Neumann architecture to meet this need, due to its unavoidable data movement between processors and memories. To address such a challenge, processing-inmemory architectures have been proposed which are implemented by either conventional or emerging memory technology. However, such architectures typically support a narrow range of operations;for instance, some of them only support logical operations such as AND, OR. Hence, it is hard to be applied into a wide spectrum of applications (e.g., some need arithmetic operations). Furthermore, some operations need to add additional CMOS logic or significantly modify standard memory array structures. this paper proposes a set of comprehensive logical and arithmetic operations that are primitive operations of today's computer instruction set and can be embedded into RRAM;they include seven bitwise logical operation and three arithmetic operations. In addition, a new multiplication algorithm is proposed to be easily embedded into RRAM. the evaluation shows that our proposal reduces the delay up to 46% using fewer or the same number of memristor devices as compared to the state-of-the-art. © 2019 IEEE.

关键词： RRAM

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Demo: A Multi-Perspective Video Streaming System with Privacy Preservation in Trauma Room

Demo: A Multi-Perspective Video Streaming System with Privac...

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IEEE/ACM symposium on Edge computing (SEC)

作者： Zhengyong Ren Yuxin Yang Kambiz Ghazinour Sara Bayramzadeh Qiang Guan Department of Computer Science Kent State University School of Science Health and Criminal Justice State University of New York at Canton College of Architecture and Environmental Design Kent State University

ISBN: (数字)9781665486118

ISBN: (纸本)9781665486125

More and more hospitals are now deploying mul-tiple cameras in trauma room for a multi-perspective remote observation. but video surveillance system can cause privacy breach by showing and storing sensitive information of patients and staff. We use OpenPose which is a state-of-the-art human body skeletons estimation framework to extract 18 human key skeleton points. For privacy preservation, we can apply the image obfuscation techniques to human heads, we also can use human skeleton to replace the human body in the truth background. we proposed a head detection method based on the 5 key points of each head output from OpenPose. We applied the st-gcn algorithm to recognize human actions, we propose a interactive algorithm for multiple cameras to recognize and trace the same person in different cameras, Based on multi-view action recognition for the same person, we can take action recognition accuracy to a high level. Our experiment results prove that our proposed technique has a high performance in privacy protection applications. Now we focus on the interactive algorithm for multiple cameras.

关键词： Head Image recognition Hospitals Estimation Streaming media Cameras Video surveillance

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DMA Medusa: A Vendor-Independent FPGA-Based architecture for 400 Gbps DMA Transfers

DMA Medusa: A Vendor-Independent FPGA-Based Architecture for...

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Annual IEEE symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Jan Kubálek Jakub Cabal Martin Špinler Radek Iša CESNET a.l.e Prague Czech Republic

ISBN: (纸本)9781665435550;9781665402538

FPGA accelerator cards are used for packet capture and monitoring in high-speed networks. With the 400G Ethernet technology, there is a need for an ability to transfer data to and from the host memory at the speed of 400Gbps. Currently available architectures (for example [1],[2],[3]) are limited to throughput up to 100Gbps and are therefore not suitable for this use *** paper presents a vendor-independent DMA architecture that is capable of scaling up to 400Gbps throughput in a single FPGA using two PCIe Gen4 ×16 slots bifurcated into four ×8 interfaces. this architecture is designed to support hundreds of independent DMA channels and supports one or more PCIe endpoints with different configurations. We also demonstrate the performance of the proposed DMA architecture using results measured on an accelerator card with Intel Stratix 10 DX FPGA.

关键词： high-speed networks computer architecture Ethernet throughput Field programmable gate arrays Monitoring

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基于Nginx负载均衡的大规模脑电信号处理集群架构设计与实现

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信息通信技术与政策 2025年第3期51卷 16-24页

作者：刘玉婷吴彤任祥辉中国电子科技集团公司第十五研究所北京100083

随着脑电信号处理技术在医疗、神经科学及人机交互领域的广泛应用,传统单机架构在高并发场景下存在计算资源受限、延迟高、稳定性差等问题。设计了一种基于Nginx负载均衡的脑电信号处理集群架构,通过反向代理技术将并发请求分配至分布... 详细信息

随着脑电信号处理技术在医疗、神经科学及人机交互领域的广泛应用,传统单机架构在高并发场景下存在计算资源受限、延迟高、稳定性差等问题。设计了一种基于Nginx负载均衡的脑电信号处理集群架构,通过反向代理技术将并发请求分配至分布式节点,结合标准化数据处理流程及统一集群入口,显著提升系统实时性、资源利用率与吞吐量。实验表明,在并发量为100~2000个的情况下,集群架构的平均响应时间与最小响应时间均有了显著优化,同时吞吐量也得到了大幅提升,且Nginx的IP访问控制策略有效拦截非法请求,保障数据安全。该架构通过动态负载均衡实现资源高效调度,为大规模神经数据处理提供技术支撑。未来可融合人工智能与边缘计算技术,拓展至复杂脑电分析场景,助力精准医疗与智能交互发展。

关键词： Nginx 负载均衡集群脑电信号处理安全访问

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Modified Dropout and Maxout based on the MNN for improving accuracy 15

Modified Dropout and Maxout based on the MNN for improving a...

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15th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2020

作者： Wang, Chao Zha, Xiaojing Xia, Yinshui Faculty of Electrical Engineering and Computer Science Ningbo University Ningbo315211 China

ISBN: (纸本)9781728162355

Memristor crossbar array is an emerged architecture suitable for matrix computation. Memristor based neural networks (MNN) address the speed and energy efficiency issues in computing hardware. However, there are still a lot of problems with memristor, and the limited size of memristor crossbar resulting in the accuracy of the MNN is lower than conventional neural networks (CNNs). In this paper, a modified Dropout and Maxout based MNN for improving the accuracy of the MNN is proposed. A three-layer memristor based multilayer Perceptron (MLP) in 64*128 crossbar is built to perform MNIST image recognition. the experiment results demonstrate that the in-situ training of the MLP achieves a high accuracy near 96.5% with Dropout and Maxout. © 2020 IEEE.

关键词： Memristors

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HEDAcc: FPGA-based Accelerator for high-order Epistasis Detection

HEDAcc: FPGA-based Accelerator for High-order Epistasis Dete...

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Annual IEEE symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Gaspar Ribeiro Nuno Neves Sergio Santander-Jiménez Aleksandar Ilic INESC-ID Instituto Superior Técnico Universidade de Lisboa Portugal Instituto de Telecomunicações Lisboa Portugal University of Extremadura Spain

the manifestation of important genetic diseases is often a consequence of the interactions between Single Nucleotide Polymorphisms (SNPs), also known as epistasis. Detecting epistasis for high-order interactions results in a huge computational complexity, as the number of SNP combinations to be evaluated exponentially grows with the interaction order. To address this challenge, state-of-the-art exhaustive search-based methods for epistasis detection rely on GPUs and FPGAs to provide high-performance solutions tailored for a specific order (second and rarely third-order interactions) and/or specific data-set sizes. In this paper, a novel parameterizable architecture is proposed that enables the deployment of FPGA-based accelerators targeting any order of interactions and any data-set size. By relying on a set of algorithmic and architecture optimizations, the proposed accelerator showed to outperform current FPGA accelerators for second and third-order interactions by as much as 4.6× and 9.5×, respectively. the proposed solution also showed comparable performance to current GPGPU third-order implementations, while consuming up to 8.2× less energy. Finally, the proposed architecture allowed for the implementation of a fourth-order epistasis detection accelerator in an FPGA platform.

关键词： Scalability computer architecture Genetics Energy efficiency Computational complexity Field programmable gate arrays Optimization

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Comparison of Direct and Indirect Networks for high-performance FPGA Clusters 16th

Comparison of Direct and Indirect Networks for High-Performa...

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16th International symposium on Applied Reconfigurable computing

作者： Mondigo, Antoniette Ueno, Tomohiro Sano, Kentaro Takizawa, Hiroyuki Tohoku Univ Grad Sch Informat Sci Sendai Miyagi Japan RIKEN Res Team Ctr Computat Sci Kobe Hyogo Japan Tohoku Univ Cybersci Ctr Sendai Miyagi Japan

ISBN: (纸本)9783030445331;9783030445348

As field programmable gate arrays (FPGAs) become a favorable choice in exploring new computing architectures for the post-Moore era, a flexible network architecture for scalable FPGA clusters becomes increasingly important in high performance computing (HPC). In this paper, we introduce a scalable platform of indirectly-connected FPGAs, where its Ethernet-switching network allows flexibly customized inter-FPGA connectivity. However, for certain applications such as in stream computing, it is necessary to establish a connection-oriented datapath with backpressure between FPGAs. Due to the lack of physical back-pressure channel in the network, we utilized our existing credit-based network protocol with flow control to provide receiver FPGA awareness and tailored it to minimize overall communication overhead for the proposed framework. To know its performance characteristics, we implemented necessary data transfer hardware on Intel Arria 10 FPGAs, modeled and obtained its communication performance, and compared it to a direct network. Results show that our proposed indirect framework achieves approximately 3% higher effective network bandwidth than our existing direct inter-FPGA network, which demonstrates good performance and scalability for large HPC applications.

关键词： FPGA cluster Indirect network Direct network Flow control Scalability Flexibility

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