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NV-BSP: A Burst I/O storage pool based on NVMe SSDs 13th

NV-BSP: A Burst I/O storage pool based on NVMe SSDs

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13th Conference on Advanced computer architecture, ACA 2020

作者： Li, Qiong Wei, Dengping Gao, Wenqiang Xie, Xuchao College of Computer National University of Defense Technology Changsha China Beijing Memblaze Technology Co. Ltd. Beijing China

ISBN: (纸本)9789811581342

the high-performance computing (HPC) systems built for future exascale computing, big data analytics, and artificial intelligence applications raise an ever-increasing demand for high-performance and highly reliable storage systems. In recent years, as Non-Volatile Memory express (NVMe) Solid-State Drives (SSDs) are deployed in HPC storage systems, the performance penalty paid for the legacy I/O software stack and storage network architecture turns out to be non-trivial. In this paper, we propose NV-BSP, an NVMe SSD-based Burst I/O Storage Pool, to leverage the performance benefits of NVMe SSD, NVMe over Fabrics (NVMeoF) Protocol, and Remote Direct Memory Access (RDMA) networks in HPC storage systems. NV-BSP disaggregates NVMe SSDs from HPC compute nodes to enhance the scalability of HPC storage systems, employs fine-grained chunks rather than physical NVMe SSD devices as the RAID-based data protection areas, and exploits high concurrent I/O processing model to alleviate the performance overhead from lock contentions and context switches in critical I/O path. We implement NV-BSP in Linux and evaluate it with synthetic FIO benchmarks. Our experimental results show that NV-BSP achieves scalable system performance as the number of NVMe SSD and CPU core increases and obtains much better system performance compared with the built-in MD-RAID in Linux. Compared with node-local SSDs in HPC, NV-BSP provides a full system solution of storage disaggregation, delivers comparable performance, and significantly improves system reliability. © Springer Nature Singapore Pte Ltd 2020.

关键词： Network architecture

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the What's Next Intermittent computing architecture 25

The What's Next Intermittent Computing Architecture

引用

25th IEEE International symposium on high performance computer architecture (HPCA)

作者： Ganesan, Karthik San Miguel, Joshua Jerger, Natalie Enright Univ Toronto Toronto ON Canada Univ Wisconsin Madison WI 53706 USA

ISBN: (纸本)9781728114446

Energy-harvesting devices operate under extremely tight energy constraints. Ensuring forward progress under frequent power outages is paramount. Applications running on these devices are typically amenable to approximation, offering new opportunities to provide better forward progress between power outages. We propose What's Next (WN), a set of anytime approximation techniques for energy harvesting: subword pipelining, subword vectorization and skim points. Skim points fundamentally decouple the checkpoint location from the recovery location upon a power outage. Ultimately, WN transforms processing on energy-harvesting devices from all-or-nothing to as-is computing. We enable an approximate (yet acceptable) result sooner and proceed to the next task when power is restored rather than resume processing from a checkpoint to yield the perfect output. WN yields speedups of 2.26x and 3.02x on non-volatile and checkpoint-based volatile processors, while still producing high-quality outputs.

关键词： energy harvesting intermittent computing approximate computing

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A Fast Cloud Detection based on Improved 2D OTSU with Zynq SoC

A Fast Cloud Detection based on Improved 2D OTSU with Zynq S...

引用

International Conference on Electronic Measurement and Instruments, ICEMI

作者： Ximing Yu Zihao Liu Yu Peng Harbin Institute of Technology Harbin China Harbin Nosean Test and Control Technology Co. Ltd. Harbin China

ISBN: (纸本)9781665444927

Cloud detection plays an important role in pre-processing of the remote sensing image to locate the potential area of the target fast and improve the detection efficiency. Although the cloud detection performance is not ideal in the complex ground, such as bright buildings on the ground, the OTSU based method is used to achieve fast cloud detection onboard for the single scenarios due to the simple calculation process. However, due to the sequential processing capabilities provided by the onboard processors, the processing complexity of OTSU increases significantly as the image size increasing. In this article, a fast cloud detection method based on the improved 2D OTSU with Zynq system on chip (SoC) is proposed. the improved 2D OTSU method is utilized for cloud detection to provide the capability to distinguish highlight buildings on the ground. And the parallel processing for key process in the 2D OTSU provided by the field programmable gate array in Zynq SoC to improve computing efficiency. Compared with the 1D OTSU, experimental results show that the proposed method could achieve high detection precision. Meanwhile, the processing time is about 0.18s for a 512×512 size image, which is a relative fast speed for the practical application.

关键词： Program processors Instruments Buildings computer architecture Interference Parallel processing Logic gates

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An Evaluation of the Communication performance of MEC-Dependent Services in 5G Networks

An Evaluation of the Communication Performance of MEC-Depend...

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IEEE International symposium on Network computing and Applications

作者： Matthias Frei thomas Deinlein Reinhard German Anatoli Djanatliev Fraunhofer Institute for Integrated Circuits IIS Erlangen Germany Computer Networks and Communication Systems University of Erlangen-Nürnberg Germany

ISBN: (纸本)9781665495516

Remote infrastructure is going to assist prospective mobile services, but requires reliable and efficient network resources. Multi-Access Edge computing (MEC) and cellular networks starting from the fifth generation (5G) are two of the enabling technologies that are necessary to meet strong service level requirements. When service constraints cannot be met all the time, the service may be malfunctioning or even impossible. Impact factors can be user mobility, the network architecture, flexible topology changes, and orchestration decisions. We discuss these challenges while considering the technical integration possibilities. Mainly, we develop a MEC network simulation with a 5G cellular network and user mobility. Our aim is to respect and focus on network conditions for MEC-dependent services and to generate performance indicators for an example task offloading application. We vary the available 5G resources, the number of involved MEC nodes, and application-level behavior like the offloaded task complexity, i.e., computing duration and offloading interval. Additionally, we examine connection-oriented and stateless communication. Our results show that a dense MEC network is able to improve round-trip time (RTT) and jitter in high-load situations and can have a positive impact on service availability and reliability.

关键词： Cellular networks Multi-access edge computing 5G mobile communication Network architecture Jitter Topology Complexity theory

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Mocarabe: high-performance Time-Multiplexed Overlays for FPGAs

Mocarabe: High-Performance Time-Multiplexed Overlays for FPG...

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Annual IEEE symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Frederick Tombs Alireza Mellat Nachiket Kapre University of Waterloo Ontario Canada

Coarse-grained reconfigurable array (CGRA) overlays can improve dataflow kernel throughput by an order of magnitude over Vivado HLS. this is possible with a combination of carefully floorplanned high-frequency (645-768 MHz) design and a scalable, communication-aware compiler. Our 2D torus CGRA architecture supports versatile processing element (PE) functionality and a configurable number of communication channels to match application demands. Compared to recent FPGA overlays like CGRA-ME's ADRES and HyCUBE implementations, our design operates at 1.8-3.4× faster clock frequency, while scaling to an orders-of-magnitude larger array size of 19×69 on Xilinx Alveo U280. Our communication-aware compiler targets HLS objectives such as initiation interval (II) and minimizes communication cost using an integer linear programming (ILP) formulation. Unlike SDC schedulers in FPGA HLS tools, we treat data movement as a first-class citizen by encoding the space and time resources communication network of the overlay in the ILP formulation. Given the same constraints on operational resources as Vivado HLS, we can retain our target II and achieve up to 9.2× higher frequency. Our ILP scheduler outperforms a PathFinder space-time router implementation in quality of result by up to nearly 2×.

关键词： Program processors computer architecture Tools Integer linear programming throughput Encoding Communication networks

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EdgeIso: Effective performance Isolation for Edge Devices 34

EdgeIso: Effective Performance Isolation for Edge Devices

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34th IEEE International Parallel and Distributed Processing symposium (IPDPS)

作者： Nam, Yoonsung Choi, Yongjun Yoo, Byeonghun Eom, Hyeonsang Son, Yongseok Seoul Natl Univ Dept Comp Sci & Engn Seoul South Korea Chung Ang Univ Sch Comp Sci & Engn Seoul South Korea

ISBN: (纸本)9781728168760

Edges enable cloud services to be provided at low-latency and efficiently reduce the amount of transferred data by placing latency-critical tasks close to users. However, multi-tasking results in resource contention on edge devices, making it challenging to meet the service level objectives (SLOs) of tasks. Compared to the clouds, edges have relatively limited resources, but their tasks are required to meet a higher level of SLOs than clouds. Furthermore, modern edge devices equipped with additional accelerators (e.g., GPU) may worsen the resource contention due to the edge's integrated architecture, sharing the memory bandwidth between CPUs and accelerators. To address these challenges, we present EdgeIso, a light-weight scheduler that dynamically isolates the performance of tasks on edges. EdgeIso periodically monitors the resource contention and mitigates the contention to meet the SLOs of tasks by efficiently enforcing several isolation techniques (e.g., DVFS and core allocation) in an incremental manner. Moreover, it detects the changes of task executions or offered loads for tasks, thus handling high load fluctuations adaptively. We implement EdgeIso as a user-level scheduler on the Linux integrates into an NVIDIA Jetson TX2. Our experimental results show that EdgeIso improves the performance of the low-latency tasks significantly while improving resource efficiency compared with both the offloading and reservation scheme used in clouds.

关键词： edge computing resource management performance isolation latency-critical workloads

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Analyzing Memory Access Traces of Deep Learning Workloads for Efficient Memory Management

Analyzing Memory Access Traces of Deep Learning Workloads fo...

引用

IEEE International symposium on Information (IT) in Medicine and Education, ITME

作者： Jeongha Lee Hyokyung Bahn Dept. of Computer Engineering Ewha University Seoul Republic of Korea

Due to the recent advances in artificial intelligence (AI) and high-performance computing technologies, deep learning is actively used in various application domains of the fourth industrial revolution. Since the data size of deep learning increasingly grows, analyzing the memory reference characteristics of AI workloads becomes important. In this article, we analyze the memory access traces of deep learning workloads consisting of text and image data. Specifically, we analyze read and write operations separately for instruction and data memory accesses. Based on our analysis, we find out the following characteristics that are quite different to memory access traces of conventional desktop workloads. First, when comparing instruction and data accesses, instruction access accounts for a little portion of memory accesses in deep learning workloads, which is quite different from traditional workloads. Specifically, instruction access accounts for 1-3.3% in deep learning workloads while 15-30% in traditional workloads. Second, when comparing read and write accesses, write access accounts for 64-80%, which is also different to traditional workloads where write accounts for 6-55%. third, although write access accounts for the majority of memory accesses, it exhibits the low access skewness. Specifically, the Zipf parameter of write access is about 0.3, and the parameter is smaller in text workloads than image workloads. Fourth, in predicting re-reference likelihood, recency ranking is important in instruction and data read accesses, but frequency ranking is necessary in write accesses for accurate estimation. We expect that the characterization study in this article will guide for managing memory systems of deep learning workloads.

关键词： Deep learning high performance computing Memory management Education Estimation Focusing Frequency estimation

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CoAP + DTLS: A Comprehensive Overview of Cryptographic performance on an IOT Scenario 15

CoAP + DTLS: A Comprehensive Overview of Cryptographic Perfo...

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15th IEEE Sensors Applications symposium, SAS 2020

作者： Westphall, Johann Loffi, Leandro Westphall, Carla Merkle Everson Martina, Jean Federal University of Santa Catarina Computer Science Graduate Program Florianópolis Brazil

ISBN: (纸本)9781728148427

Internet of things (IoT) and Fog computing applications deal with sensitive data and need security tools to be protected against attackers. CoAP (Constrained Application Protocol), combined with DTLS (Datagram Transport Layer Security), provides security to IoT/Fog applications. However, processing times need to be considered when using this combination due to IoT/Fog environment constraints. Our work presents a CoAP with DTLS application and analyzes the performance of Raspberry Pi 3 during DTLS handshakes, data encryption and data decryption with the most relevant cipher suites. the performance of confirmable and non-confirmable CoAP POST requests is also measured and discussed in our work. We discovered that cipher suites that use RSA as an authentication method on handshake are slightly faster than cipher suites that use ECDSA, while symmetric key encryption with AES256(128)GCM are 40% faster than AES256(128) default modes. Our study also suggests CoAP modifications to obtain higher efficiency, and it might help future IoT/Fog application developers to understand CoAP and DTLS union, providing an application example and performance metrics. © 2020 IEEE.

关键词： Internet of things

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Pliant: Leveraging Approximation to Improve Datacenter Resource Efficiency 25

Pliant: Leveraging Approximation to Improve Datacenter Resou...

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25th IEEE International symposium on high performance computer architecture (HPCA)

作者： Kulkarni, Neeraj Qi, Feng Delimitrou, Christina Cornell Univ Ithaca NY 14853 USA

ISBN: (纸本)9781728114446

Cloud multi-tenancy is typically constrained to a single interactive service colocated with one or more batch, low-priority services, whose performance can be sacrificed when deemed necessary. Approximate computing applications offer the opportunity to enable tighter colocation among multiple applications whose performance is important. We present Pliant, a lightweight cloud runtime that leverages the ability of approximate computing applications to tolerate some loss in their output quality to boost the utilization of shared servers. During periods of high resource contention, Pliant employs incremental and interference-aware approximation to reduce contention in shared resources, and prevent QoS violations for co-scheduled interactive, latency-critical services. We evaluate Pliant across different interactive and approximate computing applications, and show that it preserves QoS for all co-scheduled workloads, while incurring a 2.1% loss in output quality, on average.

关键词： Quality of service Approximate computing Runtime Cloud computing Interference Optimization Synchronization

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Building a lightweight container-based experimental platform for hpc education 10th

Building a lightweight container-based experimental platform...

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10th International symposium on Parallel architectures, Algorithms and Programming, PAAP 2019

作者： Wang, Zelong Wu, Di Luo, Zhenxiao Du, Yunfei School of Data and Computer Science Sun Yat-sen University Guangzhou China Guangdong Key Laboratory of Big Data Analysis and Processing Guangzhou510006 China National Supercomputer Center in Guangzhou Guangzhou China

HPC (high performance computing) is of great significance due to its excellent performance in computing acceleration. However, unlike other techniques in computer science, learning HPC requires advanced computing resources such as large-scale clusters which directly increase the cost of study for students. To help students to learn HPC programming easily, we design and develop a lightweight container-based experimental platform to provide students with easily accessible and customizable HPC practice environments. In our platform, we integrate multiple practical functional modules for students, teachers, and administrators respectively. It is convenient for a user to access high-performance computing resources via a web portal, use highly customizable basic environments and have nice graphical hands-on interactive HPC learning experiences from our platform. © Springer Nature Singapore Pte Ltd. 2020.

关键词： Containers

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