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16th International symposium on Applied Reconfigurable computing, ARC 2020

16th International Symposium on Applied Reconfigurable Compu...

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16th International symposium on Applied Reconfigurable computing, ARC 2020

ISBN: (纸本)9783030445331

the proceedings contain 29 papers. the special focus in this conference is on Applied Reconfigurable computing. the topics include: Accelerating a Classic 3D Video Game on Heterogeneous Reconfigurable MPSoCs;Cross-layer CNN Approximations for Hardware Implementation;technique for Vendor and Device Agnostic Hardware Area-Time Estimation;Resource Efficient Dynamic Voltage and Frequency Scaling on Xilinx FPGAs;RISC-V Based MPSoC Design Exploration for FPGAs: Area, Power and performance;a Modular Software Library for Effective high Level Synthesis of Convolutional Neural Networks;HLS-Based Acceleration Framework for Deep Convolutional Neural Networks;FPGA-Based Computational Fluid Dynamics Simulation architecture via high-Level Synthesis Design Method;high-Level Synthesis in Implementing and Benchmarking Number theoretic Transform in Lattice-Based Post-Quantum Cryptography Using Software/Hardware Codesign;judiciously Spreading Approximation Among Arithmetic Components with Top-Down Inexact Hardware Design;exploring fpga Optimizations to Compute Sparse Numerical Linear Algebra Kernels;A CGRA Definition Framework for Dataflow Applications;Implementing CNNs Using a Linear Array of Full Mesh CGRAs;A Block-Based Systolic Array on an HBM2 FPGA for DNA Sequence Alignment;Comparison of Direct and Indirect Networks for high-performance FPGA Clusters;A Parameterisable FPGA-Tailored architecture for YOLOv3-Tiny;Hardware/Algorithm Co-optimization for Fully-Parallelized Compact Decision Tree Ensembles on FPGAs;stocNoC: Accelerating Stochastic Models through Reconfigurable Network on Chip architectures;Implementation of FM-Index Based Pattern Search on a Multi-FPGA System;Reconfigurable Accelerator for On-Board SAR Imaging Using the Backprojection Algorithm;Optimising Operator Sets for Analytical Database Processing on FPGAs;automated Toolchain for Enhanced Productivity in Reconfigurable Multi-accelerator Systems;Chisel Usecase: Designing General Matrix Multiply for FPGA.

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HPC, Cloud and Big-Data Convergent architectures: the LEXIS Approach 13th

HPC, Cloud and Big-Data Convergent Architectures: The LEXIS ...

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13th International Conference on Complex, Intelligent, and Software Intensive Systems (CISIS)

作者： Scionti, Alberto Martinovic, Jan Terzo, Olivier Walter, Etienne Levrier, Marc Hachinger, Stephan Magarielli, Donato Goubier, thierry Louise, Stephane Parodi, Antonio Murphy, Sean D'Amico, Carmine Ciccia, Simone Danovaro, Emanuele Lagasio, Martina Donnat, Frederic Golasowski, Martin Quintino, Tiago Hawkes, James Martinovic, Tomas Riha, Lubomir Slaninova, Katerina Serra, Stefano Peveri, Roberto LINKS Fdn Adv Comp & Applicat Turin Italy VSB Tech Univ Ostrava IT4Innovat 17 Listopadu 15-2172 Ostrava 70800 Czech Republic ATOS Paris France Leibniz Supercomp Ctr LRZ Garching Germany Cyclops Labs Zurich Switzerland CEA List Paris France AvioAero Turin Italy European Ctr Medium Range Weather Forecasts ECMWF Reading Berks England CIMA Res Fdn Savona Italy Outpost24 Nice France TESEO Turin Italy

ISBN: (纸本)9783030223540;9783030223533

high performance computing (HPC) infrastructures (also referred to as supercomputing infrastructures) are at the basis of modern scientific discoveries, and allow engineers to greatly optimize their designs. the large amount of data (Big-Data) to be treated during simulations is pushing HPC managers to introduce more heterogeneity in their architectures, ranging from different processor families to specialized hardware devices (e.g., GPU computing, many-cores, FPGAs). Furthermore, there is also a growing demand for providing access to supercomputing resources as in common public Clouds. All these three elements (i.e., HPC resources, Big-Data, Cloud) make "converged" approaches mandatory to address challenges emerging in scientific and technical domains. the LEXIS project aims to design and set up an innovative computing architecture, where HPC, Cloud and Big-Data solutions are closely integrated to respond to the demands of performance, flexibility and scalability. To this end, the LEXIS architecture leverages on three main distinctive elements: (i) resources of supercomputing centers (geographically located in Europe) which are seamlessly managed in a federated fashion;(ii) an integrated data storage subsystem, which supports Big-Data ingestion and processing;and (iii) a web portal to enable users to easily get access to computing resources and manage their workloads. In addition, the LEXIS architecture will make use of innovative hardware solutions, such as burst buffers and FPGA accelerators, as well as a flexible orchestration software. To demonstrate the capabilities of the devised converged architecture, LEXIS will assess its performance, scalability and flexibility in different contexts. To this end, three computational highly demanding pilot test-beds have been selected as representative of application domains that will take advantage of the advanced LEXIS architecture: (i) Aeronautics - Computational Fluid Dynamics simulations of complex turbo-machinery and

关键词： computer architecture

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Bit Prudent In-Cache Acceleration of Deep Convolutional Neural Networks 25

Bit Prudent In-Cache Acceleration of Deep Convolutional Neur...

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25th IEEE International symposium on high performance computer architecture (HPCA)

作者： Wang, Xiaowei Yu, Jiecao Augustine, Charles Iyer, Ravi Das, Reetuparna Univ Michigan Ann Arbor MI 48109 USA Intel Corp Santa Clara CA 95051 USA

ISBN: (纸本)9781728114446

We propose Bit Prudent In-Cache Acceleration of Deep Convolutional Neural Networks - an in-SRAM architecture for accelerating Convolutional Neural Network (CNN) inference by leveraging network redundancy and massive parallelism. the network redundancy is exploited in two ways. First, we prune and fine-tune the trained network model and develop two distinct methods - coalescing and overlapping to run inferences efficiently with sparse models. Second, we propose an architecture for network models with a reduced bit width by leveraging bit-serial computation. Our proposed architecture achieves a 17.7x/3.7x speedup over server class CPU/GPU, and a 1.6x speedup compared to the relevant in-cache accelerator, with 2% area overhead each processor die, and no loss on top-1 accuracy for AlexNet. With a relaxed accuracy limit, our tunable architecture achieves higher speedups.

关键词： In-Memory computing Cache Neural Network Pruning Low Precision Neural Network

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FPGA-based high-performance Parallel architecture for Homomorphic computing on Encrypted Data 25

FPGA-based High-Performance Parallel Architecture for Homomo...

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25th IEEE International symposium on high performance computer architecture (HPCA)

作者： Roy, Sujoy Sinha Turan, Furkan Jarvinen, Kimmo Vercauteren, Frederik Verbauwhede, Ingrid Katholieke Univ Leuven Imec COSIC Leuven Belgium Univ Birmingham Sch Comp Sci Birmingham W Midlands England Univ Helsinki Dept Comp Sci Helsinki Finland

ISBN: (纸本)9781728114446

Homomorphic encryption is a tool that enables computation on encrypted data and thus has applications in privacy-preserving cloud computing. though conceptually amazing, implementation of homomorphic encryption is very challenging and typically software implementations on general purpose computers are extremely slow. In this paper we present our year long effort to design a domain specific architecture in a heterogeneous Arm+FPGA platform to accelerate homomorphic computing on encrypted data. We design a custom co-processor for the computationally expensive operations of the well-known Fan-Vercauteren (FV) homomorphic encryption scheme on the FPGA, and make the Arm processor a server for executing different homomorphic applications in the cloud, using this FPGA-based co-processor. We use the most recent arithmetic and algorithmic optimization techniques and perform design-space exploration on different levels of the implementation hierarchy. In particular we apply circuit-level and block-level pipeline strategies to boost the clock frequency and increase the throughput respectively. To reduce computation latency, we use parallel processing at all levels. Starting from the highly optimized building blocks, we gradually build our multi-core multi-processor architecture for computing. We implemented and tested our optimized domain specific programmable architecture on a single Xilinx Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit. At 200 MHz FPGA-clock, our implementation achieves over 13x speedup with respect to a highly optimized software implementation of the FV homomorphic encryption scheme on an Intel i5 processor running at 1.8 GHz.

关键词： Cloud computing privacy in cloud computing homomorphic encryption FV homomorphic encryption latticebased cryptography polynomial multiplication number theoretic transform domain specific accelerator hardware accelerator

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Improving the performance of collective communication for the on-chip network 10th

Improving the performance of collective communication for th...

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10th International symposium on Parallel architectures, Algorithms and Programming, PAAP 2019

作者： Chu, Slo-Li Ho, Wen-Chih Jiang, Yi-Jie Department of Information and Computer Engineering Chung Yuan Christian University Chung Li District Taoyuan City Taiwan

Efficiently executing the massively parallel applications has become an important goal of developing a modern high-performance multicore computer. In these parallel programs, the collective communication among these cores consume a large portion of inter-core communication. In order to prevent the collective communication from the performance bottleneck of the on-chip network, this paper proposed a new on-chip network, call Hierarchy Self Similar Cubic (HSSC), to reduce the latency of the collective communication on the multicore system. the corresponding transmission mechanisms and packet scheduling mechanism are proposed to analyze and grouping the packets, and determine a suitable transmission mechanism for each packet group on-the-fly. the experiments compare the performance of several on-chip networks. the advantages of proposed transmission mechanisms and packet scheduling mechanism are also discussed. © Springer Nature Singapore Pte Ltd. 2020.

关键词： Software architecture

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Body Motion Analysis for Golf Swing Evaluation 15th

Body Motion Analysis for Golf Swing Evaluation

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15th International symposium on Visual computing, ISVC 2020

作者： Liu, Jen Jui Newman, Jacob Lee, Dah-Jye Brigham Young University ProvoUT84602 United States

ISBN: (纸本)9783030645557

A golf swing requires full-body coordination and much practice to perform the complex motion precisely and consistently. the force from the golfer’s full-body movement on the club and the trajectory of the swing are the main determinants of swing quality. In this research, we introduce a unique motion analysis method to evaluate the quality of golf swing. the primary goal is to evaluate how close the user’s swing is to a reference ideal swing. We use 17 skeleton points to evaluate the resemblance and report a score ranging from 0 to 10. this evaluation result can be used as real-time feedback to improve player performance. Using this real-time feedback system repeatedly, the player will be able to train their muscle memory to improve their swing consistency. We created our dataset from a professional golf instructor including good and bad swings. Our result demonstrates that such a machine learning-based approach is feasible and has great potential to be adopted as a low-cost but efficient tool to improve swing quality and consistency. © 2020, Springer Nature Switzerland AG.

关键词： computer vision

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Opportunities of cloud high performance computing for SMES – A meta-analysis 15

Opportunities of cloud high performance computing for SMES ...

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15th International symposium on Operations Research, SOR 2019

作者： Gašperlin, Blaž Ilijaš, Tomi Borštnar, Mirjana Kljajić University of Maribor Faculty of Organizational Sciences Kidričeva 55a Kranj Slovenia Arctur d.o.o. Industrijska cesta 15 Nova Gorica Slovenia

ISBN: (纸本)9789616165556

high performance computing (HPC) is used to solve complex scientific, engineering and societal problems. Due to its high cost, it is mainly reserved for the large companies and institutes. However, with HPC services offered in the cloud it can become an interesting technology for small and medium sized enterprises (SMEs). the problem lies in the lack of awareness of benefits and availability of resources. We have conducted a meta-analysis of the results of CloudFlow, Fortissimo and SesameNet projects. Results suggest that SMEs can benefit using cloud HPC services, but there are also challenges that need to be addressed. © International symposium on Operations Research, SOR *** right reserved.

关键词： high-performance cloud computing high-performance computing Manufacturing SMEs

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Systematic Optimization of Image Processing Pipelines Using GPUs 15th

Systematic Optimization of Image Processing Pipelines Using ...

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15th International symposium on Visual computing, ISVC 2020

作者： Roch, Peter Shahbaz Nejad, Bijan Handte, Marcus Marrón, Pedro José University of Duisburg-Essen Essen Germany

ISBN: (纸本)9783030645588

Real-time computer vision systems require fast and efficient image processing pipelines. Experiments have shown that GPUs are highly suited for image processing operations, since many tasks can be processed in parallel. However, calling GPU-accelerated functions requires uploading the input parameters to the GPU’s memory, calling the function itself, and downloading the result afterwards. In addition, since not all functions benefit from an increase in parallelism, many pipelines cannot be implemented exclusively using GPU functions. As a result, the optimization of pipelines requires a careful analysis of the achievable function speedup and the cost of copying data. In this paper, we first define a mathematical model to estimate the performance of an image processing pipeline. thereafter, we present a number of micro-benchmarks gathered using OpenCV which we use to validate the model and which quantify the cost and benefits for different classes of functions. Our experiments show that comparing the function speedup without considering the time for copying can overestimate the achievable performance gain of GPU acceleration by a factor of two. Finally, we present a tool that analyzes the possible combinations of CPU and GPU function implementations for a given pipeline and computes the most efficient composition. By using the tool on their target hardware, developers can easily apply our model to optimize their application performance systematically. © 2020, Springer Nature Switzerland AG.

关键词： computer vision

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Phase-Based Tasks Scheduling in Data Centers Powered Exclusively by Renewable Energy 31

Phase-Based Tasks Scheduling in Data Centers Powered Exclusi...

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31st International symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Caux, Stephane Renaud-Goud, Paul Rostirolla, Gustavo Stolf, Patricia Univ Toulouse IRIT F-31062 Toulouse France Univ Toulouse Laplace UMR5213 INPT UPSCNRS Toulouse France

ISBN: (纸本)9781728141947

Data centers are considered nowadays as the factories of the digital age, being currently responsible for consuming more energy than the entire United Kingdom. On the other side, the global total capacity of renewable power increases continuously. the combination of these two factors calls for new approaches in designing data centers powered only by renewable energy sources. Our work focuses on task scheduling optimization under a power envelope, and on the way to handle power starvation, i.e. when the available power does not provide sufficient resources to execute a given workload. To do so we utilize the concept of task degradation through cross-correlation to find where to place the tasks in order to reduce the data center profit degradation. the results show that our algorithm could obtain more than 34% increase in profit when compared to algorithms from the literature, while fulfilling the power profile and resources constraints.

关键词： Scheduling Cloud computing Renewable Energy Mixed Workload

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Apache spark streaming, kafka and harmonicio: a performance benchmark and architecture comparison for enterprise and scientific computing 2nd

Apache spark streaming, kafka and harmonicio: a performance ...

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2nd International symposium on Benchmarking, Measuring, and Optimization, Bench 2019

作者： Blamey, Ben Hellander, Andreas Toor, Salman Department of Information Technology Division of Scientific Computing Uppsala University Uppsala Sweden

ISBN: (纸本)9783030495558

Many scientific computing applications generate streams where message sizes exceed one megabyte, in contrast with smaller message sizes in enterprise contexts (order kilobytes, often XML or JSON). Furthermore, the processing cost of messages in scientific computing applications are usually an order of magnitude higher than in typical enterprise applications. Frameworks such as Apache Spark offer high throughput processing of streams with such ‘enterprise’ characteristics, as well as scalability, with high resilience and many other desirable features. Motivated by the development of near real-time image processing pipelines for roboticized microscopy, we evaluate the suitability of Apache Spark for streams more typical of scientific computing applications, those with large message sizes (up to 10 MB), and heavy per-message CPU load, under typical stream integrations. For comparison, we benchmark a P2P stream processing framework, HarmonicIO, developed in-house. Our study reveals a complex interplay of performance trade-offs, revealing the boundaries of good performance for each framework and integration over a wide domain of application loads. Based on these results, we suggest which are likely to offer good performance for a given load. Broadly, the advantages of Spark’s rich features makes its performance sensitive to message size in particular, whereas the simplicity of HarmonicIO offers more robust performance, and better CPU utilization. © Springer Nature Switzerland AG 2020.

关键词： Benchmarking

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