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检索条件"任意字段=15th Symposium on Computer Architecture and High Performance Computing"

共 4639 条记录，以下是921-930 订阅

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Nonconvex Regularization for Network Slimming: Compressing CNNs Even More 15th

Nonconvex Regularization for Network Slimming: Compressing C...

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15th International symposium on Visual computing, ISVC 2020

作者： Bui, Kevin Park, Fredrick Zhang, Shuai Qi, Yingyong Xin, Jack Department of Mathematics University of California Irvine IrvineCA92697 United States Department of Mathematics and Computer Science Whittier College WhittierCA90602 United States

ISBN: (纸本)9783030645557

In the last decade, convolutional neural networks (CNNs) have evolved to become the dominant models for various computer vision tasks, but they cannot be deployed in low-memory devices due to its high memory requirement and computational cost. One popular, straightforward approach to compressing CNNs is network slimming, which imposes an 1 penalty on the channel-associated scaling factors in the batch normalization layers during training. In this way, channels with low scaling factors are identified to be insignificant and are pruned in the models. In this paper, we propose replacing the 1 penalty with the p and transformed 1 (T 1 ) penalties since these nonconvex penalties outperformed 1 in yielding sparser satisfactory solutions in various compressed sensing problems. In our numerical experiments, we demonstrate network slimming with p and T 1 penalties on VGGNet and Densenet trained on CIFAR 10/100. the results demonstrate that the nonconvex penalties compress CNNs better than 1. In addition, T 1 preserves the model accuracy after channel pruning, and 1 / 2, 3 / 4 yield compressed models with similar accuracies as 1 after retraining. © 2020, Springer Nature Switzerland AG.

关键词： Convolutional neural networks

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Reliability Evaluation of Mixed-Precision architectures 25

Reliability Evaluation of Mixed-Precision Architectures

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25th IEEE International symposium on high performance computer architecture (HPCA)

作者： dos Santos, Fernando Fernandes Lunardi, Caio Oliveira, Daniel Libano, Fabiano Rech, Paolo Univ Fed Rio Grande do Sul Inst Informat Porto Alegre RS Brazil

ISBN: (纸本)9781728114446

Novel computing architectures offer the possibility to execute float point operations with different precisions. the execution of reduced precision operationsis likely to reduce both the execution time and power consumption. However, the application's error rate and the device's reliability can also be impacted by these precision changes. In this paper, we study the impact of data and operation precision changes on the reliability of modern architectures. We consider Xilinx Field-Programmable Gate-Arrays (FPGA), Intel Xeon Phis, and NVIDIA Graphics Processing Units (GPUs) executing a set of codes implemented in double, single, and half-precision IEEE754-compliant float point data. On FPGAs, the reduced area and performance improvements brought by reduced precision operations increase reliability. On Xeon Phis the compiler biases significantly double- and single-precision instructions execution. this raises the drawback of increasing single-precision error rates when compared to double-precision. NVIDIA GPUs make use of dedicated mixed-precision cores, which draw nontrivial effects on the device reliability. In general, on GPUs half-precision allows a higher number of executions to be correctly completed before experimenting a failure. Finally, we also evaluate how transient faults impact the output correctness. Our study shows that for most applications faults in a single or half-precision data or operation are more likely to significantly modify the output value than errors in double-precision data.

关键词： computer architecture

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Aggregate Authentication for Massive Internet of things in 5G Networks 4th

Aggregate Authentication for Massive Internet of Things in 5...

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4th International symposium on Mobile Internet Security, MobiSec 2019

作者： Syalim, Amril Anggorojati, Bayu Baek, Joonsang Gerbi, Daniel You, Ilsun Faculty of Computer Science University of Indonesia Depok Indonesia School of Computing and Information Technology University of Wollongong WollongongNSW Australia Department of Information Security Engineering Soonchunhyang University Asan-si Korea Republic of

ISBN: (纸本)9789811596087

Massive Internet of things (IoT) applications are characterized by a massive number of low-powered devices with small data storage. In those applications, authentication is very important to guarantee the origin of data produced by each device. With such characteristics, the authentication scheme needs to have small footprint and low complexity computation. Likewise, the number of authentication signaling needs to be significantly reduced to accommodate massive amount of IoT devices trying to connect to the network simultaneously, which is similar to Denial of Service (DoS) attacks. In 3GPP TR 33.899 V1.3.0, an architecture of the authentication system that consists of the aggregation nodes and the authenticators is proposed. the aggregation nodes receive the authenticated data from the devices and send the aggregated authenticated data to the authenticators. In this article, we discuss the possibility to implement more efficient authentication scheme for a massive Internet of things (IoT) applications enabled in 5G networks. In particular, we analyze the performance of the system using some signature aggregation methods and identify the main research challenges in this area. © 2020, Springer Nature Singapore Pte Ltd.

关键词： Authentication

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Large-scale and high-throughput QR Decomposition on an FPGA 27

Large-scale and High-throughput QR Decomposition on an FPGA

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27th IEEE Annual International symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Lee, Dajung Hagiescu, Andrei Pritsker, Dan Intel Corp San Diego CA 92131 USA Intel Corp Toronto ON Canada

ISBN: (纸本)9781728111315

the QR decomposition, also called the QR factorization, is one of core matrix operations that is used to solve a linear inverse/solver problem. We develop a high-throughput QR decomposition for large-scale matrices on FPGA. We refine the modified Gram-Schmit QRD algorithm into a hardware-friendly algorithmic flow and describe the core architecture in C. We synthesize our code using an Intel FPGA SDK for OpenCL targeting an Intel Arria 10 FPGA device.

关键词： Field programmable gate arrays Matrix decomposition performance evaluation throughput computer architecture Hardware Graphics processing units

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Efficient architecture for Integral Image Computation on Heterogeneous FPGAs 15

Efficient Architecture for Integral Image Computation on Het...

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15th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)

作者： Spagnolo, Fanny Corsonello, Pasquale Perri, Stefania Univ Calabria Dept Informat Modeling Elect & Syst Engn Arcavacata Di Rende Italy Univ Calabria Dept Mech Energy & Management Engn Arcavacata Di Rende Italy

ISBN: (纸本)9781728135496

Integral image (IIM) is an intermediate image representation, employed in several computer vision algorithms. Although only simple arithmetic operations are required to compute an IIM, the total number of additions increases quadratically with the input image size. For this reason, the design of hardware architectures able to accelerate the IIM computation receives a great deal of attention. Unfortunately, existing solutions are not appropriate for the integration within high-performance embedded systems, which are currently realized within modern heterogeneous CPU-FPGA System on Chips (SoCs). In this paper, we present a novel hardware architecture for accelerating the IIM computation. the proposed design outperforms existing competitors by parallelizing operations along both rows and columns of the input image. Experiments, conducted on a Zynq-7000 XC7Z020 SoC, demonstrate that the novel accelerator achieves a speed per computation unit up to 124 times higher than prior works, saving more than 70Mbits of on-chip memory resources for 1920x1080 frame resolutions.

关键词： Integral image parallel computing embedded vision systems FPGA SoC

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Optimizing Stochastic computing for Low Latency Inference of Convolutional Neural Networks 20

Optimizing Stochastic Computing for Low Latency Inference of...

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39th IEEE/ACM International Conference On computer Aided Design (ICCAD)

作者： Chen, Zhiyuan Ma, Yufei Wang, Zhongfeng Nanjing Univ Sch Elect Sci & Engn Nanjing Peoples R China

ISBN: (纸本)9781665423243

the appealing property of low area, low power, flexible precision, and high bit error tolerance has made Stochastic computing (SC) a promising alternative to conventional binary arithmetic for many computation intensive tasks, e.g., convolutional neural networks (CNNs). However, to relieve the intrinsic fluctuation noise in SC, long bit stream is normally required in SC-based CNN accelerators to achieve satisfactory accuracy, which leads to extortionate latency. Although the bit parallel structure of a SC multiplier has been proposed to reduce latency, the resulting extra overhead still considerably degrade the overall efficiency of SC. In this paper, we optimize both the micro-architecture of SC multiply-and-accumulate (MAC) unit and the overall acceleration scheme of CNN accelerator to favor SC. An optimized and scalable SC-MAC unit, which fully utilizes the property of low-discrepancy bit stream, is proposed with adjustable parameters to reduce the latency with minor area increase. For the overall accelerator, the parallel dimensions of SC-based MAC array are extended to reuse hardware resources and improve throughput, since the judiciously chosen loop unrolling strategy can better benefit SC operations. the proposed CNN accelerator with extended SC-MAC array is synthesized and demonstrated using TSMC 28nm CMOS on several representative CNNs, which gains 2x performance speedup, 2.8x energy savings and 15% area reduction compared to state-of-the-art SC based CNN accelerator.

关键词： Stochastic systems

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An FPGA-based computing Infrastructure Tailored to Efficiently Scaffold Genome Sequences 27

An FPGA-based Computing Infrastructure Tailored to Efficient...

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27th IEEE Annual International symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Zeni, Alberto Crespi, Matteo Di Tucci, Lorenzo Santambrogio, Marco D. Politecn Milan Dipartimento Elettron Informaz & Bioingn Milan Italy

ISBN: (纸本)9781728111315

In the current years broad access to genomic data is leading to improve the understanding and prevention of human diseases as never before. De-novo genome assembly, represents a main obstacle to perform the analysis on a large scale, as it is one of the most time-consuming phases of the genome analysis. In this paper, we present a scalable, high performance and energy efficient architecture for the alignment step of SSPACE, a state of the art tool used to perform scaffolding also in case of de-novo assembly. the final architecture is able to achieve up to 9.83x speedup in performance when compared to the software version of Bowtie, a state of the art tool used by SSPACE to perform the alignment.

关键词： Genomics Bioinformatics computer architecture Field programmable gate arrays Software algorithms Software Tools

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An efficient system for grammatical error correction on mobile devices

An efficient system for grammatical error correction on mobi...

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International Conference on Semantic computing

作者： Sourabh Vasant Gothe Sushant Dogra Mritunjai Chandra Chandramouli Sanchi Barath Raj Kandur Raja Samsung R&D Institute Bangalore Karnataka India

ISBN: (数字)9781728188997

ISBN: (纸本)9781728189000

As per the analysis by lemongrad, among 1,121 million English speakers globally, there are 743 million nonnative and 378 million native English speakers (7:3 Ratio). With the increasing number of non-native English speakers, there has been a lot of ongoing research on automated Grammatical Error Correction (GEC). Despite the advances in this field, a GEC system for mobile devices with a low model size, quick inference time and high accuracy is a pressing need. Existing solutions for mobile devices are server-based, which poses a potential risk of data privacy to the user. To this end, we propose an on-device hybrid system which consists of various components, such as preprocessor with spell-checker, Deep Neural Network (DNN) model, N-gram language model, rule-corrector for GEC. User's input text is passed through the proposed system sequentially to get the grammatically correct, contextually enhanced and profanity checked output sentence. Our novel system is at par with other available models for mobile devices with inference time of 95ms, module size of 11.6 MB and F 0.5 score of 52.3 on CoNLL-2014 [1] (test).

关键词： Data privacy Semantics computer architecture Pressing Mobile handsets User experience Error correction

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AI Playground: Unreal Engine-Based Data Ablation Tool for Deep Learning 15th

AI Playground: Unreal Engine-Based Data Ablation Tool for De...

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15th International symposium on Visual computing, ISVC 2020

作者： Mousavi, Mehdi Khanal, Aashis Estrada, Rolando Department of Computer Science Georgia State University AtlantaGA30303 United States

ISBN: (纸本)9783030645588

Machine learning requires data, but acquiring and labeling real-world data is challenging, expensive, and time-consuming. More importantly, it is nearly impossible to alter real data post-acquisition (e.g., change the illumination of a room), making it very difficult to measure how specific properties of the data affect performance. In this paper, we present AI Playground (AIP), an open-source, Unreal Engine-based tool for generating and labeling virtual image data. With AIP, it is trivial to capture the same image under different conditions (e.g., fidelity, lighting, etc.) and with different ground truths (e.g., depth or surface normal values). AIP is easily extendable and can be used with or without code. To validate our proposed tool, we generated eight datasets of otherwise identical but varying lighting and fidelity conditions. We then trained deep neural networks to predict (1) depth values, (2) surface normals, or (3) object labels and assessed each network’s intra- and cross-dataset performance. Among other insights, we verified that sensitivity to different settings is problem-dependent. We confirmed the findings of other studies that segmentation models are very sensitive to fidelity, but we also found that they are just as sensitive to lighting. In contrast, depth and normal estimation models seem to be less sensitive to fidelity or lighting, and more sensitive to the structure of the image. Finally, we tested our trained depth-estimation networks on two real-world datasets and obtained results comparable to training on real data alone, confirming that our virtual environments are realistic enough for real-world tasks. © 2020, Springer Nature Switzerland AG.

关键词： Lighting

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highway Traffic Classification for the Perception Level of Situation Awareness 15th

Highway Traffic Classification for the Perception Level of S...

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15th International symposium on Visual computing, ISVC 2020

作者： Nine, Julkar Manoharan, Shanmugapriyan Sapkota, Manoj Saleh, Shadi Hardt, Wolfram Department of Computer Engineering Technische Universität Chemnitz Straße der Nationen 62 Chemnitz09111 Germany Embedded Systems Technische Universität Chemnitz Straße der Nationen 62 Chemnitz09111 Germany Automotive Software Engineering Technische Universität Chemnitz Straße der Nationen 62 Chemnitz09111 Germany

ISBN: (纸本)9783030645588

the automotive industry is rapidly moving towards the highest level of autonomy. However, one of the major challenges for highly autonomous vehicles is the differentiation between driving modes according to different driving situations. Different driving zones have different driving safety regulations. For example, German traffic regulations require a higher degree of safety measurements for highway driving. therefore, a classification of the different driving scenarios on a highway is necessary to regulate these safety assessments. this paper presents a novel vision-based approach to the classification of German highway driving scenarios. We develop three different and precise algorithms utilizing image processing and machine learning approaches to recognize speed signs, traffic lights, and highway traffic signs. Based on the results of these algorithms, a weight-based classification process is performed, which determines the current driving situation either as a highway driving mode or not. the main goal of this research work is to maintain and to ensure the high safety specifications required for the German highway. Finally, the result of this classification process is provided as an extracted driving scenario-based feature on the perceptual level of a system known as situation awareness to provide a high level of driving safety. this study was realized on a custom-made hardware unit called "CE-Box", which was developed at the Department of computer Engineering at TU Chemnitz as an automotive test solution for testing automotive software applications on an embedded hardware unit. © 2020, Springer Nature Switzerland AG.

关键词： Machine learning

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