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信息与电脑 2024年第13期36卷 113-116页

作者：邹博四川省第十五建筑有限公司四川南充637000

随着互联网信息技术的持续更新与应用,现代建筑行业受到剧烈冲击,其中机电安装行业受到的冲击尤为严重。《2016—2020年建筑业信息化发展纲要》明确提出,现代建筑也应向高信息化水平发展,积极推广并应用建筑信息模型(Building Informati... 详细信息

随着互联网信息技术的持续更新与应用,现代建筑行业受到剧烈冲击,其中机电安装行业受到的冲击尤为严重。《2016—2020年建筑业信息化发展纲要》明确提出,现代建筑也应向高信息化水平发展,积极推广并应用建筑信息模型(Building Information Modeling,BIM)、移动通讯、大数据、物联网、云计算、人工智能等新型信息技术,以此推动建造手段的智能化发展。因此,智能建造成为现代建筑业发展转型的重要目标,而依托智能建造推动机电安装行业高质量发展则是其中最关键的内容之一。本文在此背景下展开研究,通过阐述机电安装行业中推广智能建造技术的意义,总结了机电安装行业在智能建造时面临的问题和采取应对的对策。

关键词：智能建造机电安装行业信息技术

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Overscan Detection in Digitized Analog Films by Precise Sprocket Hole Segmentation 15th

Overscan Detection in Digitized Analog Films by Precise Spro...

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15th International symposium on Visual computing, ISVC 2020

作者： Helm, Daniel Kampel, Martin Institute of Visual Computing and Human-Centered Technology Computer Vision Lab TU Wien Vienna Austria

ISBN: (纸本)9783030645557

Automatic video analysis is explored in order to understand and interpret real-world scenes automatically. For digitized historical analog films, this process is influenced by the video quality, video composition or scan artifacts called overscanning. the main aim of this paper is to find the Sprocket Holes (SH) in digitized analog film frames in order to drop unwanted overscan areas and extract the correct scaled final frame content which includes the most significant frame information. the outcome of this investigation proposes a precise overscan detection pipeline which combines the advantages of supervised segmentation networks such as DeepLabV3 with an unsupervised Gaussian Mixture Model for fine-grained segmentation based on histogram features. Furthermore, this exploration demonstrates the strength of using low-level backbone features in combination with low-cost CNN architectures like SqueezeNet in terms of inference runtime and segmentation performance. Moreover, a pipeline for creating photo-realistic frame samples to build a self-generated dataset is introduced and used in the training and validation phase. this dataset consists of 15000 image-mask pairs including synthetically created and deformed SHs with respect to the exact film reel layout geometry. Finally, the approach is evaluated by using real-world historical film frames including original SHs and deformations such as scratches, cracks or wet splices. the proposed approach reaches a Mean Intersection over Union (mIoU) score of 0.9509 (@threshold: 0.5) as well as a Dice Coefficient of 0.974 (@threshold: 0.5) and outperforms state-of-the-art solutions. Finally, we provide full access to our source code as well as the self-generated dataset in order to promote further research on digitized analog film analysis and fine-grained object segmentation. © 2020, Springer Nature Switzerland AG.

关键词： Sprockets

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A Review of the theory and Method for New Developed Feedforward Neural Networks 15th

A Review of the Theory and Method for New Developed Feedforw...

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15th International Conference on Natural Computation, Fuzzy Systems and Knowledge Discovery, ICNC-FSKD 2019, co-located with the 5th International Conference on Harmony Search, Soft computing and Applications, ICHSA 2019

作者： Zhang, Daiyuan College of Computer Nanjing University of Posts and Telecommunications Nanjing China

ISBN: (纸本)9783030324551

Two new theories and methods of feedforward neural network developed in recent years are systematically reviewed. they are Algebraic Algorithm of feedforward neural network and Spline Weight Function Algorithm of feedforward neural network. the network structure, basic theory and algorithm, and basic performance of the two networks are described. the algebraic algorithm of feedforward neural network can get the global optimum, but BP algorithm is difficult to get the global optimum. Algebraic algorithm has high accuracy and fast training speed. In engineering application, the algebraic algorithm gives the calculation formula of accurately determining the number of hidden layer neurons, but the BP algorithm does not give such an accurate formula. However, algebraic algorithm, like traditional BP algorithm, obtains constant weights, which is difficult to reflect the information of training samples. the spline weight function algorithm of feedforward neural network not only retains the advantages of algebraic algorithm, but also overcomes its shortcomings, so that the weight of trained neural network is a function of input sample (called weight function), which is composed of spline function, not a constant of traditional method. the trained weight function can extract useful information features from the trained samples. the topological structure of the spline weighted neural network is very simple, and the number of its neurons is independent of the number of samples, which is equal to the number of input and output nodes. the calculation speed is fast. Moreover, with the increase of the number of samples, the generalization ability of the network is also improving. © Springer Nature Switzerland AG, 2020.

关键词： Feedforward neural networks

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A Light-Weight Monocular Depth Estimation with Edge-Guided Occlusion Fading Reduction 15th

A Light-Weight Monocular Depth Estimation with Edge-Guided O...

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15th International symposium on Visual computing, ISVC 2020

作者： Peng, Kuo-Shiuan Ditzler, Gregory Rozenblit, Jerzy Department of Electrical and Computer Engineering University of Arizona TucsonAZ85721 United States Department of Surgery University of Arizona TucsonAZ85721 United States

ISBN: (纸本)9783030645588

Self-supervised monocular depth estimation methods suffer occlusion fading, which is a result of a lack of supervision by the ground truth pixels. A recent work introduced a post-processing method to reduce occlusion fading;however, the results have a severe halo effect. this work proposes a novel edge-guided post-processing method that reduces occlusion fading for self-supervised monocular depth estimation. We also introduce Atrous Spatial Pyramid Pooling with Forward-Path (ASPPF) into the network to reduce computational costs and improve inference performance. the proposed ASPPF-based network is lighter, faster, and better than current depth estimation networks. Our light-weight network only needs 7.6 million parameters and can achieve up to 67 frames per second for 256×512 inputs using a single nVIDIA GTX1080 GPU. the proposed network also outperforms the current state-of-the-art methods on the KITTI benchmark. the ASPPF-based network and edge-guided post-processing produces better results, both quantitatively and qualitatively than the competitors. © 2020, Springer Nature Switzerland AG.

关键词： Processing

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high Precision, high performance FPGA Adders 27

High Precision, High Performance FPGA Adders

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27th IEEE Annual International symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Langhammer, Martin Pasca, Bogdan Baeckler, Gregg Intel Corp Santa Clara CA 95051 USA

ISBN: (纸本)9781728111315

FPGAs are now being commonly used in the datacenter as smart Network Interface Cards (NICs), with cryptography as one of the strategic application areas. Public key cryptography algorithms in particular require arithmetic with thousands of bits of precision. Even an operation as simple as addition can be difficult for the FPGA when dealing with large integers, because of the high resource count and high latency needed to achieve usable performance levels with known methods. this paper examines the architecture and implementation of high-performance integer adders on FPGAs for widths ranging from 1024 to 8192 bits, in both single-instance and many-core chip-filling configurations. For chip-filling designs the routing impact of these wide busses are assessed, as they often have an impact outside the immediate locality of the structures. the architectures presented in this work show 1 to 2 orders magnitude reduction in the area-latency product over commonly used approaches. Routing congestion is managed, with near 100% logic efficiency (packing) for the adder function. performance for these largely automatically placed designs are approximately the same as for carefully floor-planned non-arithmetic applications. In one example design, we show a 2048 bit adder in 5021 ALMs, with a latency of 6 clock cycles, at 628 MHz in a Stratix 10 E-2 device.

关键词： Adders Field programmable gate arrays Routing Pipeline processing performance evaluation Pipelines computer architecture

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Sketch-Inspector: A Deep Mixture Model for high-Quality Sketch Generation of Cats 15th

Sketch-Inspector: A Deep Mixture Model for High-Quality Sket...

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15th International symposium on Visual computing, ISVC 2020

作者： Pang, Yunkui Pan, Zhiqing Sun, Ruiyang Wang, Shuchong University of Southern California Los AngelesCA United States Sun Yat-sen University Guangzhou China University of Waterloo Waterloo Canada Michigan State University East LansingMI United States

ISBN: (纸本)9783030645557

With the involvement of artificial intelligence (AI), sketches can be automatically generated under certain topics. Even though breakthroughs have been made in previous studies in this area, a relatively high proportion of the generated figures are too abstract to recognize, which illustrates that AIs fail to learn the general pattern of the target object when drawing. this paper posits that supervising the process of stroke generation can lead to a more accurate sketch interpretation. Based on that, a sketch generating system with an assistant convolutional neural network (CNN) predictor to suggest the shape of the next stroke is presented in this paper. In addition, a CNN-based discriminator is introduced to judge the recognizability of the end product. Since the base-line model is ineffective at generating multi-class sketches, we restrict the model to produce one category. Because the image of a cat is easy to identify, we consider cat sketches selected from the QuickDraw data set. this paper compares the proposed model with the original Sketch-RNN on 75K human-drawn cat sketches. the result indicates that our model produces sketches with higher quality than human’s sketches. © 2020, Springer Nature Switzerland AG.

关键词： Drawing (graphics)

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Anomaly Detection in high performance computers: A Vicinity Perspective 18

Anomaly Detection in High Performance Computers: A Vicinity ...

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18th International symposium on Parallel and Distributed computing (ISPDC)

作者： Ghiasvand, Siavash Ciorba, Florina M. Tech Univ Dresden Dresden Germany Univ Basel Basel Switzerland

ISBN: (纸本)9781728138015

In response to the demand for higher computational power, the number of computing nodes in high performance computers (HPC) increases rapidly. Exascale HPC systems are expected to arrive by 2020. With drastic increase in the number of HPC system components, it is expected to observe a sudden increase in the number of failures which, consequently, poses a threat to the continuous operation of the HPC systems. Detecting failures as early as possible and, ideally, predicting them, is a necessary step to avoid interruptions in HPC systems operation. Anomaly detection is a well-known general purpose approach for failure detection, in computing systems. the majority of existing methods are designed for specific architectures, require adjustments on the computing systems hardware and software, need excessive information, or pose a threat to users' and systems' privacy. this work proposes a node failure detection mechanism based on a vicinity-based statistical anomaly detection approach using passively collected and anonymized system log entries. Application of the proposed approach on system logs collected over 8 months indicates an anomaly detection precision between 62% to 81%.

关键词： Anomaly detection computer architecture Hardware Correlation Resource management Bridges Graphics processing units

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面向目标检测的卷积神经网络优化方法

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高技术通讯 2022年第3期32卷 227-238页

作者：张志超王剑章隆兵肖俊华计算机体系结构国家重点实验室(中国科学院计算技术研究所) 北京100190 中国科学院计算技术研究所北京100190 中国科学院大学北京100049 中国电子科技集团公司第十五研究所北京100083

针对星载等功耗受限平台下遥感影像目标检测存在的高准确率、低功耗以及高吞吐量等要求,本文提出了一种面向目标检测的现场可编程门阵列(FPGA)卷积神经网络(CNN)优化方法。采用数据流调度技术以及基于乘法矩阵与前向加法链的卷积计算阵... 详细信息

针对星载等功耗受限平台下遥感影像目标检测存在的高准确率、低功耗以及高吞吐量等要求,本文提出了一种面向目标检测的现场可编程门阵列(FPGA)卷积神经网络(CNN)优化方法。采用数据流调度技术以及基于乘法矩阵与前向加法链的卷积计算阵列设计对浮点卷积神经网络模型进行加速。利用该方法在FPGA开发板上实现了浮点卷积目标检测网络,在应用中达到了与原模型一致的准确率,平均准确率为97.59%,吞吐量达到了Titan X的22倍。与同类的FPGA加速浮点卷积方法对比,该方法的吞吐量以及能效比达到了最优。实验数据表明,该方案突破了浮点卷积加速的线速吞吐难点,解决了应用中存在的功耗、准确率以及吞吐量三者制衡的问题。

关键词：卷积神经网络(CNN) 现场可编程门阵列(FPGA) 数据流调度目标检测加速

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Analysis and Optimization of Pipelined Broadcast Algorithms on Gigabit Ethernet and InfiniBand Networks 15

Analysis and Optimization of Pipelined Broadcast Algorithms ...

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15th International Asian School-Seminar on Optimization Problems of Complex Systems (OPCS)

作者： Kurnosov, Mikhail Berlizov, Daniil Tkacheva, Tatiana Tokmasheva, Elizaveta Siberian State Univ Telecommun & Informat Sci Novosibirsk Russia

ISBN: (纸本)9781728129860

theoretical and experimental analysis of MPI_Bcast algortihms is presented. the optimal tree degrees and segment sizes for pipelined versions of algorithms are obtained. Algorithms were investigated according to their implementation in the Open MPI library. theoretical results are consistent with experiments on a computer cluster with Gigabit Ethernet and InfiniBand communication networks.

关键词： broadcast MPI parallel programming high-performance computing

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On the Hardware Implementation performance, of Face Recognition Techniques, for Digital Forensics 7th

On the Hardware Implementation Performance, of Face Recognit...

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7th International symposium on Security in computing and Communications, SSCC 2019

作者： Pantopoulou, Maria Sklavos, Nicolas Ognjanovic, Ivana SCYTALE Group Computer Engineering and Informatics Department University of Patras Patras Greece University of Donja Gorica Podgorica Montenegro

ISBN: (纸本)9789811548246

As face recognition systems constitute a very useful tool in the sector of Digital Forensics, they should provide accurate and fast results. Although several software implementations for face recognition exist, they are unable to achieve high recognition rate in reasonable time, due to the complex and numerous needed calculations. As a result, there is an on-going research in low-cost hardware implementations, especially based on Field Programmable Gate Arrays (FPGAs), in order to reduce the processing time and the false alarm identification rate. In this work, we introduce the fundamental of algorithms, for face recognition, such as Principal Components Analysis (PCA), and its modified methods, as well as the Local Binary Pattern (LBP). these approaches are applied in different architectures, and alternative FPGA implementations are introduced. We also present implementation synthesis results, based on the recognition time and the allocated hardware resources. © Springer Nature Singapore Pte Ltd. 2020.

关键词： Face recognition

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