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11th International symposium on Intelligence Computation and Applications, ISICA 2019

作者： Zhang, Qing Jiao, Ruwang Zeng, Sanyou Zeng, Zhigao School of Computer Science Huanggang Normal University Huanggang438000 China School of Mechanical Engineering and Electronic Information China University of Geosciences Wuhan430074 China College of Computer Hunan University of Technology ZhuzhouHunan412007 China

ISBN: (纸本)9789811555763

this paper proposes a decomposition-based dynamic multi-objective evolutionary algorithm for addressing global optimization problems. In the proposed method, the niche count function is regarded as an additional objective to maintain the population diversity. the niche count function is controlled by niche radius. the niche radius is dynamically reduced from a large value to zero, which can provide a tradeoff between exploration and exploitation. In each generation, the proposed algorithm decomposes the transformed bi-objective optimization problem into a number of simple bi-objective subproblems, and then solving these bi-objective subproblems in a collaborative way. Experiments have been conducted on benchmark test instances and compared with four state-of-art algorithms. the experimental results have demonstrated its effectiveness in solving complex global optimization problems. © 2020, Springer Nature Singapore Pte Ltd.

关键词： Global optimization

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high-performance Two-stage Face Recognition Algorithm for Reduced Illumination Effect

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SENSORS AND MATERIALS 2019年第9期31卷 2771-2776页

作者： Yeh, Cheng-Yu Chen, Chien-Fu Lin, Chun-Cheng Natl Chin Yi Univ Technol Dept Elect Engn 57Sect 2Zhongshan Rd Taichung 41170 Taiwan

Face recognition, which is a method of identifying a person in a digital image, is widely applied to biometric-based authentication systems. A significant decrease in recognition rate is caused by extracted features that are affected by illumination. In an attempt to resolve this problem, in this paper, we present a two-stage algorithm, namely, a local binary pattern (LBP) followed by the algorithm Fisherface. As the first step of this work, a face image is converted to an LBP, which is then projected onto a low-dimensional feature space using Fisherface for subsequent classification and recognition. As a result, the outperformance of this work is demonstrated by a recognition rate of up to 96.45%, a figure far beyond 67.97% using the LBP histogram (LBPH), 84.69% using Fisherface, and 93.09% using the support vector machine (SVM) algorithm.

关键词： face recognition local binary pattern (LBP) LBP histogram (LBPH) Fisherface principal component analysis (PCA) linear discriminant analysis (LDA)

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HyPar: Towards Hybrid Parallelism for Deep Learning Accelerator Array 25

HyPar: Towards Hybrid Parallelism for Deep Learning Accelera...

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25th IEEE International symposium on high performance computer architecture (HPCA)

作者： Song, Linghao Mao, Jiachen Zhuo, Youwei Qian, Xuehai Li, Hai Chen, Yiran Duke Univ Durham NC 27706 USA Univ Southern Calif Los Angeles CA 90089 USA

ISBN: (纸本)9781728114446

With the rise of artificial intelligence in recent years, Deep Neural Networks (DNNs) have been widely used in many domains. To achieve high performance and energy efficiency, hardware acceleration (especially inference) of DNNs is intensively studied both in academia and industry. However, we still face two challenges: large DNN models and datasets, which incur frequent off-chip memory accesses;and the training of DNNs, which is not well-explored in recent accelerator designs. To truly provide high throughput and energy efficient acceleration for the training of deep and large models, we inevitably need to use multiple accelerators to explore the coarse-grain parallelism, compared to the fine-grain parallelism inside a layer considered in most of the existing architectures. It poses the key research question to seek the best organization of computation and dataflow among accelerators. In this paper, we propose a solution HYPAR to determine layer-wise parallelism for deep neural network training with an array of DNN accelerators. HYPAR partitions the feature map tensors (input and output), the kernel tensors, the gradient tensors, and the error tensors for the DNN accelerators. A partition constitutes the choice of parallelism for weighted layers. the optimization target is to search a partition that minimizes the total communication during training a complete DNN. To solve this problem, we propose a communication model to explain the source and amount of communications. then, we use a hierarchical layer-wise dynamic programming method to search for the partition for each layer. HYPAR is practical: the time complexity for the partition search in HYPAR is linear. We apply this method in an HMC-based DNN training architecture to minimize data movement. We evaluate HYPAR with ten DNN models from classic Lenet to large-size model VGGs, and the number of weighted layers of these models range from four to nineteen. Our evaluation finds that: the default Model Parallelism

关键词： Parallel processing Training Data models Neural networks computer architecture Acceleration

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A Driver Guidance System to Support the Stationary Wireless Charging of Electric Vehicles 15th

A Driver Guidance System to Support the Stationary Wireless ...

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15th International symposium on Visual computing, ISVC 2020

作者： Shahbaz Nejad, Bijan Roch, Peter Handte, Marcus Marrón, Pedro José University of Duisburg-Essen Essen Germany

ISBN: (纸本)9783030645588

Air pollution is a problem in many cities. Although it is possible to mitigate this problem by replacing combustion with electric engines, at the time of writing, electric vehicles are still a rarity in European cities. Reasons for not buying an electric vehicle are not only the high purchase costs but also the uncomfortable initiation of the charging process. A more convenient alternative is wireless charging, which is enabled by integrating an induction plate into the floor and installing a charging interface at the vehicle. To maximize efficiency, the vehicle’s charging interface must be positioned accurately above the induction plate which is integrated into the floor. Since the driver cannot perceive the region below the vehicle, it is difficult to precisely align the position of the charging interface by maneuvering the vehicle. In this paper, we first discuss the requirements for driver guidance systems that help drivers to accurately position their vehicle and thus, enables them to maximize the charging efficiency. thereafter, we present a prototypical implementation of such a system. To minimize the deployment cost for charging station operators, our prototype uses an inexpensive off-the-shelf camera system to localize the vehicles that are approaching the station. To simplify the retrofitting of existing vehicles, the prototype uses a smartphone app to generate navigation visualizations. To validate the approach, we present experiments indicating that, despite its low cost, the prototype can technically achieve the necessary precision. © 2020, Springer Nature Switzerland AG.

关键词： computer vision

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Coarse-to-Fine Object Tracking Using Deep Features and Correlation Filters 15th

Coarse-to-Fine Object Tracking Using Deep Features and Corre...

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15th International symposium on Visual computing, ISVC 2020

作者： Zgaren, Ahmed Bouachir, Wassim Ksantini, Riadh Department of Science and Technology TELUQ University Montreal Canada Department of Computer Science University of Bahrain Zallaq Bahrain

ISBN: (纸本)9783030645557

During the last years, deep learning trackers achieved stimulating results while bringing interesting ideas to solve the tracking problem. this progress is mainly due to the use of learned deep features obtained by training deep convolutional neural networks (CNNs) on large image databases. But since CNNs were originally developed for image classification, appearance modeling provided by their deep layers might be not enough discriminative for the tracking task. In fact, such features represent high-level information, that is more related to object category than to a specific instance of the object. Motivated by this observation, and by the fact that discriminative correlation filters (DCFs) may provide a complimentary low-level information, we present a novel tracking algorithm taking advantage of both approaches. We formulate the tracking task as a two-stage procedure. First, we exploit the generalization ability of deep features to coarsely estimate target translation, while ensuring invariance to appearance change. then, we capitalize on the discriminative power of correlation filters to precisely localize the tracked object. Furthermore, we designed an update control mechanism to learn appearance change while avoiding model drift. We evaluated the proposed tracker on object tracking benchmarks. Experimental results show the robustness of our algorithm, which performs favorably against CNN and DCF-based trackers. © 2020, Springer Nature Switzerland AG.

关键词： Convolutional neural networks

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Fault-Tolerant architecture for On-board Dual-Core Synthetic-Aperture Radar Imaging 15th

Fault-Tolerant Architecture for On-board Dual-Core Synthetic...

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15th International symposium on Applied Reconfigurable computing

作者： Cruz, Helena Duarte, Rui Policarpo Neto, Horacio INESC ID Rua Alves Redol 9 Lisbon Portugal Univ Lisbon Inst Super Tecn Lisbon Portugal

ISBN: (纸本)9783030172268;9783030172275

In this research work, an on-board dual-core embedded architecture was developed for SAR imaging systems, implementing a reduced-precision redundancy fault-tolerance mechanism. this architecture protects the execution of the BackProjection Algorithm, capable of generating acceptable SAR images in embedded systems subjected to errors from the space environment. the proposed solution was implemented on a Xilinx SoC device with a dual-core processor. the present work was able to produced images with less 0.65 dB on average, than the fault-free image, at the expense of a time overhead up to 33%, when in the presence of error rates similar to the ones measured in space environment. Notwithstanding, the BackProjection algorithm executed up to 1.58 times faster than its single-core version without any fault-tolerance mechanisms.

关键词： Synthetic-Aperture Radar BackProjection Algorithm Approximate computing FPGA Dual-core SoC

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SoC-based computing infrastructures for scientific applications and commercial services: performance and economic evaluations

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FUTURE GENERATION computer SYSTEMS-thE INTERNATIONAL JOURNAL OF ESCIENCE 2019年 96卷 11-22页

作者： D'Agostino, Daniele Quarati, Alfonso Clematis, Andrea Morganti, Lucia Corni, Elena Giansanti, Valentina Cesini, Daniele Merelli, Ivan Natl Res Council Italy Inst Appl Math & Informat Technol E Magenes Genoa Italy Italian Inst Nucl Phys CNAF Sect Bologna Italy Natl Res Council Italy Inst Biomed Technol Milan Italy

Energy consumption represents one of the most relevant issues by now in operating computing infrastructures, from traditional high performance computing Centers to Cloud Data Centers. Low power System-on-Chip (SoC) architectures, originally developed in the context of mobile and embedded technologies, are becoming attractive also for scientific and industrial applications given their increasing computing performances, coupled with relatively low costs and power demands. In this paper, we investigate the performance of the most representative SoCs for a computational intensive N-body benchmark, a simple deep learning based application and a real-life application taken from the field of molecular biology. the goal is to assess the trade-off among time-to-solution, energy-to-solution and economical aspects for both scientific and commercial purposes they are able to achieve in comparison to traditional server-grade architectures adopted in present infrastructures. (C) 2019 Elsevier B.V. All rights reserved.

关键词： Low power Systems-on-Chip N-body benchmark Deep learning Next-Generation Sequencing performance and economic evaluations

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A Stochastic-computing based Deep Learning Framework using Adiabatic Quantum-Flux-Parametron Superconducting Technology 19

A Stochastic-Computing based Deep Learning Framework using A...

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46th International symposium on computer architecture (ISCA) / Workshop on computer architecture Education (WCAE)

作者： Cai, Ruizhe Ren, Ao Chen, Olivia Liu, Ning Ding, Caiwen Qian, Xuehai Han, Jie Luo, Wenhui Yoshikawa, Nobuyuki Wang, Yanzhi Northeastern Univ Boston MA 02115 USA Yokohama Natl Univ Yokohama Kanagawa Japan Univ Southern Calif Los Angeles CA 90089 USA Univ Alberta Edmonton AB Canada

ISBN: (纸本)9781450366694

the Adiabatic Quantum-Flux-Parametron (AQFP) superconducting technology has been recently developed, which achieves the highest energy efficiency among superconducting logic families, potentially 104-105 gain compared with state-of-the-art CMOS. In 2016, the successful fabrication and testing of AQFP-based circuits with the scale of 83,000 JJs have demonstrated the scalability and potential of implementing largescale systems using AQFP. As a result, it will be promising for AQFP in high-performance computing and deep space applications, with Deep Neural Network (DNN) inference acceleration as an important example. Besides ultra-high energy efficiency, AQFP exhibits two unique characteristics: the deep pipelining nature since each AQFP logic gate is connected with an AC clock signal, which increases the difficulty to avoid RAW hazards;the second is the unique opportunity of true random number generation (RNG) using a single AQFP buffer, far more efficient than RNG in CMOS. We point out that these two characteristics make AQFP especially compatible with the stochastic computing (SC) technique, which uses a time-independent bit sequence for value representation, and is compatible with the deep pipelining nature. Further, the application of SC has been investigated in DNNs in prior work, and the suitability has been illustrated as SC is more compatible with approximate computations. this work is the first to develop an SC-based DNN acceleration framework using AQFP technology. the deep-pipelining nature of AQFP circuits translates into the difficulty in designing accumulators/counters in AQFP, which makes the prior design in SC-based DNN not suitable. We overcome this limitation taking into account different properties in CONV and FC layers: (i) the inner product calculation in FC layers has more number of inputs than that in CONV layers;(ii) accurate activation function is critical in CONV rather than FC layers. Based on these observations, we propose (i) accurate inte

关键词： Stochastic computing Deep Learning Adiabatic Quantum-Flux-Parametron Superconducting

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iMACE: In-Memory Acceleration of Classic McEliece Encoder 18

iMACE: In-Memory Acceleration of Classic McEliece Encoder

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18th IEEE-computer-Society Annual symposium on VLSI (ISVLSI)

作者： Nagarajan, Karthikeyan Ensan, Sina Sayyah Mandal, Swagata Ghosh, Swaroop Chattopadhyay, Anupam Penn State Univ Sch EECS University Pk PA 16802 USA Jalpaiguri Govt Engn Coll Sch ECE Jalpaiguri India Nanyang Technol Univ Sch CSE Singapore Singapore

ISBN: (纸本)9781728133911

Asymmetric code-based crypto-systems have been developed in the last decade due to rapid evolution of quantum computing that can potentially compromise RSA and ECC based crypto-systems. the McEliece crypto-system based on the general decoding problem is one of the front runner candidates for post-quantum cryptography but the energy efficiency is limited by the heavy data traffic between the processing elements and the memory. In memory-computing (IMC) architectures can remove the energy-efficiency barriers posed by Von-Neumann computing due to movement of data between the processor and the memory. Emerging non-volatile memories (NVM) such as, Resistive RAM (ReRAM) implemented in a crossbar array are promising substrates to realize IMC due to excellent high Resistance State (HRS) to Low Resistance State (LRS) ratios and high-densities. therefore, McEliece can be benefited substantially by in-memory acceleration. We propose, iMACE, a high performance and area-efficient hardware implementation of the core encoding function of McEliece by exploiting ReRAM-based IMC. Simulation results show 18.8X-94X better throughput and 46%-97% reduction in energy consumption compared to the FPGA-based implementation.

关键词： computer architecture Elliptic curve cryptography Encryption Resistance

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Near-Memory and In-Storage FPGA Acceleration for Emerging Cognitive computing Workloads (Invited Paper) 18

Near-Memory and In-Storage FPGA Acceleration for Emerging Co...

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18th IEEE-computer-Society Annual symposium on VLSI (ISVLSI)

作者： Dhar, Ashutosh Huang, Sitao Xiong, Jinjun Jamsek, Damir Mesnet, Bruno Huang, Jian Kim, Nam Sung Hwu, Wen-mei Chen, Deming Univ Illinois Ctr C3SR Urbana IL 61801 USA IBM Res San Jose CA USA IBM Syst Boigny Sur Bionne France

ISBN: (纸本)9781728133911

the slow down in Moore's Law has resulted in poor scaling of performance and energy. this slow down in scaling has been accompanied by the explosive growth of cognitive computing applications, creating a demand for high performance and energy efficient solutions. Amidst this climate, FPGA-based accelerators are emerging as a potential platform for deploying accelerators for cognitive computing workloads. However, the slow-down in scaling also limits the scaling of memory and I/O bandwidths. Additionally, a growing fraction of energy is spent on data transfer between off-chip memory and the compute units. thus, now more than ever, there is a need to leverage near-memory and in-storage computing to maximize the bandwidth available to accelerators, and further improve energy efficiency. In this paper, we make the case for leveraging FPGAs in near-memory and in-storage settings, and present opportunities and challenges in such scenarios. We introduce a conceptual FPGA-based near-data processing architecture, and discuss innovations in architecture, systems, and compilers for accelerating cognitive computing workloads.

关键词： Near Memory Acceleration In-Storage Acceleration NMA FPGA Cognitive computing Deep Learning

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