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Few-Shot Image Recognition with Manifolds 15th

Few-Shot Image Recognition with Manifolds

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15th International symposium on Visual computing, ISVC 2020

作者： Das, Debasmit Moon, J.H. George Lee, C.S. School of Electrical and Computer Engineering Purdue University West LafayetteIN United States

ISBN: (纸本)9783030645588

In this paper, we extend the traditional few-shot learning (FSL) problem to the situation when the source-domain data is not accessible but only high-level information in the form of class prototypes is available. this limited information setup for the FSL problem deserves much attention due to its implication of privacy-preserving inaccessibility to the source-domain data but it has rarely been addressed before. Because of limited training data, we propose a non-parametric approach to this FSL problem by assuming that all the class prototypes are structurally arranged on a manifold. Accordingly, we estimate the novel-class prototype locations by projecting the few-shot samples onto the average of the subspaces on which the surrounding classes lie. During classification, we again exploit the structural arrangement of the categories by inducing a Markov chain on the graph constructed with the class prototypes. this manifold distance obtained using the Markov chain is expected to produce better results compared to a traditional nearest-neighbor-based Euclidean distance. To evaluate our proposed framework, we have tested it on two image datasets – the large-scale ImageNet and the small-scale but fine-grained CUB-200. We have also studied parameter sensitivity to better understand our framework. © 2020, Springer Nature Switzerland AG.

关键词： Large dataset

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On the testing of special memories in GPGPUs

On the testing of special memories in GPGPUs

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IEEE symposium on On-Line Testing (IOLTS)

作者： Josie E. Rodriguez Condia Matteo Sonza Reorda Dept. of Control and Computer Engineering Politecnico di Torino Torino Italy

ISBN: (数字)9781728181875

ISBN: (纸本)9781728181882

Nowadays, data-intensive processing applications, such as multimedia, high-performance computing and safety-critical ones (e.g., in automotive) employ General Purpose Graphics Processing Units (GPGPUs) due to their parallel processing capabilities and high performance. In these devices, multiple levels of memories are employed in GPGPUs to hide latency and increase the performance during the operation of a kernel. Moreover, modern GPGPU architectures implement cutting-edge semiconductor technologies, reducing their size and power consumption. However, some studies proved that these technologies are prone to faults during the operative life of a device, so compromising reliability. In this work, we developed functional test techniques based on parallel Software-Based Self-Test routines to test memory structures in the memory hierarchy of a GPGPU (FlexGripPlus) implementing the G80 architecture of Nvidia.

关键词： Instruction sets Registers Radio frequency Kernel performance evaluation computer architecture Power demand

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Constrained optimization via quantum genetic algorithm for task scheduling problem 10th

Constrained optimization via quantum genetic algorithm for t...

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10th International symposium on Parallel architectures, Algorithms and Programming, PAAP 2019

作者： Yan, Zihan Shen, Hong Huang, Huiming Deng, Zexi School of Data and Computer Science Sun Yat-sen University Guangzhou China

Task scheduling is one of the most important issues on heterogeneous multiprocessor systems. In this paper, the problem is defined as performance-constrained energy optimization. It is a commonly used constrained optimization problem (COP) in practice. Task scheduling for constrained optimization problem is NP problem. It is usually handled by heuristics or meta-heuristics method. Classic quantum genetic algorithm is an excellent meta-heuristics algorithm, but they are hardly ever used to handle COPs because quantum rotation gate can only deal with single objective problem. Moreover, it is difficult to model the task scheduling problems so as to be handled by quantum genetic algorithm. To handles COPs in task scheduling on heterogeneous multiprocessor systems, we propose a new quantum genetic algorithm. In our algorithm, the chromosome consists of task sequence part and mapping part. Task sequence part is generated by list scheduling algorithm which can improve the parallel of the tasks. the mapping part indicates the correspondence between the tasks and the processors which they will run on. the mapping part will be transferred to quantum bits and take part in the evolve-ment guided by quantum genetic algorithm. Beside, we adopt an adaptive penalty method which belongs to constraint-handling technique to transfer COP into single objective problem. the results in simulations show the superiority of our method compared with state-of-the-art algorithms. © Springer Nature Singapore Pte Ltd. 2020.

关键词： Mapping

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Hsm2: A hybrid and scalable metadata management method in distributed file systems 10th

Hsm2: A hybrid and scalable metadata management method in di...

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10th International symposium on Parallel architectures, Algorithms and Programming, PAAP 2019

作者： Wang, Yiduo Chen, Youxu Shao, Xinyang Chen, Jinzhong Yuan, Liu Xu, Yinlong School of Computer Science and Technology University of Science and Technology of China AnHui Province Key Laboratory of High Performance Computing Hefei China East China Research Institute of Electronic Engineering Hefei China China Academy of Electronics and Information Technology Beijing China

In the bigdata era, metadata performance is critical in modern distributed file systems. Traditionally, the metadata management strategies like the subtree partitioning method focus on keeping namespace locality, while the other ones like the hash-based mapping method aim to offer good load balance. Nevertheless, none of these methods achieve the two desirable properties simultaneously. To close this gap, in this paper, we propose a novel metadata management scheme, HSM2, which combines the subtree partitioning and hash-based mapping method together. We implemented HSM2 in CephFS, a widely deployed distributed file systems, and conducted a comprehensive set of metadata-intensive experiments. Experimental results show that HSM2 can achieve better namespace locality and load balance simultaneously. Compared with CephFS, HSM2 can reduce the completion time by 70% and achieve 3.9× overall throughput speedup for a file-scanning workload. © Springer Nature Singapore Pte Ltd. 2020.

关键词： Metadata

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PLEXUS: A Pattern-Oriented Runtime System architecture for Resilient Extreme-Scale high-performance computing Systems

PLEXUS: A Pattern-Oriented Runtime System Architecture for R...

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Pacific Rim International symposium on Dependable computing

作者： Saurabh Hukerikar Christian Engelmann Oak Ridge National Laboratory Oak Ridge TN USA

ISBN: (数字)9781728180038

ISBN: (纸本)9781728180045

For high-performance computing (HPC) system designers and users, meeting the myriad challenges of next-generation exascale supercomputing systems requires rethinking their approach to application and system software design. Among these challenges, providing resiliency and stability to the scientific applications in the presence of high fault rates requires new approaches to software architecture and design. As HPC systems become increasingly complex, they require intricate solutions for detection and mitigation for various modes of faults and errors that occur in these large-scale systems, as well as solutions for failure recovery. these resiliency solutions often interact with and affect other system properties, including application scalability, power and energy efficiency. therefore, resilience solutions for HPC systems must be thoughtfully engineered and deployed. In previous work, we developed the concept of resilience design patterns, which consist of templated solutions based on well-established techniques for detection, mitigation and recovery. In this paper, we use these patterns as the foundation to propose new approaches to designing runtime systems for HPC systems. the instantiation of these patterns within a runtime system enables flexible and adaptable end-to-end resiliency solutions for HPC environments. the paper describes the architecture of the runtime system, named Plexus, and the strategies for dynamically composing and adapting pattern instances under runtime control. this runtime-based approach enables actively balancing the cost-benefit trade-off between performance overhead and protection coverage of the resilience solutions. Based on a prototype implementation of PLEXUS, we demonstrate the resiliency and performance gains achieved by the pattern-based runtime system for a parallel linear solver application.

关键词： Resilience Runtime Libraries computer architecture Systems architecture Government Scalability

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AIR: A Light-Weight Yet high-performance Dataflow Engine based on Asynchronous Iterative Routing

AIR: A Light-Weight Yet High-Performance Dataflow Engine bas...

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International symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Vinu E. Venugopal Martin theobald Samira Chaychi Amal Tawakuli University of Luxembourg Belval Esch-sur-Alzette Luxembourg Faculty of Science Technology and Medicine University of Luxembourg Belval Luxembourg

ISBN: (数字)9781728199245

ISBN: (纸本)9781728199252

Distributed Stream Processing Engines (DSPEs) are currently among the most emerging topics in data management, with applications ranging from real-time event monitoring to processing complex dataflow programs and big data analytics. In this paper, we describe the architecture of our AIR engine, which is designed from scratch in C++ using the Message Passing Interface (MPI), pthreads for multithreading, and is directly deployed on top of a common HPC workload manager such as SLURM. AIR implements a light-weight, dynamic sharding protocol (referred to as "Asynchronous Iterative Routing"), which facilitates a direct and asynchronous communication among all worker nodes and thereby completely avoids any additional communication overhead with a dedicated master node. With its unique design, AIR fills the gap between the prevalent scale-out (but Java-based) architectures like Apache Spark and Flink, on one hand, and recent scale-up (and C++ based) prototypes such as StreamBox and PiCo, on the other hand. Our experiments over various benchmark settings confirm that AIR performs as good as the best scale-up SPEs on a single-node setup, while it outperforms existing scale-out DSPEs in terms of processing latency and sustainable throughput by a factor of up to 15 in a distributed setting.

关键词： Task analysis throughput computer architecture C++ languages Message systems Resource management Java

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15th International symposium on Applied Reconfigurable computing, ARC 2019

15th International Symposium on Applied Reconfigurable Compu...

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15th International symposium on Applied Reconfigurable computing, ARC 2019

ISBN: (纸本)9783030172268

the proceedings contain 28 papers. the special focus in this conference is on Applied Reconfigurable computing. the topics include: Proof-Carrying Hardware Versus the Stealthy Malicious LUT Hardware Trojan;secure Local Configuration of Intellectual Property Without a Trusted third Party;HiFlipVX: An Open Source high-Level Synthesis FPGA Library for Image Processing;Real-Time FPGA Implementation of Connected Component Labelling for a 4K Video Stream;A Scalable FPGA-Based architecture for Depth Estimation in SLAM;Evaluating LULESH Kernels on OpenCL FPGA;the TaPaSCo Open-Source Toolflow for the Automated Composition of Task-Based Parallel Reconfigurable computing Systems;Graph-Based Code Restructuring Targeting HLS for FPGAs;UltraSynth: Integration of a CGRA into a Control Engineering Environment;exploiting Reconfigurable Vector Processing for Energy-Efficient Computation in 3D-Stacked Memories;Optimizing CNN-Based Hyperspectral Image Classification on FPGAs;Automatic Toolflow for VCGRA Generation to Enable CGRA Evaluation for Arithmetic Algorithms;reM: A Reconfigurable Multipotent Cell for New Distributed Reconfigurable architectures;Update or Invalidate: Influence of Coherence Protocols on Configurable HW Accelerators;hybrid Prototyping for Manycore Design and Validation;Evaluation of FPGA Partitioning Schemes for Time and Space Sharing of Heterogeneous Tasks;third Party CAD Tools for FPGA Design—A Survey of the Current Landscape;Filter-Wise Pruning Approach to FPGA Implementation of Fully Convolutional Network for Semantic Segmentation;Exploring Data Size to Run Convolutional Neural Networks in Low Density FPGAs;Faster Convolutional Neural Networks in Low Density FPGAs Using Block Pruning;Supporting Columnar In-memory Formats on FPGA: the Hardware Design of Fletcher for Apache Arrow;A Novel Encoder for TDCs.

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A Fast and Scalable Pipeline for Stain Normalization of Whole-Slide Images in Histopathology 15th

A Fast and Scalable Pipeline for Stain Normalization of Whol...

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15th European Conference on computer Vision (ECCV)

作者： Stanisavljevic, Milos Anghel, Andreea Papandreou, Nikolaos Andani, Sonali Pati, Pushpak Ruschoff, Jan Hendrik Wild, Peter Gabrani, Maria Pozidis, Haralampos IBM Res Zurich CH-8803 Ruschlikon Switzerland Univ Klinikum Frankfurt Senckenberg Inst Pathol D-60590 Frankfurt Germany Univ Spital Zurich Inst Pathol & Mol Pathol CH-8091 Zurich Switzerland

ISBN: (纸本)9783030110246;9783030110239

Stain normalization is one of the main tasks in the processing pipeline of computer-aided diagnosis systems in modern digital pathology. Some of the challenges in this tasks are memory and runtime bottlenecks associated with large image datasets. In this work, we present a scalable and fast pipeline for stain normalization using a state-of-the-art unsupervised method based on stain-vector estimation. the proposed system supports single-node and distributed implementations. Based on a highly-optimized engine, our architecture enables high-speed and large-scale processing of high-magnification whole-slide images (WSI). We demonstrate the performance of the system using measurements from different datasets. Moreover, by using a novel pixel-sampling optimization we show lower processing time per image than the scanning time of ultrafast WSI scanners with the single-node implementation and additional 3.44 average speed-up with the 4-nodes distributed pipeline.

关键词： Histopathological image processing Whole-slide images Stain normalization Distributed computing Color deconvolution

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the BRISC-V Platform: A Practical Teaching Approach for computer architecture

The BRISC-V Platform: A Practical Teaching Approach for Comp...

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46th International symposium on computer architecture (ISCA) / Workshop on computer architecture Education (WCAE)

作者： Agrawal, Rashmi Bandara, Sahan Ehret, Alan Isakov, Mihailo Mark, Miguel Kinsy, Michel A. Boston Univ Adapt & Secure Comp Syst ASCS Lab Boston MA 02215 USA

ISBN: (纸本)9781450368421

computer architecture lies at the intersection of electrical engineering, digital design, compiler design, programming language theory and high-performance computing. It is considered a foundational segment of an electrical and computer engineering education. RISC-V is a new and open ISA that is gaining significant traction in academia. Despite it being used extensively in research, more RISC-V-based tools need to be developed in order for RISC-V to gain greater adoption in computer organization and computer architecture classes. To that end, we present the BRISC-V Platform, a design space exploration tool which offers: (1) a web-based RISC-V simulator, which compiles C and executes assembly within the browser, and (2) a web-based generator of fully-synthesizable, highly-modular and parametrizable hardware systems with support for different types of cores, caches, and network-on-chip topologies. We illustrate how we use these tools in teaching computer organization and computer architecture classes, and describe the structure of these classes.

关键词： computer architecture computer organization risc-v simulator Verilog generator

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NFVMP: An architecture for NFV Applications from Multiple Providers 20

NFVMP: An Architecture for NFV Applications from Multiple Pr...

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20th Asia-Pacific Network Operations and Management symposium (APNOMS)

作者： Li, Lishan Liu, Ying Wu, Jianping Ren, Gang Tsinghua Univ Inst Network Sci & Cyberspace Beijing Peoples R China Tsinghua Univ Dept Comp Sci & Technol Beijing Peoples R China

ISBN: (纸本)9784885523205

With the evolution of Network Function Virtualization (NFV), small- and medium-size enterprises are increasingly outsourcing their network functions (NFs) to the cloud. In order to obtain cost-effective and high-performance services, customers may utilize NFs from various cloud providers. Current NFV architectures are mostly designed on the assumption of one provider, which utilize centralized controllers for orchestration. In multi-provider scenario, autonomy of each provider leads to infeasibility of a centralized controller. In this paper, we propose NFVMP, a novel NFV architecture that enables cooperation of providers to compose intended chains, while maintaining dependency of each provider. NFVMP adopts a fresh view that regards the sub-chain of each provider as first-class entity, and supports sub-chain composition and flexibility. We implement a prototype, which demonstrates that NFVMP supports correct chain deployment across providers with a negligible performance overhead on latency and throughput.

关键词： Noise measurement Partitioning algorithms Cloud computing Classification algorithms Switches computer architecture Network function virtualization

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