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检索条件"任意字段=16th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA 2008"

共 51 条记录，以下是41-50 订阅

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Simultaneous Retiming and Placement for Pipelined Netlists

Simultaneous Retiming and Placement for Pipelined Netlists

引用

Annual IEEE symposium on field-programmable Custom Computing Machines (FCCM)

作者： Ken Eguro Scott Hauck Department of Electrical Engineering University of Washington Seattle WA USA

Although pipelining or C-slowing an fpga-based application can potentially dramatically improve the performance, this poses a question for conventional reconfigurable architectures and CAD tools: what is the best way to support these new extra registers? While there have been multiple research efforts to address this problem, they generally impose strict architectural requirements, offer limited retiming capabilities, or require multiple iterations with no guarantees regarding feasible implementations. In this paper we introduce a new simulated annealing-based placement and retiming approach that provides the capability to aggressive apply retiming on a wide range of netlists, for arbitrary architectures, while maintaining predictable results. Our results show that for heavily pipelined applications, this methodology can produce netlists and placements with 1.65x better post-routing critical path delay as compared to the classical approach of retiming before timing-driven VPR placement, and 1.08x better than retiming before our improved timing-driven placer.

关键词： field programmable gate arrays Pipeline processing Circuits Delay Registers Timing Clocks Logic devices Reconfigurable architectures Frequency

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the Effectiveness of Configuration Merging in Point-to-Point Networks for Module-based fpga Reconfiguration

The Effectiveness of Configuration Merging in Point-to-Point...

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Annual IEEE symposium on field-programmable Custom Computing Machines (FCCM)

作者： Shannon Koh Oliver Diessel School of Computer Science and Engineering University of New South Wales Sydney Australia

Communications infrastructure for modular reconfiguration of fpgas needs to support the changing communications interfaces of a sequence of modules. In order to avoid the overheads incurred by a bus system or network-on-chip, the approach we have taken is to create point-to-point wiring harnesses to support the dynamic intermodule communications. these harnesses are reconfigured at various stages in the application as necessary. the COMMA methodology implements applications on tile-reconfigurable fpgas such as the Virtex-4. this paper outlines the methodology and describes greedy and dynamic programming-based algorithms for merging configurations, which is a central process in generating wiring harnesses within the methodology. the effects of merging the configuration graphs were explored with both algorithms for a range of device sizes and architectural parameters. Our evaluation indicates graph merging using the greedy method can reduce reconfiguration delay by up to 60% and the dynamic programming algorithm can achieve a further 50% reduction in reconfiguration delay.

关键词： Merging field programmable gate arrays Wiring Network-on-a-chip Heuristic algorithms Delay effects Protocols Computer interfaces Computer networks Computer science

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An Efficient Implementation of a Phase Unwrapping Kernel on Reconfigurable Hardware

An Efficient Implementation of a Phase Unwrapping Kernel on ...

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Annual IEEE symposium on field-programmable Custom Computing Machines (FCCM)

作者： Sherman Braganza Miriam Leeser Northeastern University Boston MA USA

the optical quadrature method of microscopy (OQM) was developed at Northeastern University for the purpose of non-invasively capturing phase data to image the sample being studied. this phase data need to be unwrapped before it can be of use. Phase unwrapping is the process by which an integer multiple of 2¿ is added to a measured, wrapped phase value in order to generate a continuous function. the algorithm used is the minimum L P norm method which uses a two dimensional discrete cosine transform (2-D DCT) to solve the discrete Poisson equation. this calculation forms the most computationally expensive part of the minimum L P norm method. this paper presents an implementation on reconfigurable hardware that performs the 2-D DCT over the entire image, solves the Poisson equation and then performs the two dimensional inverse discrete cosine transform (2-D IDCT) using a novel fpga implementation of the DCT with a semi-floating point data representation.

关键词： Kernel Hardware Discrete cosine transforms Poisson equations Embryo Random access memory field programmable gate arrays Timing Glass Optical microscopy

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ShareStreams-V: A Virtualized QoS Packet Scheduling Accelerator

ShareStreams-V: A Virtualized QoS Packet Scheduling Accelera...

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Annual IEEE symposium on field-programmable Custom Computing Machines (FCCM)

作者： Kangtao Kendall Chuang Sudhakar Yalamanchili Ada Gavrilovska Karsten Schwan Qualcomm Inc. Center for Experimental Research in Computer Systems School of Electrical & Computer Engineering and School of Computer Sciences Georgia Institute of Technology USA

this paper introduces a virtualized fpga-based accelerator for wire speed scheduling of packet streams under quality of service constraints. this work implements the dynamic window constrained scheduling algorithm and builds upon our previous custom accelerator by adding support for virtualization. this implementation is parametric, permitting tradeoffs between packet decision latency, decision throughput, and the number of virtual packet schedulers supported. When scheduling streams from multiple processes, ShareStreams-V 1 is able to schedule minimal size packets faster than one decision per 51.2 ns for up to 64 streams, the throughput required for 10 gbps Ethernet. the bottleneck currently is the host-accelerator HW/SW (PCIe) interface; this may be mitigated using high-speed interconnects/interfaces such as HyperTransport.

关键词： Scheduling algorithm Acceleration field programmable gate arrays Quality of service Wire throughput Dynamic scheduling Resource virtualization Communication system control Registers

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fpga-Based Co-processor for Singular Value Array Reconciliation Tomography

FPGA-Based Co-processor for Singular Value Array Reconciliat...

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Annual IEEE symposium on field-programmable Custom Computing Machines (FCCM)

作者： Jack Coyne David Cyganski R. James Duckworth Worcester Polytechnic Institute Worcester MA USA

We present an fpga-based co-processor for accelerating computations associated with Singular Value Array Reconciliation Tomography (SART), a recently developed method for RF source localization. the co-processor allows this relatively complex computational task to be performed using less hardware and less power than would be required by a microprocessor-based computing cluster with comparable throughput and accuracy. the architecture exploits parallelism of the SART algorithm at many levels in order to efficiently map it into the fpga platform. the system has been developed in VHDL, and implemented on a Virtex-4 SX55 fpga. Compared to a Pentium 4 CPU running at 3 GHz, use of the co-processor system provides a speed-up of about 6 times for the current signal matrix size of 128-by-16. Greater speed-ups will be obtained when larger matrices are processed because the co-processor reduces the complexity of a m-by-n SVD from O(mn 2 ), to O(mn). Even larger speed-ups may be obtained by using multiple devices in parallel. the system is capable of computing the SART metric to an accuracy of about -145 dB (0.2 ppm) with respect to its true value. this level of accuracy, which is better than that obtained using single precision floating point arithmetic, allows even relatively weak signals to make a meaningful contribution to the final SART solution.

关键词： Coprocessors Tomography field programmable gate arrays Acceleration Radio frequency Hardware throughput Computer architecture Parallel processing Clustering algorithms

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Map-reduce as a Programming Model for Custom Computing Machines

Map-reduce as a Programming Model for Custom Computing Machi...

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Annual IEEE symposium on field-programmable Custom Computing Machines (FCCM)

作者： Jackson H.C. Yeung C.C. Tsang K.H. Tsoi Bill S.H. Kwan Chris C.C. Cheung Anthony P.C. Chan Philip H.W. Leong Department of Computer Science and Engineering Chinese University of Hong Kong New Territories Hong Kong China Hong Kong Science and Technology Park Cluster Technology Limited New Territories Hong Kong China

the map-reduce model requires users to express their problem in terms of a map function that processes single records in a stream, and a reduce function that merges all mapped outputs to produce a final result. By exposing structural similarity in this way, a number of key issues associated with the design of custom computing machines including parallelisation; design complexity; software-hardware partitioning; hardware-dependency, portability and scalability can be easily addressed. We present an implementation of a map-reduce library supporting parallel field programmable gate arrays (fpgas) and graphics processing units (GPUs). Parallelisation due to pipelining, multiple data paths and concurrent execution of fpga/GPU hardware is automatically achieved. Users first specify the map and reduce steps for the problem in ANSI Cand no knowledge of the underlying hardware or parallelisation is needed. the source code is then manually translated into a pipelined data path which, along with the map-reduce library, is compiled into appropriate binary configurations for the processing units. We describe our experience in developing a number of benchmark problems in signal processing, Monte Carlo simulation and scientific computing as well as report on the performance of fpga, GPU and heterogeneous systems.

关键词： field programmable gate arrays Hardware Concurrent computing Parallel processing Graphics Signal processing Computer science Scalability Software libraries Pipeline processing

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Kiwi: Synthesis of fpga Circuits from Parallel Programs

Kiwi: Synthesis of FPGA Circuits from Parallel Programs

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Annual IEEE symposium on field-programmable Custom Computing Machines (FCCM)

作者： Satnam Singh David J. Greaves Computer Laboratory University of Cambridge Cambridge UK Microsoft Research Cambridge Cambridge UK

We describe the Kiwi parallel programming library and its associated synthesis system which is used to transform C# parallel programs into circuits for realization on fpgas. the Kiwi system is targeted at making reconfigurable computing technology accessible to software engineers that are willing to express their computations as parallel programs. Although there has been much work on compiling sequential C-like programs to hardware by automatically `discovering¿ parallelism, we work by exploiting the parallel architecture communicated by the designer through the choice of parallel and concurrent programming language constructs. Specifically, we describe a system that takes .NET assembly language with suitable custom attributes as input and produces Verilog output which is mapped to fpgas. We can then choose to apply analysis and verification techniques to either the highlevel representation in C# or other .NET languages or to the generated RTL netlists. A distinctive aspect of our approach is the exploitation of existing language constructs for concurrent programming and synchronization which contrasts with other schemes which introduce specialized concurrency control constructs to extend a sequential language.

关键词： Circuit synthesis field programmable gate arrays Parallel programming Software libraries Concurrent computing Hardware Parallel processing Parallel architectures Computer languages Assembly systems

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Multiobjective Optimization of fpga-Based Medical Image Registration

Multiobjective Optimization of FPGA-Based Medical Image Regi...

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Annual IEEE symposium on field-programmable Custom Computing Machines (FCCM)

作者： Omkar Dandekar William Plishker Shuvra Bhattacharyya Raj Shekhar Department of Diagnostic Radiology University of Maryland Baltimore MD USA Department of Diagnostic Radiology University of Maryland College Park MD USA University of Maryland at College Park College Park MD US Department of Electrical and Computer Engineering University of Maryland College Park MD USA

With a multitude of technological innovations, one emerging trend in image processing, and medical image processing, in particular, is custom hardware implementation of computationally intensive algorithms in the quest to achieve real-time performance. For reasons of area-efficiency and performance, these implementations often employ limited-precision datapaths. Identifying effective wordlengths for these datapaths while accounting for tradeoffs between design complexity and accuracy is a critical and time consuming aspect of this design process. Having access to optimized tradeoff curves can equip designers to adapt their designs to different performance requirements and target specific devices while reducing design time. this paper presents a multiobjective optimization strategy developed in the context of field-programmable gate array-based implementation of medical image registration. Within this framework, we compare several search methods and demonstrate the applicability of an evolutionary algorithm-based search for efficiently identifying superior multiobjective tradeoff curves. this strategy can easily be adapted to a wide range of signal processing applications, including areas of image and video processing beyond the medical domain.

关键词： Biomedical imaging Image registration Signal processing algorithms Technological innovation Image processing Biomedical image processing Hardware Process design Design optimization field programmable gate arrays

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DSPs, BRAMs and a Pinch of Logic: New Recipes for AES on fpgas

DSPs, BRAMs and a Pinch of Logic: New Recipes for AES on FPG...

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Annual IEEE symposium on field-programmable Custom Computing Machines (FCCM)

作者： Saar Drimer Tim Güneysu Christof Paar Computer Laboratory University of Cambridge UK Horst Görtz Institute for IT Security Ruhr University of Bochum Germany

We present an AES cipher implementation that is based on the BlockRAM and DSP units embedded within Xilinx's Virtex-5 fpgas. An iterative "basic" module outputs a 32 bit column of an AES round each clock cycle, with a throughput of 1.76 Gbit/s when processing two 128 bit inputs. this construct is replicated four times for a 128 bit datapath for a full AES round with 6.21 Gbit/s throughput when processing eight inputs. Finally, the "round" module is replicated ten times for a fully unrolled design that yields over 55 Gbit/s of throughput. the combination and arrangement of the specialized embedded functions available in the fpga allows us to implement our designs using very few traditional user logic elements such as flip-flops and lookup tables, yet still achieve these high throughputs. the complete source code for these designs is made publicly available for use in further research and for replicating our results. Our contribution ends with a discussion of comparing cipher implementations in the literature, and why these comparisons can be meaningless without a common reporting style, platform, or within the context of a specific constrained application.

关键词： Digital signal processing Logic field programmable gate arrays Cryptography throughput Hardware Embedded computing Laboratories Computer security Clocks

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Efficient tiling patterns for reconfigurable gate arrays 08

Efficient tiling patterns for reconfigurable gate arrays

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Proceedings of the 16th international acm/sigda symposium on field programmable gate arrays

作者： Sumanta Chaudhuri Jean-Luc Danger Philippe Hoogvorst Sylvain Guilley ENST Paris France

ISBN: (纸本)9781595939340

this article does a purely mathematical analysis based on generic models, and the idea is to investigate the possibility of using tiling patterns other than Manhattan grid in fpgas. the goal of our research is to evolve fpga architectures with advances in technology, and specifically better utilization of available interconnect layers. We propose a method to evaluate tiling patterns based on the first principles ( i.e Rent's Rule, Donath's result, equivalence of wire flux and wire length). We show that, use of tiling patterns formed with higher order polygons can improve the speed and area performances of an fpga. this gain is highly dependent on depopulation schemes and other parameters. However for generic tiling patterns with crossbar switchboxes there is a 22% gain in area for the hexagonal tiling pattern, and a 30% gain in area for the octagonal tiling pattern. Moreover the average interconnect length is around 15% lesser for hexagonal and 31% lesser for the octagonal tiling compared to square tiling. We can expect a proportional increase in speed. We also present a comparative plot of total interconnect lengths for these tiling patterns and the hierarchical gate arraysthe physical realizability of these tiling patterns in CMOS are to be investigated. We present a layout scheme for both hexagonal and octagonal fpgas. To our knowledge standard processes support 45° metal lines, whereas 60° lines can be etched using non-standard processes. We must keep in mind, that in practice one must use some sort of depopulation and staggering scheme, and these results provide only an idea of gains that can be achieved. the actual interconnect structure is of course dependent on several factors (i.e available interconnect layers, difficulty of fabrication, required speed/area, evolution of CMOS technology etc). Our future research direction will be to choose an efficient interconnect strategy based on this and previous researches, as well as experimental results

关键词： tiling interconnect fpga hexagonal octagonal

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