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检索条件"任意字段=16th ACM Symposium on Principles and Practice of Parallel Programming"

共 407 条记录，以下是111-120 订阅

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A parallel Sparse Tensor Benchmark Suite on CPUs and GPUs 20

A Parallel Sparse Tensor Benchmark Suite on CPUs and GPUs

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25th acm SIGPLAN symposium on principles and practice of parallel programming (PPoPP)

作者： Li, Jiajia Lakshminarasimhan, Mahesh Wu, Xiaolong Li, Ang Olschanowsky, Catherine Barker, Kevin Pacific Northwest Natl Lab Richland WA 99352 USA Univ Utah Salt Lake City UT USA Purdue Univ W Lafayette IN 47907 USA Boise State Univ Boise ID 83725 USA

ISBN: (纸本)9781450368186

Tensor computations present significant performance challenges that impact a wide spectrum of applications. Efforts on improving the performance of tensor computations include exploring data layout, execution scheduling, and parallelism in common tensor kernels. this work presents a benchmark suite for arbitrary-order sparse tensor kernels using state-of-the-art tensor formats: coordinate (COO) and hierarchical coordinate (HiCOO). It demonstrates a set of reference tensor kernel implementations and some observations on Intel CPUs and NVIDIA GPUs. the full paper can be referred to at http://***/abs/2001.00660.

关键词： sparse tensors benchmark GPU roofline model

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Backtracking-based Load Balancing

Backtracking-based Load Balancing

引用

14th acm SIGPLAN symposium on principles and practice of parallel programming

作者： Hiraishi, Tasuku Yasugi, Masahiro Umatani, Seiji Yuasa, Taiichi Kyoto Univ Acad Ctr Comp & Media Studies Kyoto 6068501 Japan Kyoto Univ Grad Sch Informat Kyoto 6068501 Japan

ISBN: (纸本)9781605583976

High-productivity languages for parallel computing become more important as parallel environments including multicores become more common. Cilk is such a language. It provides good load balancing for many applications including irregular ones;that is, it keeps all workers busy by creating plenty of "logical" threads and adopting the oldest-first work stealing strategy. this paper proposes a "logical thread"-free framework called Tascell, which achieves a higher performance and supports a wider range of parallel environments including clusters without loss of productivity. A Tascell worker spawns a "real" task only when requested by another idle worker. the worker performs the spawning by temporarily "backtracking" and restoring its oldest task-spawnable state. Our approach eliminates the cost of spawning/managing logical threads. It also promotes the reuse of workspaces and improves the locality of reference since it does not need to prepare a workspace for each concurrently runnable logical thread. Furthermore, Tascell enables elegant and highly-efficient backtrack search algorithms with delayed workspace copying. For instance, our 16-queens problem solver is 1.86 times faster than Cilk on a system with two dual-core processors. Our approach also enables a single program to run in both shared and distributed memory environments with reasonable efficiency and scalability.

关键词： Design Languages Performance load balancing parallel computing backtracking backtrack search

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POSTER: LB-HM: Load Balance-Aware Data Placement on Heterogeneous Memory for Task-parallel HPC Applications 27

POSTER: LB-HM: Load Balance-Aware Data Placement on Heteroge...

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27th acm SIGPLAN symposium on principles and practice of parallel programming (PPoPP)

作者： Xie, Zhen Liu, Jie Ma, Sam Li, Jiajia Li, Dong Univ Calif Merced CA USA Coll William Mary Williamsburg WA USA

ISBN: (纸本)9781450392044

the emergence of heterogeneous memory (HM) provides a cost-effective and high-performance solution to memory-consuming HPC applications. However, using HM, wisely migrating data objects on it is critical for high performance. In this work, we introduce a load balance-aware page management system, named LB-HM. LB-HM introduces task semantics during memory profiling, rather than being application-agnostic. Evaluating with a set of memory-consuming HPC applications, we show that we show that LB-HM reduces existing load imbalance and leads to an average of 17.1% and 15.4% (up to 26.0% and 23.2%) performance improvement, compared with a hardware-based solution and an industry-quality software-based solution on Optane-based HM.

关键词： Semantics

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Simplifying low-level GPU programming with GAS 21

Simplifying low-level GPU programming with GAS

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26th acm SIGPLAN symposium on principles and practice of parallel programming, PPoPP 2021

作者： Yan, Da Wang, Wei Chu, Xiaowen Hkust Hong Kong Hong Kong Baptist University Hong Kong

ISBN: (纸本)9781450382946

Many low-level optimizations for NVIDIA GPU can only be implemented in native hardware assembly (SASS). However, programming in SASS is unproductive and not portable. To simplify low-level GPU programming, we present GAS (Gpu ASsembly), a PTX-like language that provides a stable instruction set across hardware architectures while giving programmers a low-level control of code execution. We demonstrate that GAS can be used with ease for low-level benchmarking and performance tuning in the context of Tensor Core HGEMM. © 2021 Owner/Author.

关键词： Graphics processing unit

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Tapir: Embedding Fork-Join parallelism into LLVM's Intermediate Representation 17

Tapir: Embedding Fork-Join Parallelism into LLVM's Intermedi...

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22nd acm SIGPLAN symposium on principles and practice of parallel programming (PPoPP)

作者： Schardl, Tao B. Moses, William S. Leiserson, Charles E. MIT Comp Sci & Artificial Intelligence Lab 32 Vassar St Cambridge MA 02139 USA

ISBN: (纸本)9781450344937

this paper explores how fork-join parallelism, as supported by concurrency platforms such as Cilk and OpenMP, can be embedded into a compiler's intermediate representation (IR). Mainstream compilers typically treat parallel linguistic constructs as syntactic sugar for function calls into a parallel runtime. these calls prevent the compiler from performing optimizations across parallel control constructs. Remedying this situation is generally thought to require an extensive reworking of compiler analyses and code transformations to handle parallel semantics. Tapir is a compiler IR that represents logically parallel tasks asymmetrically in the program's control flow graph. Tapir allows the compiler to optimize across parallel control constructs with only minor changes to its existing analyses and code transformations. To prototype Tapir in the LLVM compiler, for example, we added or modified about 6000 lines of LLVM's 4-million-line codebase. Tapir enables LLVM's existing compiler optimizations for serial code - including loop-invariant-code motion, common-subexpression elimination, and tail-recursion elimination - to work with parallel control constructs such as spawning and parallel loops. Tapir also supports parallel optimizations such as loop scheduling.

关键词： Cilk compiling control-flow graph fork-join parallelism LLVM multicore OpenMP optimization parallel computing serial semantics Tapir

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An OpenACC-based unified programming model for multi-accelerator systems 2015

An OpenACC-based unified programming model for multi-acceler...

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20th acm SIGPLAN symposium on principles and practice of parallel programming, PPoPP 2015

作者： Kim, Jungwon Lee, Seyong Vetter, Jeffrey S. Oak Ridge National Laboratory United States Georgia Institute of Technology United States

ISBN: (纸本)9781450332057

this paper proposes a novel SPMD programming model of OpenACC. Our model integrates the different granularities of parallelism from vector-level parallelism to node-level parallelism into a single, unified model based on OpenACC. It allows programmers to write programs for multiple accelerators using a uniform programming model whether they are in shared or distributed memory systems. We implement a prototype of our model and evaluate its performance with a GPU-based supercomputer using three benchmark applications.

关键词： Supercomputers

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POSTER: Towards OmpSs-2 and OpenACC Interoperation 27

POSTER: Towards OmpSs-2 and OpenACC Interoperation

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27th acm SIGPLAN symposium on principles and practice of parallel programming (PPoPP)

作者： Korakitis, Orestis De Gonzalo, Simon Garcia Guidotti, Nicolas Barreto, Joao Pedro Monteiro, Jose C. Pena, Antonio J. Barcelona Supercomputing Ctr Barcelona Spain Univ Lisbon Inst Super Tecnico INESC ID Lisbon Portugal

ISBN: (纸本)9781450392044

the increasing demand in HPC to utilize accelerators has motivated the development of pragma-based directives to target these devices. OmpSs-2 and OpenACC are both directive-based solutions that allow application programmers to utilize accelerators. the two leverage distinct types of parallelism: task parallelism and data parallelism, respectively. Non-trivial scientific applications can benefit from both types of available parallelism. However, the combination of pragma-based models is difficult to coordinate, as both assume full control and are unaware of each other at runtime. We propose an interoperation mechanism to enable novel composability across pragma-based programming models. We study and propose a clear separation of duties and implement our approach by augmenting the OmpSs-2 programming model, compiler and runtime to support OmpSs-2 + OpenACC programming.

关键词： programming Productivity Data-flow Paradigm Runtime Scheduling Code Transformation parallelism GPU

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An Overview of Medusa: Simplified Graph Processing on GPUs 12

An Overview of Medusa: Simplified Graph Processing on GPUs

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17th acm SIGPLAN symposium on principles and practice of parallel programming

作者： Zhong, Jianlong He, Bingsheng Nanyang Technol Univ Singapore 639798 Singapore

ISBN: (纸本)9781450311601

Graphs are the de facto data structures for many applications, and efficient graph processing is a must for the application performance. GPUs have an order of magnitude higher computational power and memory bandwidth compared to CPUs and have been adopted to accelerate several common graph algorithms. However, it is difficult to write correct and efficient GPU programs and even more difficult for graph processing due to the irregularities of graph structures. To address those difficulties, we propose a programming framework named Medusa to simplify graph processing on GPUs. Medusa offers a small set of APIs, based on which developers can define their application logics by writing sequential code without awareness of GPU architectures. the Medusa runtime system automatically executes the developer defined APIs in parallel on the GPU, with a series of graph-centric optimizations. this poster gives an overview of Medusa, and presents some preliminary results.

关键词： Algorithms Performance GPGPU GPU programming Graph Processing Runtime Framework

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Compactly representing parallel program executions 03

Compactly representing parallel program executions

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9th acm SIGPLAN symposium on principles and practice of parallel programming

作者： Goel, A Roychoudhury, A Mitra, T Natl Univ Singapore Sch Comp Singapore 117543 Singapore

ISBN: (纸本)9781581135886

Collecting a program's execution profile is important for many reasons: code optimization, memory layout, program debugging and program comprehension. Path based execution profiles are more detailed than count based execution profiles, since they present the order of execution of the various blocks in a program: modules, procedures, basic blocks etc. Recently, online string compression techniques have been employed for collecting compact representations of sequential program executions. In this paper, we show how a similar approach can be taken for shared memory parallel programs. Our compaction scheme yields one to two orders of magnitude compression compared to the uncompressed parallel program trace on some of the SPLASH benchmarks. Our compressed execution traces contain detailed information about synchronization and control/data flow which can be exploited for post-mortem analysis. In particular, information in our compact execution traces are useful for accurate data race detection (detecting unsynchronized shared variable accesses that occurred in the execution).

关键词： algorithms measurement path profiling program path compression dynamic program analysis

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Comparability Graph Coloring for Optimizing Utilization of Stream Register Files in Stream Processors

Comparability Graph Coloring for Optimizing Utilization of S...

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14th acm SIGPLAN symposium on principles and practice of parallel programming

作者： Yang, Xuejun Wang, Li Xue, Jingling Deng, Yu Zhang, Ying UNSW Programming Languages & Compilers Grp Sch Comp Sci & Engn Sydney NSW Australia

ISBN: (纸本)9781605583976

A stream processor executes an application that has been decomposed into a sequence of kernels that operate on streams of data elements. During the execution of a kernel, all streams accessed must be communicated through the SRF (Stream Register File), a non-bypassing software-managed on-chip memory. therefore, optimizing utilization of the SRF is crucial for good performance. the key insight is that the interference graphs formed by the streams in stream applications tend to be comparability graphs or decomposable into a set of multiple comparability graphs. We present a compiler algorithm that can find optimal or near-optimal colorings in stream IGs, thereby improving SRF utilization than the First-Fit bin-packing algorithm, the best in the literature.

关键词： Algorithms Languages Performance Stream processor stream programming comparability graph coloring software-managed cache

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