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检索条件"任意字段=16th ACM Symposium on Principles and Practice of Parallel Programming"

共 407 条记录，以下是151-160 订阅

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XIndex: A Scalable Learned Index for Multicore Data Storage 20

XIndex: A Scalable Learned Index for Multicore Data Storage

引用

25th acm SIGPLAN symposium on principles and practice of parallel programming (PPoPP)

作者： Tang, Chuzhe Wang, Youyun Dong, Zhiyuan Hu, Gansen Wang, Zhaoguo Wang, Minjie Chen, Haibo Shanghai Jiao Tong Univ Inst Parallel & Distributed Syst Shanghai Peoples R China Shanghai Jiao Tong Univ Shanghai Key Lab Scalable Comp & Syst Shanghai Peoples R China NYU Dept Comp Sci New York NY 10003 USA

ISBN: (纸本)9781450368186

We present XIndex, a concurrent ordered index designed for fast queries. Similar to a recent proposal of the learned index, XIndex uses learned models to optimize index efficiency. Comparing with the learned index, XIndex is able to effectively handle concurrent writes without affecting the query performance by leveraging fine-grained synchronization and a new compaction scheme, Two-Phase Compaction. Furthermore, XIndex adapts its structure according to runtime workload characteristics to support dynamic workload. We demonstrate the advantages of XIndex with both YCSB and TPC-C (KV), a TPC-C variant for key-value stores. XIndex achieves up to 3.2x and 4.4x performance improvement comparing with Masstree and Wormhole, respectively, on a 24-core machine, and it is open-sourced(1).

关键词： Compaction

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Leveraging parallel Nesting in Transactional Memory

Leveraging Parallel Nesting in Transactional Memory

引用

15th acm SIGPLAN symposium on principles and practice of parallel programming

作者： Barreto, Joao Dragojevic, Aleksandar Ferreira, Paulo Guerraoui, Rachid Kapalka, Michal Univ Tecn Lisboa INESC ID Lisbon Portugal Swiss Fed Inst Technol CH-1015 Lausanne Switzerland

ISBN: (纸本)9781605587080

Exploiting the emerging reality of affordable multi-core architectures goes through providing programmers with simple abstractions that would enable them to easily turn their sequential programs into concurrent ones that expose as much parallelism as possible. While transactional memory promises to make concurrent programming easy to a wide programmer community, current implementations either disallow nested transactions to run in parallel or do not scale to arbitrary parallel nesting depths. this is an important obstacle to the central goal of transactional memory, as programmers can only start parallel threads in restricted parts of their code. this paper addresses the intrinsic difficulty behind the support for parallel nesting in transactional memory, and proposes a novel solution that, to the best of our knowledge, is the first practical solution to meet the lowest theoretical upper bound known for the problem. Using a synthetic workload configured to test parallel transactions on a multi-core machine, a practical implementation of our algorithm yields substantial speed-ups (up to 22x with 33 threads) relatively to serial nesting, and shows that the time to start and commit transactions, as well as to detect conflicts, is independent of nesting depth.

关键词： Algorithms Nested parallel programs fork-join work-stealing transactional memory

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Petascale Computing with Accelerators

Petascale Computing with Accelerators

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14th acm SIGPLAN symposium on principles and practice of parallel programming

作者： Kistler, Michael Gunnels, John Brokenshire, Daniel Benton, Brad IBM Corp Austin TX 78758 USA IBM Corp Yorktown Hts NY 10598 USA

ISBN: (纸本)9781605583976

A trend is developing in high performance computing in which commodity processors are coupled to various types of computational accelerators. Such systems are commonly called hybrid systems. In this paper, we describe our experience developing an implementation of the Linpack benchmark for a petascale hybrid system, the LANL Roadrunner cluster built by IBM for Los Alamos National Laboratory. this system combines traditional x86-64 host processors with IBM PowerXCell (TM) 8i accelerator processors. the implementation of Linpack we developed was the first to achieve a performance result in excess of 1.0 PFLOPS, and made Roadrunner the #1 system on the Top500 list in June 2008. We describe the design and implementation of hybrid Linpack, including the special optimizations we developed for this hybrid architecture. We then present actual results for single node and multi-node executions. From this work, we conclude that it is possible to achieve high performance for certain applications on hybrid architectures when careful attention is given to efficient use of memory bandwidth, scheduling of data movement between the host and accelerator memories, and proper distribution of work between the host and accelerator processors.

关键词： Algorithms Performance Design Accelerators hybrid programming models

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A Comparison of programming Models for Multiprocessors with Explicitly Managed Memory Hierarchies

A Comparison of Programming Models for Multiprocessors with ...

引用

14th acm SIGPLAN symposium on principles and practice of parallel programming

作者： Schneider, Scott Yeom, Jae-Seung Rose, Benjamin Linford, John C. Sandu, Adrian Nikolopoulos, Dimitrios S. Virginia Tech Dept Comp Sci Blacksburg VA 24060 USA

ISBN: (纸本)9781605583976

On multiprocessors with explicitly managed memory hierarchies (EMM), software has the responsibility of moving data in and out of fast local memories. this task can be complex and error-prone even for expert programmers. Before we can allow compilers to handle the complexity for us, we must identify the abstractions that are general enough to allow us to write applications with reasonable effort, yet specific enough to exploit the vast on-chip memory bandwidth of EMM multi-processors. To this end, we compare two programming models against hand-tuned codes on the STI Cell, paying attention to programmability and performance. the first programming model, Sequoia, abstracts the memory hierarchy as private address spaces, each corresponding to a parallel task. the second, Cellgen, is a new framework which provides OpenMP-like semantics and the abstraction of a shared address spaces divided into private and shared data. We compare three applications programmed using these models against their hand-optimized counterparts in terms of abstractions, programming complexity, and performance.

关键词： Design Languages Cell BE Explicitly Managed Memory Hierarchies programming Models

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Improving parallel shear-warp volume rendering on shared address space multiprocessors 97

Improving parallel shear-warp volume rendering on shared add...

引用

Proceedings of the 1997 6th acm SIGPLAN symposium on principles and practice of parallel programming

作者： Jiang, Dongming Singh, Jaswinder Pal Princeton Univ Princeton NJ United States

ISBN: (纸本)9780897919067

this paper presents a new parallel volume rendering algorithm and implementation, based on shear warp factorization, for shared address space multiprocessors. Starting from an existing parallel shear-warp renderer, we use increasingly detailed performance measurements on real machines and simulators to understand performance bottlenecks. this leads us to a new parallel implementation that substantially outperforms and out-scales the old one on a range of shared address space platforms, from bus-based centralized memory machine to hardware-coherent distributed memory machines to networks of computers connected by page-based shared virtual memory. the results demonstrate that real time volume rendering is promising on general purpose multiprocessors, and illustrate the utility of tool hierarchies in conjunction with algorithmic and application knowledge to understand memory system interactions and improve parallel algorithms.

关键词： parallel algorithms

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Fault detection in multi-threaded c++ server applications 07

Fault detection in multi-threaded c++ server applications

引用

2007 acm SIGPLAN symposium on principles and practice of parallel programming, PPoPP'07

作者： Müehlenfeld, Arndt Wotawa, Franz Graz University of Technology Inffeldgasse 16b/2 A-8010 Graz Austria

this paper describes experiments with the freely available tool Helgrind, results obtained by using it for debugging a server application comprising 500 kLOC. We present improvements to the run time analysis of C++ pr... 详细信息

ISBN: (纸本)1595936025

关键词： Object oriented programming

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parallel breadth-first BDD construction

Parallel breadth-first BDD construction

引用

Proceedings of the 1997 6th acm SIGPLAN symposium on principles and practice of parallel programming

作者： Yang, Bwolen O'Hallaron, David R. Carnegie Mellon Univ Pittsburgh United States

With the increasing complexity of protocol and circuit designs, formal verification has become an important research area and binary decision diagrams (BDDs) have been shown to be a powerful tool in formal verification. this paper presents a parallel algorithm for BDD construction targeted at shared memory multiprocessors and distributed shared memory systems. this algorithm focuses on improving memory access locality through specialized memory managers and partial breadth-first expansion, and on improving processor utilization through dynamic load balancing. the results on a shared memory system show speedups of over two on four processors and speedups of up to four on eight processors. the measured results clearly identify the main source of bottlenecks and point out some interesting directions for further improvements.

关键词： parallel algorithms

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the lock-free k-LSM relaxed priority queue 2015

The lock-free k-LSM relaxed priority queue

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20th acm SIGPLAN symposium on principles and practice of parallel programming, PPoPP 2015

作者： Wimmer, Martin Gruber, Jakob Träff, Jesper Larsson Tsigas, Philippas Faculty of Informatics Parallel Computing Vienna University of Technology Vienna/Wien1040 Austria Computer Science and Engineering Chalmers University of Technology Göteborg412 96 Sweden

ISBN: (纸本)9781450332057

We present a new, concurrent, lock-free priority queue that relaxes the delete-min operation to allow deletion of any of the ρ+1 smallest keys instead of only a minimal one, where ρ is a parameter that can be configured at runtime. It is built from a logarithmic number of sorted arrays, similar to log-structured merge-trees (LSM). For keys added and removed by the same thread the behavior is identical to a non-relaxed priority queue. We compare to state-of-the-art lock-free priority queues with both relaxed and non-relaxed semantics, showing high performance and good scalability of our approach.

关键词： parallel programming

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PARRAY: A Unifying Array Representation for Heterogeneous parallelism 12

PARRAY: A Unifying Array Representation for Heterogeneous Pa...

引用

17th acm SIGPLAN symposium on principles and practice of parallel programming

作者： Chen, Yifeng Cui, Xiang Mei, Hong Peking Univ Sch EECS HCST Key Lab Beijing 100871 Peoples R China

ISBN: (纸本)9781450311601

this paper introduces a programming interface called PARRAY (or parallelizing ARRAYs) that supports system-level succinct programming for heterogeneous parallel systems like GPU clusters. the current practice of software development requires combining several low-level libraries like Pthread, OpenMP, CUDA and MPI. Achieving productivity and portability is hard with different numbers and models of GPUs. PARRAY extends mainstream C programming with novel array types of the following features:1)the dimensions of an array type are nested in a tree structure, conceptually reflecting the memory hierarchy;2) the definition of an array type may contain references to other array types, allowing sophisticated array types to be created for parallelization;3) threads also form arrays that allow programming in a Single-Program Multiple-Code block (SPMC) style to unify various sophisticated communication patterns. this leads to shorter, more portable and maintainable parallel codes, while the programmer still has control over performance-related features necessary for deep manual optimization. Although the source-to-source code generator only faithfully generates low-level library calls according to the type information,higher-level programming and automatic performance optimization are still possible through building libraries of subprograms on top of PARRAY. the case study on cluster FFT illustrates a simple 30-line code that 2x-outperforms Intel Cluster MKL on the Tianhe-1A system with 7168 Fermi GPUs and 14336 CPUs.

关键词： Languages Performance theory parallel programming Array Representation Heterogeneous parallelism GPU Clusters

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High performance Fortran for highly irregular problems

High performance Fortran for highly irregular problems

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Proceedings of the 1997 6th acm SIGPLAN symposium on principles and practice of parallel programming

作者： Hu, Y.Charlie Johnsson, S.Lennart Teng, Shang-Hua Harvard Univ Cambridge United States

We present a general data parallel formulation for highly irregular problems in High Performance Fortran (HPF). Our formulation consists of (1) a method for linearizing irregular data structures (2) a data parallel implementation (in HPF) of graph partitioning algorithms applied to the linearized data structure, (3) techniques for expressing irregular communication and nonuniform computations associated with the elements of linearized data structures. We demonstrate and evaluate our formulation on a parallel, hierarchical N-body method for the evaluation of potentials and forces of nonuniform particle distributions. Our experimental results demonstrate that efficient data parallel (HPF) implementations of highly nonuniform problems are feasible with the proper language/compiler/runtime support. Our data parallel N-body code provides a much needed 'benchmark' code for evaluating and improving HPF compilers.

关键词： parallel processing systems

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