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检索条件"任意字段=16th ACM Symposium on Principles and Practice of Parallel Programming"

共 407 条记录，以下是161-170 订阅

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CPMA: An Efficient Batch-parallel Compressed Set Without Pointers 24

CPMA: An Efficient Batch-Parallel Compressed Set Without Poi...

引用

29th acm SIGPLAN Annual symposium on principles and practice of parallel programming (PPoPP)

作者： Wheatman, Brian Burns, Randal Buluc, Aydin Xu, Helen Johns Hopkins Univ Baltimore MD 21218 USA Lawrence Berkeley Natl Lab Lawrence KS USA Georgia Inst Technol Atlanta GA USA

ISBN: (纸本)9798400704352

this paper introduces the batch-parallel Compressed Packed Memory Array (CPMA), a compressed, dynamic, ordered set data structure based on the Packed Memory Array (PMA). Traditionally, batch-parallel sets are built on pointerbased data structures such as trees because pointer-based structures enable fast parallel unions via pointer manipulation. Whencompared with cache-optimized trees, PMAswere slower to update but faster to scan. the batch-parallel CPMA overcomes this tradeoff between updates and scans by optimizing for cache-friendliness. On average, the CPMA achieves 3x faster batch-insert throughput and 4x faster range-query throughput compared with compressed PaC-trees, a state-of-the-art batch-parallel set library based on cache-optimized trees. We further evaluate the CPMA compared with compressed PaC-trees and Aspen, a state-of-the-art system, on a realworld application of dynamic-graph processing. the CPMA is on average 1.2x faster on a suite of graph algorithms and 2x faster on batch inserts when compared with compressed PaC-trees. Furthermore, the CPMA is on average 1.3x faster on graph algorithms and 2x faster on batch inserts compared with Aspen.

关键词： packed memory array batch-parallel compression data structures dynamic graphs

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Compilation of parallel multimedia computations - extending retiming theory and Amdahl's law 97

Compilation of parallel multimedia computations - extending ...

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Proceedings of the 1997 6th acm SIGPLAN symposium on principles and practice of parallel programming

作者： Prasanna, G.N.Srinivasa Lucent Technologies Murray Hill NJ United States

ISBN: (纸本)9780897919067

Multimedia applications operate on downstreams. A large class of multimedia applications is described by the macro-dataflow graph model. this study attempted to examine how such multimedia applications can be compiled to run efficiently on parallel machines, by optimizing both throughput (T) and latency (L), using two techniques based on task speedup functions. the first step chooses an appropriate pipeline structure for the system while the second exploits the dataset parallelism intrinsic in the period datastream, and runs multiple datasets in parallel (task/cluster multiplicity) for each clustering. Both techniques were used to compile real-time image-processing problems on an NCUBE-2 multiprocessor. the two techniques showed substantial performance gains.

关键词： Program compilers

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Evaluating the locality benefits of active messages

Evaluating the locality benefits of active messages

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Proceedings of the 5th acm SIGPLAN symposium on principles and practice of parallel programming

作者： Spertus, Ellen Dally, William J. Massachusetts Inst of Technology Cambridge United States

A major challenge in fine-grained computing is achieving locality without excessive scheduling overhead. We built two J-Machine implementations of a fine-grained programming model, the Berkeley threaded Abstract Machine. One implementation takes an Active Messages approach, maintaining a scheduling hierarchy in software in order to improve data cache performance. Another approach relies on the J-Machine's message queues and fast task switch, lowering the control costs at the expense of data locality. Our analysis measures the costs and benefits of each approach, for a variety of programs and cache configurations. the Active Messages implementation is strongest when miss penalties are high and for the finest-grained programs. the hardware-buffered implementation is strongest in direct-mapped caches, where it achieves substantially better instruction cache performance.

关键词： parallel processing systems

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No Barrier in the Road: A Comprehensive Study and Optimization of ARM Barriers 20

No Barrier in the Road: A Comprehensive Study and Optimizati...

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25th acm SIGPLAN symposium on principles and practice of parallel programming (PPoPP)

作者： Liu, Nian Zang, Binyu Chen, Haibo Shanghai Jiao Tong Univ Inst Parallel & Distributed Syst Shanghai Peoples R China Shanghai Jiao Tong Univ Shanghai Key Lab Scalable Comp & Syst Shanghai Peoples R China

ISBN: (纸本)9781450368186

In this paper, we present the first comprehensive performance characterization and optimization of ARM barriers on both mobile and server platforms. We draw a set of observations through several abstracted models and validate them in scenarios where barriers are intensively used. We find that (1) order-preserving approaches without involving the bus significantly outperform other approaches, and (2) the tremendous overhead mostly comes from barriers strictly following remote memory references. Usually, such barriers are inserted when threads are exchanging data, and they are used to ensure the relative order between storing the data to a shared buffer and setting a flag to inform the receiver. Based on the observations, we propose a new mechanism, Pilot, to remove such barriers by leveraging the single-copy atomicity to piggyback the flag with the data. Applying Pilot only requires minor changes to applications and provides 10%-360% performance improvements in multiple benchmarks, which are close to the ideal performance without barriers.

关键词： barrier synchronization concurrency lock

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throughput-Oriented GPU Memory Allocation 19

Throughput-Oriented GPU Memory Allocation

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24th acm SIGPLAN symposium on principles and practice of parallel programming (PPoPP)

作者： Gelado, Isaac Garland, Michael NVIDIA Santa Clara CA 95051 USA

ISBN: (纸本)9781450362252

throughput-oriented architectures, such as GPUs, can sustain three orders of magnitude more concurrent threads than multicore architectures. this level of concurrency pushes typical synchronization primitives (e.g., mutexes) over their scalability limits, creating significant performance bottlenecks in modules, such as memory allocators, that use them. In this paper, we develop concurrent programming techniques and synchronization primitives, in support of a dynamic memory allocator, that are efficient for use with very high levels of concurrency. We formulate resource allocation as a two-stage process, that decouples accounting for the number of available resources from the tracking of the available resources themselves. To facilitate the accounting stage, we introduce a novel bulk semaphore abstraction that extends traditional semaphore semantics by optimizing for the case where threads operate on the semaphore simultaneously. We also similarly design new collective synchronization primitives that enable groups of cooperating threads to enter critical sections together. Finally, we show that delegation of deferred reclamation to threads already blocked greatly improves efficiency. Using all these techniques, our throughput-oriented memory allocator delivers both high allocation rates and low memory fragmentation on modern GPUs. Our experiments demonstrate that it achieves allocation rates that are on average 16.56 times higher than the counterpart implementation in the CUDA 9 toolkit.

关键词： Concurrency Memory Allocation GPU programming

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Leveraging parallel Nesting in Transactional Memory

Leveraging Parallel Nesting in Transactional Memory

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15th acm SIGPLAN symposium on principles and practice of parallel programming

作者： Barreto, Joao Dragojevic, Aleksandar Ferreira, Paulo Guerraoui, Rachid Kapalka, Michal Univ Tecn Lisboa INESC ID Lisbon Portugal Swiss Fed Inst Technol CH-1015 Lausanne Switzerland

ISBN: (纸本)9781605587080

Exploiting the emerging reality of affordable multi-core architectures goes through providing programmers with simple abstractions that would enable them to easily turn their sequential programs into concurrent ones that expose as much parallelism as possible. While transactional memory promises to make concurrent programming easy to a wide programmer community, current implementations either disallow nested transactions to run in parallel or do not scale to arbitrary parallel nesting depths. this is an important obstacle to the central goal of transactional memory, as programmers can only start parallel threads in restricted parts of their code. this paper addresses the intrinsic difficulty behind the support for parallel nesting in transactional memory, and proposes a novel solution that, to the best of our knowledge, is the first practical solution to meet the lowest theoretical upper bound known for the problem. Using a synthetic workload configured to test parallel transactions on a multi-core machine, a practical implementation of our algorithm yields substantial speed-ups (up to 22x with 33 threads) relatively to serial nesting, and shows that the time to start and commit transactions, as well as to detect conflicts, is independent of nesting depth.

关键词： Algorithms Nested parallel programs fork-join work-stealing transactional memory

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Automatic Problem Size Sensitive Task Partitioning on Heterogeneous parallel Systems 13

Automatic Problem Size Sensitive Task Partitioning on Hetero...

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18th acm SIGPLAN symposium on principles and practice of parallel programming

作者： Grasso, Ivan Kofler, Klaus Cosenza, Biagio Fahringer, thomas Univ Innsbruck Inst Informat A-6020 Innsbruck Austria

ISBN: (纸本)9781450319225

In this paper we propose a novel approach which automatizes task partitioning in heterogeneous systems. Our framework is based on the Insieme Compiler and Runtime infrastructure [1]. the compiler translates a single-device OpenCL program into a multi-device OpenCL program. the runtime system then performs dynamic task partitioning based on an offline-generated prediction model. In order to derive the prediction model, we use a machine learning approach that incorporates static program features as well as dynamic, input sensitive features. Our approach has been evaluated over a suite of 23 programs and achieves performance improvements compared to an execution of the benchmarks on a single CPU and a single GPU only.

关键词： Languages Algorithms Performance heterogeneous computing compilers GPU task partitioning code analysis machine learning runtime system

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Petascale Computing with Accelerators

Petascale Computing with Accelerators

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14th acm SIGPLAN symposium on principles and practice of parallel programming

作者： Kistler, Michael Gunnels, John Brokenshire, Daniel Benton, Brad IBM Corp Austin TX 78758 USA IBM Corp Yorktown Hts NY 10598 USA

ISBN: (纸本)9781605583976

A trend is developing in high performance computing in which commodity processors are coupled to various types of computational accelerators. Such systems are commonly called hybrid systems. In this paper, we describe our experience developing an implementation of the Linpack benchmark for a petascale hybrid system, the LANL Roadrunner cluster built by IBM for Los Alamos National Laboratory. this system combines traditional x86-64 host processors with IBM PowerXCell (TM) 8i accelerator processors. the implementation of Linpack we developed was the first to achieve a performance result in excess of 1.0 PFLOPS, and made Roadrunner the #1 system on the Top500 list in June 2008. We describe the design and implementation of hybrid Linpack, including the special optimizations we developed for this hybrid architecture. We then present actual results for single node and multi-node executions. From this work, we conclude that it is possible to achieve high performance for certain applications on hybrid architectures when careful attention is given to efficient use of memory bandwidth, scheduling of data movement between the host and accelerator memories, and proper distribution of work between the host and accelerator processors.

关键词： Algorithms Performance Design Accelerators hybrid programming models

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Improving parallel shear-warp volume rendering on shared address space multiprocessors 97

Improving parallel shear-warp volume rendering on shared add...

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Proceedings of the 1997 6th acm SIGPLAN symposium on principles and practice of parallel programming

作者： Jiang, Dongming Singh, Jaswinder Pal Princeton Univ Princeton NJ United States

ISBN: (纸本)9780897919067

this paper presents a new parallel volume rendering algorithm and implementation, based on shear warp factorization, for shared address space multiprocessors. Starting from an existing parallel shear-warp renderer, we use increasingly detailed performance measurements on real machines and simulators to understand performance bottlenecks. this leads us to a new parallel implementation that substantially outperforms and out-scales the old one on a range of shared address space platforms, from bus-based centralized memory machine to hardware-coherent distributed memory machines to networks of computers connected by page-based shared virtual memory. the results demonstrate that real time volume rendering is promising on general purpose multiprocessors, and illustrate the utility of tool hierarchies in conjunction with algorithmic and application knowledge to understand memory system interactions and improve parallel algorithms.

关键词： parallel algorithms

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Fault detection in multi-threaded c++ server applications 07

Fault detection in multi-threaded c++ server applications

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2007 acm SIGPLAN symposium on principles and practice of parallel programming, PPoPP'07

作者： Müehlenfeld, Arndt Wotawa, Franz Graz University of Technology Inffeldgasse 16b/2 A-8010 Graz Austria

this paper describes experiments with the freely available tool Helgrind, results obtained by using it for debugging a server application comprising 500 kLOC. We present improvements to the run time analysis of C++ pr... 详细信息

ISBN: (纸本)1595936025

关键词： Object oriented programming

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