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RaftLib: A C plus plus template library for high performance stream parallel processing

INTERNATIONAL JOURNAL OF HIGH PERFORMANCE COMPUTING APPLICATIONS 2017年第5期31卷 391-404页

作者： Beard, Jonathan C. Li, Peng Chamberlain, Roger D. ARM Res 5707 Southwest Pkwy Suite 100 Austin Austin TX 78735 USA Amazon Inc Seattle WA USA Washington Univ Dept Comp Sci & Engn St Louis MO 63130 USA

Stream processing is a compute paradigm that has been around for decades, yet until recently has failed to garner the same attention as other mainstream languages and libraries (e.g. C++, OpenMP, MPI). Stream processing has great promise: the ability to safely exploit extreme levels of parallelism to process huge volumes of streaming data. there have been many implementations, both libraries and full languages. the full languages implicitly assume that the streaming paradigm cannot be fully exploited in legacy languages, while library approaches are often preferred for being integrable with the vast expanse of extant legacy code. Libraries, however are often criticized for yielding to the shape of their respective languages. RaftLib aims to fully exploit the stream processing paradigm, enabling a full spectrum of streaming graph optimizations, while providing a platform for the exploration of integrability with legacy C/C++ code. RaftLib is built as a C++ template library, enabling programmers to utilize the robust C++ standard library, and other legacy code, along with RaftLib's parallelization framework. RaftLib supports several online optimization techniques: dynamic queue optimization, automatic parallelization, and real-time low overhead performance monitoring.

关键词： Stream processing big-data C plus plus template library high performance computing RaftLib performance monitoring parallel processing

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Managing application parallelism via parallel efficiency regulation 19

Managing application parallelism via parallel efficiency reg...

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24th acm SIGPLAN symposium on principles and practice of parallel programming, PPoPP 2019

作者： Srikanthan, Sharanyan Ferro, Princeton Chakraborti, Sayak Dwarkadas, Sandhya University of Rochester United States

ISBN: (纸本)9781450362252

Modern multiprocessor systems contain a wealth of compute, memory, and communication network resources, such that multiple applications can often successfully execute on and compete for these resources. Unfortunately, good performance for individual applications in addition to achieving overall system eficiency proves a dificult task, especially for applications with low parallel eficiency (speedup per utilized computational core). Limitations to parallel eficiency arise out of factors such as algorithm design, excess synchronization, limitations in hardware resources, and sub-optimal task placement on CPUs. In this work, we introduce MAPPER, a Manager of Application parallelism via parallel Efficiency Regulation. MAPPER monitors and coordinates all participating applications by making two coupled decisions: how much parallelism to afford to each application, and which specific CPU cores to schedule applications on. While MAPPER can work for generic applications without modifying their parallel runtimes, we introduce a simple interface that can be used by parallel runtime systems for a tighter integration, resulting in better task granularity control. Using MAPPER can result in up to 3.3X speedup, with an average performance improvement of 20%. © 2019 Copyright held by the owner/author(s).

关键词： Program processors

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Scalable parallel Debugging with Statistical Assertions

Scalable Parallel Debugging with Statistical Assertions

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17th acm SIGPLAN symposium on principles and practice of parallel programming

作者： Minh Ngoc Dinh Abramson, David Jin, Chao Gontarek, Andrew Moench, Bob DeRose, Luiz Monash Univ Clayton Vic 3800 Australia Cray Inc St Paul MN 55101 USA

Traditional debuggers are of limited value for modern scientific codes that manipulate large complex data structures. this paper discusses a novel debug-time assertion, called a "Statistical Assertion", that allows a user to reason about large data structures, and the primitives are parallelised to provide an efficient solution. We present the design and implementation of statistical assertions, and illustrate the debugging technique with a molecular dynamics simulation. We evaluate the performance of the tool on a 12,000 cores Cray XE6.

关键词： Performance Verification parallel debugging statistic assertion

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Bounding space usage of conservative garbage collectors 02

Bounding space usage of conservative garbage collectors

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POPL 2002: 29th acm SIGPLAN-SIGACT symposium on principles of programming Languages

作者： Boehm, Hans-J. Hewlett-Packard Laboratories 1501 Page Mill Rd. Palo Alto CA 94304 United States

ISBN: (纸本)9781581134506

Conservative garbage collectors can automatically reclaim unused memory in the absence of precise pointer location information. If a location can possibly contain a pointer, it is treated by the collector as though it contained a pointer. Although it is commonly assumed that this can lead to unbounded space use due to misidentified pointers, such extreme space use is rarely observed in practice, and then generally only if the number of misidentified pointers is itself unbounded. We show that if the program manipulates only data structures satisfying a simple GC-robustness criterion, then a bounded number of misidentified pointers can at most result in increasing space usage by a constant factor. We argue that nearly all common data structures are already GC-robust, and it is typically easy to identify and replace those that are not. thus it becomes feasible to prove space bounds on programs collected by mildly conservative garbage collectors, such as the one in [2]. the worst-case space overhead introduced by such mild conservatism is comparable to the worst-case fragmentation overhead for inherent in any non-moving storage allocator. the same GC-robustness criterion also ensures the absence of temporary space leaks of the kind discussed in [13] for generational garbage collectors.

关键词： programming theory

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Implementation of a portable nested data-parallel language 93

Implementation of a portable nested data-parallel language

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4th acm SIGPLAN symposium on principles and practice of parallel programming, PPOPP 1993

作者： Blelloch, Guy E. Chatterjee, Siddhartha Hardwick, Jonathan C. Sipelstein, Jay Zagha, Marco School of Computer Science Carnegie Mellon University PittsburghPA15213 United States RIACS Mail Stop T045-1 NASA Ames Research Center Moffett FieldCA94035 United States

ISBN: (纸本)0897915895

this paper gives an overview of the implementation of NESL, a portable nested data-parallel language. this language and its implementation are the first to fully support nested data structures as well as nested data-parallel function calls. these features allow the concise description of parallel algorithms on irregular data, such as sparse matrices and graphs. In addition, they maintain the advantages of data-parallel languages: a simple programming model and portability. the current NESL implementation is based on an intermediate language called VcODE and a library of vector routines called CVL. It runs on the Connection Machine CM-2, the Cray Y-MP C90, and serial machines. We compare initial benchmark results of NESL with those of machine-specific code on these machines for three algorithms: least-squares line-fitting, median finding, and a sparse-matrix vector product. these results show that NESL'S performance is competitive with that of machine-specific codes for regular dense data, and is often superior for irregular data. © 1993 acm.

关键词： Matrix algebra

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Certified Compilation of Financial Contracts 18

Certified Compilation of Financial Contracts

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20th International symposium on principles and practice of Declarative programming (PPDP)

作者： Annenkov, Danil Elsman, Martin INRIA GALLINETTE Res Ream Nantes France Univ Copenhagen Dept Comp Sci DIKU Copenhagen Denmark

ISBN: (纸本)9781450364416

We present an extension to a certified financial contract management system that allows for templated declarative financial contracts and for integration with financial stochastic models through verified compilation into so-called payoff-expressions. Such expressions readily allow for determining the value of a contract in a given evaluation context, such as contexts created for stochastic simulations. the templating mechanism is useful both at the contract specification level, for writing generic reusable contracts, and for reuse of code that, without the templating mechanism, needs to be recompiled for different evaluation contexts. We report on the effect of using the certified system in the context of a GPGPU-based Monte Carlo simulation engine for pricing various over-the-counter (OTC) financial contracts. the full contract-management system, including the payoff-language compilation, is verified in the Coq proof assistant and certified Haskell code is extracted from our Coq development along with Futhark code for use in a data-parallel pricing engine.

关键词： financial contracts contract languages domain-specific languages certified programming software correctness Coq

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Prolog programming with a map-reduce parallel construct 13

Prolog programming with a map-reduce parallel construct

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15th symposium on principles and practice of Declarative programming, PPDP 2013

作者： Côrte-Real, Joana Dutra, Inês Rocha, Ricardo CRACS INESC TEC University of Porto Rua Campo Alegre 1021/1055 4169-007 Porto Portugal

ISBN: (纸本)9781450321549

Map-Reduce is a programming model that has its roots in early functional programming. In addition to producing short and elegant code for problems involving lists or collections, this model has proven very useful for large-scale highly parallel data processing. In this work, we present the design and implementation of a high-level parallel construct that makes the Map-Reduce programming model available for Prolog programmers. To the best of our knowledge, there is no Map-Reduce framework native to Prolog, and so the aim of this work is to offer data processing features from which several applications can greatly benefit;the Inductive Logic programming field, for instance, can take advantage of a Map-Reduce predicate when proving newly created rules against sets of examples. Our Map-Reduce model was comprehensively tested with different applications. Our experiments, using the Yap Prolog system, show that: (i) the model scales linearly up to 24 processors;(ii) a dynamic distributed scheduling strategy performs better than centralized or static scheduling strategies;and (iii) the performance varies significantly with the number of items being sent to each processor at a time. Overall, our Map-Reduce framework presents as a good alternative for both taking advantage of the currently available low cost multi-core architectures and developing scalable data processing applications, native to the Prolog programming language. © 2013 acm.

关键词： Computer circuits

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HPVM: Heterogeneous parallel Virtual Machine 18

HPVM: <i>Heterogeneous Parallel Virtual Machine</i>

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23rd acm SIGPLAN symposium on principles and practice of parallel programming (PPoPP)

作者： Kotsifakou, Maria Srivastava, Prakalp Sinclair, Matthew D. Komuravelli, Rakesh Adve, Vikram Adve, Sarita Univ Illinois Dept Comp Sci Champaign IL 61820 USA Qualcomm Technol Inc San Diego CA USA

ISBN: (纸本)9781450349826

We propose a parallel program representation for heterogeneous systems, designed to enable performance portability across a wide range of popular parallel hardware, including GPUs, vector instruction sets, multicore CPUs and potentially FPGAs. Our representation, which we call HPVM, is a hierarchical dataflow graph with shared memory and vector instructions. HPVM supports three important capabilities for programming heterogeneous systems: a compiler intermediate representation (IR), a virtual instruction set (ISA), and a basis for runtime scheduling;previous systems focus on only one of these capabilities. As a compiler IR, HPVM aims to enable effective code generation and optimization for heterogeneous systems. As a virtual ISA, it can be used to ship executable programs, in order to achieve both functional portability and performance portability across such systems. At runtime, HPVM enables flexible scheduling policies, both through the graph structure and the ability to compile individual nodes in a program to any of the target devices on a system. We have implemented a prototype HPVM system, defining the HPVM IR as an extension of the LLVM compiler IR, compiler optimizations that operate directly on HPVM graphs, and code generators that translate the virtual ISA to NVIDIA GPUs, Intel's AVX vector units, and to multicore X86-64 processors. Experimental results show that HPVM optimizations achieve significant performance improvements, HPVM translators achieve performance competitive with manually developed OpenCL code for both GPUs and vector hardware, and that runtime scheduling policies can make use of both program and runtime information to exploit the flexible compilation capabilities. Overall, we conclude that the HPVM representation is a promising basis for achieving performance portability and for implementing parallelizing compilers for heterogeneous parallel systems.

关键词： Virtual ISA Compiler parallel IR Heterogeneous Systems GPU Vector SIMD

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TileSpGEMM: A Tiled Algorithm for parallel Sparse General Matrix-Matrix Multiplication on GPUs 22

TileSpGEMM: A Tiled Algorithm for Parallel Sparse General Ma...

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27th acm SIGPLAN symposium on principles and practice of parallel programming (PPoPP)

作者： Niu, Yuyao Lu, Zhengyang Ji, Haonan Song, Shuhui Jin, Zhou Liu, Weifeng China Univ Petr Super Sci Software Lab Beijing Peoples R China

ISBN: (纸本)9781450392044

Sparse general matrix-matrix multiplication (SpGEMM) is one of the most fundamental building blocks in sparse linear solvers, graph processing frameworks and machine learning applications. the existing parallel approaches for shared memory SpGEMM mostly use the row-row style with possibly good parallelism. However, because of the irregularity in sparsity structures, the existing row-row methods often suffer from three problems: (1) load imbalance, (2) high global space complexity and unsatisfactory data locality, and (3) sparse accumulator selection. We in this paper propose a tiled parallel SpGEMM algorithm named TileSpGEMM. Our algorithm sparsifies the tiled method in dense general matrix-matrix multiplication (GEMM), and saves each non-empty tile in a sparse form. Its first advantage is that the basic working unit is now a fixed-size sparse tile containing a small number of nonzeros, but not a row possibly very long. thus the load imbalance issue can be naturally alleviated. Secondly, the temporary space needed for each tile is small and can always be in on-chip scratchpad memory. thus there is no need to allocate an off-chip space for a large amount of intermediate products, and the data locality can be much better. thirdly, because the computations are restricted within a single tile, it is relatively easier to select a fast sparse accumulator for a sparse tile. Our experimental results on two newest NVIDIA GPUs show that our TileSpGEMM outperforms four state-of-the-art SpGEMM methods cuSPARSE, bhSPARSE, NSPARSE and spECK in 139, 138, 127 and 94 out of all 142 square matrices executing no less than one billion flops for an SpGEMM operation, and delivers up to 2.78x, 145.35x, 97.86x and 3.70x speedups, respectively.

关键词： Sparse matrix SpGEMM tiled algorithm GPU

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ParlayANN: Scalable and Deterministic parallel Graph-Based Approximate Nearest Neighbor Search Algorithms 24

ParlayANN: Scalable and Deterministic Parallel Graph-Based A...

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29th acm SIGPLAN Annual symposium on principles and practice of parallel programming (PPoPP)

作者： Manohar, Magdalen Dobson Shen, Zheqi Blelloch, Guy E. Dhulipala, Laxman Gu, Yan Simhadri, Harsha Vardhan Sun, Yihan Carnegie Mellon Univ Pittsburgh PA 15213 USA UC Riverside Riverside CA USA Univ Maryland Baltimore MD USA Microsoft Res Redmond WA USA

ISBN: (纸本)9798400704352

Approximate nearest-neighbor search (ANNS) algorithms are a key part of the modern deep learning stack due to enabling efficient similarity search over high-dimensional vector space representations (i.e., embeddings) of data. Among various ANNS algorithms, graph-based algorithms are known to achieve the best throughput-recall tradeoffs. Despite the large scale of modern ANNS datasets, existing parallel graphbased implementations suffer from significant challenges to scale to large datasets due to heavy use of locks and other sequential bottlenecks, which 1) prevents them from efficiently scaling to a large number of processors, and 2) results in nondeterminism that is undesirable in certain applications. In this paper, we introduce ParlayANN, a library of deterministic and parallel graph-based approximate nearest neighbor search algorithms, along with a set of useful tools for developing such algorithms. In this library, we develop novel parallel implementations for four state-of-the-art graph-based ANNS algorithms that scale to billion-scale datasets. Our algorithms are deterministic and achieve high scalability across a diverse set of challenging datasets. In addition to the new algorithmic ideas, we also conduct a detailed experimental study of our new algorithms as well as two existing non-graph approaches. Our experimental results both validate the effectiveness of our new techniques, and lead to a comprehensive comparison among ANNS algorithms on large scale datasets with a list of interesting findings.

关键词： nearest neighbor search vector search parallel algorithms

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