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检索条件"任意字段=16th Euromicro International Conference on Parallel, Distributed and Network-Based Processing"

共 1090 条记录，以下是11-20 订阅

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Analyzing the performance of hierarchical collective algorithms on ARM-based multicore clusters 30

Analyzing the performance of hierarchical collective algorit...

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30th euromicro international conference on parallel, distributed and network-based processing (PDP)

作者： Utrera, Gladys Gil, Marisa Martorell, Xavier Univ Politecn Cataluna Comp Architecture Dept Barcelona Spain

ISBN: (纸本)9781665469586

MPI is the de facto communication standard library for parallel applications in distributed memory architectures. Collective operations performance is critical in HPC applications as they can become the bottleneck of their executions. the advent of larger node sizes on multicore clusters has motivated the exploration of hierarchical collective algorithms aware of the process placement in the cluster and the memory hierarchy. this work analyses and compares several hierarchical collective algorithms from the literature that do not form part of the current MPI standard. We implement the algorithms on top of OpenMPI using the shared-memory facility provided by MPI-3 at the intra-node level and evaluate them on ARM-based multicore clusters. From our results, we evidence aspects of the algorithms that impact the performance and applicability of the different algorithms. Finally, we propose a model that helps us to analyze the scalability of the algorithms.

关键词： MPI shared-memory collectives HPC

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Decision Tree-based Rule Derivation for Intrusion Detection in Safety-Critical Automotive Systems 30

Decision Tree-Based Rule Derivation for Intrusion Detection ...

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30th euromicro international conference on parallel, distributed and network-based processing (PDP)

作者： Buschlinger, Lucas Rieke, Roland Sarda, Sanat Krauss, Christoph Fraunhofer SIT Darmstadt Germany Fraunhofer Singapore Singapore Darmstadt Univ Appl Sci Darmstadt Germany

ISBN: (纸本)9781665469586

Intrusion Detection Systems (IDSs) are being introduced into safety-critical systems such as connected vehicles. Since the behavior and effectiveness of measures are validated before approval, the decisions made by an IDS are required to be traceable and the IDS also needs to work efficiently on resource-constrained embedded systems. these requirements complicate the direct use of Machine Learning (ML) approaches in IDS design. In this paper, we propose an approach to using ML to generate rules for an efficient rule-based IDS like Snort. Our approach eases the time-consuming and difficult process of creating a rule set. We use decision trees to generate rules that can be used by experts as a basis for creating a rule set for a specific safety critical use case. In addition, we use long short-term memory methods to circumvent the problem of limited training data availability, a common limitation in safety-critical systems. Our implementation and evaluation shows the feasibility of our approach to derive specific IDS rules for such systems.

关键词： intrusion detection rule generation machine learning anomaly detection decision trees long short-term memory automotive security

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Advancing Database System Operators with Near-Data processing 30

Advancing Database System Operators with Near-Data Processin...

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30th euromicro international conference on parallel, distributed and network-based processing (PDP)

作者： dos Santos, Sairo R. Moreira, Francis B. Kepe, Tiago R. Alves, Marco A. Z. Univ Fed Parana Dept Informat Curitiba Parana Brazil Fed Rural Univ Semiarid Dept Exact Sci & Informat Technol Angicos Brazil Fed Inst Parana Curitiba Parana Brazil

ISBN: (纸本)9781665469586

As applications become more data-intensive, issues like von Neumann's bottleneck and the memory wall became more apparent since data movement is the main source of inefficiency in computer systems. Looking to mitigate this issue, Near-Data processing (NDP) moves computation from the processor to the memory, thus reducing the data movement required by many data-intensive workloads. In this paper, we look to database query operators, common targets of NDP research as database systems often need to deal with large amounts of data. We investigate the migration of most time-consuming database operators to Vector-In-Memory Architecture (VIMA), a novel 3D-stacked memory-based NDP architecture. We consider the selection, projection, and bloom join database query operators, commonly used by data analytics applications, comparing VIMA to a high-performance x86 baseline. Our results show speedups of up to 8x for selection, 6x for projection, and 16x for join while consuming up to 99% less energy. To the best of our knowledge, these results outperform the state-of-the-art for these operators on NDP platforms.

关键词： Data analysis Memory management Memory architecture Database systems

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Mitigating Transceiver and Token Controller Permanent Faults in Wireless network-on-Chip 30

Mitigating Transceiver and Token Controller Permanent Faults...

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30th euromicro international conference on parallel, distributed and network-based processing (PDP)

作者： Chatterjee, Navonil Ruaro, Marcelo Martin, Kevin J. M. Diguet, Jean-Philippe CNRS Paris France Univ Bretagne Sud Lab STICC UMR 6285 Lorient France

ISBN: (纸本)9781665469586

Conventional wired network-on-Chip (NoC) designs suffer from performance degradation due to multi-hop long-distance communication. To address such a problem, in the past decade, researchers have been focused on investigating Wireless NoC (WiNoC), which evolved as a viable solution to mitigate this communication bottleneck by using single-hop long-range wireless links. However, many researchers reported that these interconnects may suffer failure due to the complexity of implementation. Although few works in the literature tackle faults in WiNoC, none of them provides a comprehensive study related to channel access mechanisms in the presence of faults. To till this gap, we propose a fault aware WiNoC architecture. We discuss two types of faults in wireless interconnects, namely, transceiver faults and token controller faults. We provide different faultt-olerant techniques to deal with such faults. the proposed FTWiNoC presents, on average, 17.8% and 8.9% improvement in latency compared to two different fault mitigation strategies in the literature.

关键词： Wireless network-on-Chip Fault Detection Fault Mitigating strategies

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Towards Portable Realizations of Winograd-based Convolution with Vector Intrinsics and OpenMP 30

Towards Portable Realizations of Winograd-based Convolution ...

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30th euromicro international conference on parallel, distributed and network-based processing (PDP)

作者： Dolz, Manuel F. Castello, Adrian Quintana-Orti, Enrique S. Univ Jaume 1 Castellon de La Plana Spain Univ Politecn Valencia Valencia Spain

ISBN: (纸本)9781665469586

We take a step forward in the direction of developing high performance codes for the convolution, based on the Winograd transformation, that are easy to customize for different processor architectures. In our approach, augmenting the portability of the solution is achieved via the introduction of vector intrinsics to exploit the SIMI) (single-instruction multiple-data) capabilities of current processors as well as OpenMP pragmas to exploit multi-thread parallelism. While this comes at the cost of sacrificing a fraction of the computational performance, our experimental results on two distinct processors, with Intel Xeon Skylake and ARM Cortex A57 architectures, show that the impact is affordable, and still renders a Winograd-based solution that is competitive with the general method for the convolution based on the so-called im2col transform followed by a matrix-matrix multiplication.

关键词： Convolution Winograd's algorithm high-performance vector intrinsics SIMD floating point units (FPUs) multicore processors

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SeRSS: a storage mesh architecture to build serverless reliable storage services 30

SeRSS: a storage mesh architecture to build serverless relia...

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30th euromicro international conference on parallel, distributed and network-based processing (PDP)

作者： Carrizales-Espinoza, Diana Sanchez-Gallegos, Dante D. Gonzalez-Compean, J. L. Carretero, Jesus Marcelin-Jimenez, Ricardo Cinvestav Tamaulipas Cd Victoria Mexico Univ Carlos III Madrid Madrid Spain Univ Autonoma Metropolitana Iztapalapa Mexico City DF Mexico

ISBN: (纸本)9781665469586

Cloud storage has been the solution for organizations to manage the exponential growth of data observed over the past few years. However, end-users still suffer from side-effects of cloud service outages, which particularly affect edgefog-cloud environments. this paper presents SeRSS, a storage mesh architecture to create and operate reliable, configurable, and flexible serverless storage services for heterogeneous infrastructures. A case study was conducted based on-the-fly building of storage services to manage medical imagery. the experimental evaluation revealed the efficiency of SeRSS to manage and store data in a reliable manner in heterogeneous infrastructures.

关键词： Information dispersal storage systems server-less reliability P2P network

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Predicting the Soft Error Vulnerability of GPGPU Applications 30

Predicting the Soft Error Vulnerability of GPGPU Application...

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30th euromicro international conference on parallel, distributed and network-based processing (PDP)

作者： Topcu, Burak Oz, Isil Izmir Inst Technol Comp Engn Dept Izmir Turkey

ISBN: (纸本)9781665469586

As Graphics processing Units (GPUs) have evolved to deliver performance increases for general-purpose computations as well as graphics and multimedia applications, soft error reliability becomes an important concern. the soft error vulnerability of the applications is evaluated via fault injection experiments. Since performing fault injection takes impractical times to cover the fault locations in complex GPU hardware structures, prediction-based techniques have been proposed to evaluate the soft error vulnerability of General-Purpose GPU (GPGPU) programs based on the hardware performance characteristics. In this work, we propose ML-based prediction models for the soft error vulnerability evaluation of GPGPU programs. We consider both program characteristics and hardware performance metrics collected from either the simulation or the profiling tools. While we utilize regression models for the prediction of the masked fault rates, we build classification models to specify the vulnerability level of the programs based on their silent data corruption (SDC) and crash rates. Our prediction models achieve maximum prediction accuracy rates of 96.6%, 82.6%, and 87% for masked fault rates, SDCs, and crashes, respectively.

关键词： Measurement Graphics processing units Predictive models Fault location Computer crashes Hardware Data models

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GraphDEAR: An Accelerator Architecture for Exploiting Cache Locality in Graph Analytics Applications 30

GraphDEAR: An Accelerator Architecture for Exploiting Cache ...

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30th euromicro international conference on parallel, distributed and network-based processing (PDP)

作者： Hu, Siyi Kondo, Masaaki He, Yuan Sakamoto, Ryuichi Zhang, Hao Zhou, Jun Nakamura, Hiroshi Univ Tokyo Tokyo Japan Keio Univ Yokohama Kanagawa Japan RIKEN Ctr Computat Sci Kobe Hyogo Japan Tokyo Inst Technol Tokyo Japan Gusu Lab Mat Suzhou Peoples R China

ISBN: (纸本)9781665469586

Data structure is the key in Edge Computing where various types of data are continuously generated by ubiquitous devices. Within all common data structures, graphs are used to express relationships and dependencies among human identities, objects, and locations;and they are expected to become one of the most important data infrastructure in the near future. Furthermore, as graph processing often requires random accesses to vast memory spaces, conventional memory hierarchies with caches cannot perform efficiently. To alleviate such memory access bottlenecks in graph processing, we present a solution through vertex accesses scheduling and edge array re-ordering, in parallel with the execution of graph processing application to improve both temporal and spatial locality of memory accesses, especially for edge-centric graphs which are popular means in handling dynamic graphs. Our proposed architecture is evaluated and tested through both trace-based cache simulations and cycle-accurate FPGA-based prototyping. Evaluation results show that our proposal has a potential of significantly reducing the quantity of Miss-Per-Kilo-Instructions (MPKI) for Last Level Cache (LLC) by 56.27% on average.

关键词： graph processing cache data locality domain-specific acceleration

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Evaluating Micro-batch and Data Frequency for Stream processing Applications on Multi-cores 30

Evaluating Micro-batch and Data Frequency for Stream Process...

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30th euromicro international conference on parallel, distributed and network-based processing (PDP)

作者： Garcia, Adriano Marques Griebler, Dalvan Schepke, Claudio Fernandes, Luiz Gustavo L. Pontifical Catholic Univ Rio Grande Sul PUCRS Sch Technol Porto Alegre RS Brazil Tres Maio Fac SETREM Lab Adv Res Cloud Comp LARCC Tres De Maio Brazil Fed Univ Pampa UNIPAMPA Alegrete Brazil

ISBN: (纸本)9781665469586

In stream processing, data arrives constantly and is often unpredictable. It can show large fluctuations in arrival frequency, size, complexity, and other factors. these fluctuations can strongly impact application latency and throughput, which are critical factors in this domain. therefore, there is a significant amount of research on self-adaptive techniques involving elasticity or micro-batching as a way to mitigate this impact. However, there is a lack of benchmarks and tools for helping researchers to investigate micro-batching and data stream frequency implications. In this paper, we extend a benchmarking framework to support dynamic micro-batching and data stream frequency management. We used it to create custom benchmarks and compare latency and throughput aspects from two different parallel libraries. We validate our solution through an extensive analysis of the impact of micro-batching and data stream frequency on stream processing applications using Intel TBB and FastFlow, which are two libraries that leverage stream parallelism on multi-core architectures. Our results demonstrated up to 33% throughput gain over latency using micro-batches. Additionally, while TBB ensures lower latency, FastFlow ensures higher throughput in the parallel applications for different data stream frequency configurations.

关键词： Fluctuations distributed databases Benchmark testing parallel processing Elasticity throughput Libraries

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A Neural network to Estimate Isolated Performance from Multi-Program Execution 30

A Neural Network to Estimate Isolated Performance from Multi...

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30th euromicro international conference on parallel, distributed and network-based processing (PDP)

作者： Lurbe, Manel Feliu, Josue Petit, Salvador Gomez, Maria E. Sahuquillo, Julio Univ Politecn Valencia Dept Informat Sistemas & Computadores Valencia Spain Univ Murcia Dept Ingn & Tecnol Computadores Murcia Spain

ISBN: (纸本)9781665469586

When multiple applications are running on a platform with shared resources like multicore CPUs, the behaviour of the running application can be altered by the co-runners. In this case, the system resources need to be managed (e.g. by repartitioning the cache space, re-schedule applications in distinct cores, modifying the prefetcher configuration, etc.) to reduce the inter-application interference in order to minimize the performance losses over isolated execution. In this context, a main challenge in different computing scenarios like the public cloud or soft real-time systems is knowing the performance impact of a given management action on each application with respect to its isolated execution. With this aim, in this work we present a neural network-based approach that estimates the performance an application would have had in isolation from multi-program executions. Experimental results show that the proposal dynamically adapts to changes in application behavior. On average, the predicted performance presents an error deviation by 11.7% and 2.3% for MAPE and MSE respectively.

关键词： IBM POWER8 System Performance Inter-Application Interference Machine Learning Deep Learning

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