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Statistical placement for FPGAs considering process variation

IET COMPUTERS AND DIGITAL TECHNIQUES 2007年第4期1卷 267-275页

作者： Lin, Y. Hutton, M. He, L. Univ Calif Los Angeles Dept Elect Engn Los Angeles CA 90095 USA Altera Corp San Jose CA 95134 USA

Process variations affecting timing and power is an important issue for modem integrated circuits in nanometre technologies. field programmable gate arrays (FPGA) are similar to application-specific integrated circuit (ASIC) in their susceptibility to these issues, but face unique challenges in that critical paths are unknown at test time. the first in-depth study on applying statistical timing analysis with cross-chip and on-chip variations to speed-binning and guard-banding in FPGAs has been presented. Considering the uniqueness of re-programmability in FPGAs, the effects of timing-model with guard-banding and speed-binning on statistical performance and timing yield are quantified. A new variation aware statistical placement, which is the first statistical algorithm for FPGA layout and achieves a yield loss of 29.7% of the original yield loss with guard-banding and a yield loss of 4% of the original one with speed-binning for Microelectronics Center of North Carolina (MCNC) and Quartus University Interface Program (QUIP) designs, has also been developed.

关键词： integrated circuit layout statistical analysis statistical timing analysis logic design on-chip variations statistical placement process variation cross-chip speed-binning modern integrated circuits nanometre technologies timing guard-banding FPGA layout application-specific integrated circuit field programmable gate arrays

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TMD-MPI:: An MPI implementation for multiple processors across multiple FPGAS

TMD-MPI:: An MPI implementation for multiple processors acro...

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16th international conference on field programmable logic and applications

作者： Saldana, Manuel Chow, Paul Univ Toronto Dept Elect & Comp Engn Toronto ON M5S 3G4 Canada

ISBN: (纸本)9781424403127

With current FPGAs, designers can now instantiate several embedded processors, memory units, and a wide variety of IP blocks to build a single-chip, high-performance multiprocessor embedded system. Furthermore, Multi-FPGA systems can be built to provide massive parallelism given an efficient programming model. In this paper, we present a lightweight subset implementation of the standard message-passing interface, MPI, that is suitable for embedded processors. It does not require an operating system and uses a small memory footprint. With our MPI implementation (TMD-MPI), we provide a programming model capable of using multiple-FPGAs that hides hardware complexities from the programmer, facilitates the development of parallel code and promotes code portability. To enable intra-FPGA and inter-FPGA communications, a simple Network-on-Chip is also developed using a low overhead network packet protocol. Together, TMD-MPI and the network provide a homogeneous view of a cluster of embedded processors to the programmer. Performance parameters such as link latency, link bandwidth, and synchronization cost are measured by executing a set of microbenchmarks.

关键词： field programmable gate arrays (FPGA)

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An FPGA implementation of high throughput stochastic simulator for large-scale biochemical systems

An FPGA implementation of high throughput stochastic simulat...

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16th international conference on field programmable logic and applications

作者： Yoshimi, Masato Osana, Yasunori Iwaoka, Yow Nishikawa, Yuri Kojima, Toshinori Funahashi, Akira Hiroi, Noriko Shibata, Yuichiro Iwanaga, Naoki Kitano, Hiroaki Amano, Hideharu Keio Univ Yokohama Kanagawa 223 Japan ERATO-SORST JST Kitano Symbiotic Syst Project Tokyo Japan Nagasaki Univ Nagasaki Japan

ISBN: (纸本)9781424403127

Stochastic simulation of biochemical systems has become one of major approaches to study life processes as system, yet is a computational challenge to run the simulation due to its vast calculation cost. this paper shows the implementation and evaluation of a stochastic simulation algorithm (SSA) called "First Reaction Method" on an FPGA-based biochemical simulator. It achieves high throughput by (1) consecutively throwing data into deeply-pipelined floating point arithmetic units, and (2) by distruibuting multiple simulators for parallel execution. As the result of evaluation on an FPGA-based simulation platform called ReCSiP2, the simulator outperforms execution on Xeon 2.80 GHz by approximately 80 times, even with large-scale biochemical systems.

关键词： field programmable gate arrays (FPGA)

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Execution objects for dynamically reconfigurable FPGA systems

Execution objects for dynamically reconfigurable FPGA system...

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16th international conference on field programmable logic and applications

作者： Oliver, Timothy F. Maskell, Douglas L. Nanyang Technol Univ Ctr High Performance Embedded Syst Sch Comp Engn Singapore 2263 Singapore

ISBN: (纸本)9781424403127

this paper explores the use of pre-routed cores as execution objects in an object-oriented programming model and execution environment for dynamic computing on FPGA. In order to maintain FPGA computing performance it is crucial to thoroughly analyze the issues at the lowest level of device detail in order to ensure that computing circuit encapsulation is as efficient as possible. We present the first methodology that allows a core to scale its interface bandwidth to the maximum available in a routing channel. Cores can be constructed independently from the rest of the system using a framework that is independent of the method used to place and route primitive components within the core. We use an architecture model and CAD tools that mirror those used in industry. Abutting cores are instantly connected by co-location of interface wires. Eliminating run-time routing drastically reduces the time taken to construct a system using a set of cores. We illustrate how, although pre-routing has an adverse impact on core performance by up to 14%, it can improve functional density by up to six times for rapid reconfiguration.

关键词： field programmable gate arrays (FPGA)

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A thERMAL MANAGEMENT AND PROFILING MEthOD FOR RECONFIGURABLE HARDWARE applications

<bold>A THERMAL MANAGEMENT AND PROFILING METHOD FOR RECONFIG...

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16th international conference on field programmable logic and applications

作者： Jones, Phillip H. Lockwood, John W. Cho, Young H. Washington Univ Appl Res Lab St Louis MO 63130 USA

ISBN: (纸本)9781424403127

Given large circuit sizes, high clock frequencies, and possibly extreme operating environments, field programmable Gate Arrays (FPGAs) are capable of heating beyond their designed thermal limits. As new circuits are developed for FPGAs and deployed remotely, engineers are challenged to determine in advance if the device will operate within recommended thermal ranges. ne amount of power consumed by the circuit depends on how an algorithm is compiled into hardware, how the circuit is placed and routed, and the patterns of data that pass through the system. the amount of heat that can be dissipated depends on the thermal transfer characteristics of the package, the air flow that passes over the package, and the ambient temperature of the remote systems. Rather than designing a system to handle unreasonable worst-case situations, we have implemented a thermal management system that continuously monitors the temperature of the FPGA and reprograms the device if the temperate approaches the outer limits of safe operating conditions. Our system measures the junction temperature of a Xilinx Virtex FPGA using a built-in thermal diode. Using the temperature monitoring mechanism, we have studied the steady-state and transient conditions of multiple benchmark circuits implemented in an FPGA logic on the field-programmable Port Extender (FPX) development platform. We observed properties of these benchmark circuits that enable us to predict power and thermal characteristics for real applications. We propose a Dynamic thermal Management (DTM) strategy for FPGAs based on temperature feedback.

关键词： t

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High performance scientific computing using FPGAS with IEEE floating point and logarithmic arithmetic for lattice QCD

High performance scientific computing using FPGAS with IEEE ...

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16th international conference on field programmable logic and applications

作者： Callanan, Owen Gregg, David Nisbet, Andy Peardon, Mike Univ Dublin Trinity Coll Dept Comp Sci Dublin 2 Ireland Manchester Metropolitan Univ Dept Comp Math Manchester M15 6BH Lancs England Trinity Coll Dublin Dept Math Dublin Ireland

ISBN: (纸本)9781424403127

the recent development of large FPGAs along with the availability of a variety of floating point cores have made it possible to implement high-performance matrix and vector kernel operations on FPGAs. In this paper we seek to evaluate the performance of FPGAs for real scientific computations by implementing Lattice QCD, one of the classic scientific computing problems. Lattice QCD is the focus of considerable research work worldwide, including two custom ASIC-based solutions. Our results give significant insights into the usefulness of FPGAs for scientific computing. We also seek to evaluate two different number systems available for running scientific computations on FPGAs. To do this we implement FPGA based lattice QCD processors using both double precision IEEE floating point and single precision equivalent Logarithmic Number System (INS) cores and compare their performance with that of two lattice QCD targeted ASIC based solutions and with PC cluster based solutions.

关键词： field programmable gate arrays (FPGA)

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Boot time Bitstream Authentication for FPGAs 16

Boot time Bitstream Authentication for FPGAs

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IEEE 16th international conference on Smart Cities - Improving Quality of Life Using ICT and IoT and AI (HONET-ICT)

作者： Siddiqui, Ali Shuja Gui, Yutian Saqib, Fareena Univ North Carolina Charlotte Charlotte NC 28223 USA

ISBN: (纸本)9781728139715

Major commercial field programmable Gate Arrays (FPGAs) vendors provide encryption and authentication for programmable logic fabric (PL) bitstream using AES and RSA respectively. they are limited in scope of security that they provide and have proven to be vulnerable to different attacks. As-such, in-field deployed devices are susceptible to attacks where either a configuration bitstream, application software or dynamically reconfigurable bitstreams can be maliciously replaced. this hardware demo presents a framework for secure boot and runtime authentication for FPGAs. the presented system employs on-board cryptographic mechanisms and third-party established architectures such as Trusted Platform Module (TPM). the scope of this hardware demo is of systems level.

关键词： field programmable gate arrays bit stream Authentication applications software cryptography AES gene Auger electron spectroscopy system level Vulnerable Antimicrobial Susceptibility Result Trusted Platform Module

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Design of a field-programmable dual-precision floating-point arithmetic unit

Design of a field-programmable dual-precision floating-point...

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16th international conference on field programmable logic and applications

作者： Diniz, Pedro C. Govindu, Gokul USC Inst Informat Sci 4676 Admiralty WaySuite 1001 Marina Del Rey CA 90292 USA Univ Southern Calif Dept Elect Engn Los Angeles CA 90089 USA

ISBN: (纸本)9781424403127

the growth in FPGA capacity and the inclusion of embedded arithmetic cores has enabled the use of these devices for general purpose floating-point computing. Despite their clock rate handicap with respect to contemporary general-purpose processors, these devices can be field-programmable to meet the precision requirements and operator-level parallelism of a specific computation. In this paper we describe and evaluate the performance of dual-precision, pipelined, floating-point arithmetic cores for addition, multiplication and division. Each of these arithmetic cores can be switched at run-time to perform either one double-precision operation, or with the same hardware resources, perform two single-precision operations. We also implemented quad-precision cores which can be switched to perform either one quad-precision operation or two double-precision operations. As an application of these cores, we describe and evaluate the performance potential of a custom, but flexible, vector processing units as part of a system-level architecture targeting a Xilinx Virtex-II Pro (TM) 100 FPGA device connected to multiple SRAM banks.

关键词： Digital arithmetic

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Improving usability of FPGA-based reconfigurable computers through operating system support

Improving usability of FPGA-based reconfigurable computers t...

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16th international conference on field programmable logic and applications

作者： So, Hayden Kwok-Hay Brodersen, Robert W. Univ Calif Berkeley Berkeley CA 94720 USA

ISBN: (纸本)9781424403127

Advances in FPGA-based reconfigurable computers have made them a viable computing platform for a vast variety of computation demanding areas such as bioinformatics, speech recognition, and high-end digital signal processing. the lack of common, intuitive operating system support, however, hinders their wide deployment. this paper presents BORPH, an operating system framework for FPGA-based reconfigurable computers with a goal to ease and accelerate development of high-level applications to run on these computers. It provides kernel support for FPGA resources by extending a standard Linux operating system. Users therefore compile and execute hardware processes on FPGA resources the same way they run software processes on conventional processor-based systems. the operating system offers run-time general file system support to hardware processes as if they were software. Furthermore, a virtual file system is built to allow access to memories and registers defined in the FPGA, which provides communication links with running hardware processes. Increased productivities have been observed for high-level application developers, who have few previous experiences in hardware design, to implement complex mixed software/hardware designs on a FPGA-based reconfigurable computer running BORPH.

关键词： field programmable gate arrays (FPGA)

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FPGA design of a H.264/AVC main profile decoder for HDTV

FPGA design of a H.264/AVC main profile decoder for HDTV

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16th international conference on field programmable logic and applications

作者： Agostini, Luciano V. Azevedo Filho, Arnaldo P. Rosa, Vagner S. Berriel, Eduardo A. Santos, Tatiana G. S. Bampi, Sergio Susin, Altamiro A. Univ Fed Rio Grande do Sul Inst Informat Porto Alegre RS Brazil Univ Fed Rio Grande do Sul Elect Engn Dept Porto Alegre RS Brazil

ISBN: (纸本)9781424403127

this paper presents the architecture, design, validation, and prototyping of inverse transforms and quantization, intra prediction, motion compensation and loop filter, for a main profile H.264/AVC decoder. these architectures were designed to reach high throughputs and to be easily integrated with the other H.264/AVC modules. the architectures, all fully H.264/AVC compliant, were completely described in VHDL and further validated through simulations down to prototyping. the architectures were prototyped using a Digilent XUP V2P board, containing a Virtex-H Pro XC2VP30 Xilinx FPGA. the post place-and-route synthesis results indicate that the designed architectures are able to process 114 million of samples per second and, in the worst case, they are able to process 64 HDTV frames (1080x1920) per second, allowing their use in H.264/AVC decoders targeting real time HDTV applications.

关键词： field programmable gate arrays (FPGA)

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