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检索条件"任意字段=16th International Conference on Field Programmable Logic and Applications"

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Tetracycline Intelligent Target-Inducing logic Gate Based on Triple-Stranded DNA Nanoswitch 16th

Tetracycline Intelligent Target-Inducing Logic Gate Based on...

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16th international conference on Bio-Inspired Computing: theories and applications, BIC-TA 2021

作者： Xi, Sunfan Wang, Yue Hu, Mengyang Wang, Luhui Cheng, Meng Dong, Yafei College of Life Science Shaanxi Normal University Shaanxi Xi’an710119 China School of Computer Science Shaanxi Normal University Shaanxi Xi’an710119 China

ISBN: (纸本)9789811912559

A previously unreported three-strand DNA (ts-DNA) non-metal structure with hairpin structure was designed based on a strategy of logic switching and tetracycline (TC) signaling molecule switching. Will target and TC-binding aptamer (TBA) is the combination of body, and its relation with three functional chain DNA conformation, with programmable DNA sensor signal by FAM input molecule fluorescence emission monitoring. After the combination, the input signal is converted to a fluorescent signal to perform a logical operation. By introducing a novel nanomaterial, graphene oxide (GO), as a signal regulator, the fluorescence response changed by intermolecular interactions is the key to achieving logical calculation. the harm of tetracycline can generally cause kidney damage, ear damage, gastrointestinal adverse reactions, skin allergies, *** tetracycline as a molecular trigger to induce conformational changes in DNA, a logical operation target detection method was constructed. In addition, nanoscale devices can be reconfigured and optimized to accommodate additional logical calculations and target detection. © 2022, Springer Nature Singapore Pte Ltd.

关键词： DNA

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Fitop-Trans: Maximizing Transformer Pipeline Efficiency through Fixed-Length Token Pruning on FPGA

Fitop-Trans: Maximizing Transformer Pipeline Efficiency thro...

引用

international conference on field programmable logic and applications

作者： Kejia Shi Manting Zhang Keqing Zhao Xiaoxing Wu Yang Liu Jun Yu Kun Wang School of Microelectronics Fudan University Shanghai China

ISBN: (数字)9798331530075

ISBN: (纸本)9798331530082

Recent years have witnessed Transformers emerge as a groundbreaking innovation in the Natural Language Processing (NLP) field. Unlike Recurrent Neural Network (RNN) models, Transformers process sequences in parallel, boosting accuracy for longer sequences. However, Transformers face challenges with extended processing time. this is particularly due to the requirement of padding inputs to match the longest sentence in a batch, thereby increasing computational demands. In this paper, we present Fitop-Trans, the first algorithm-hardware co-optimized framework using Fixed-Length Token Pruning strategy while deploying Transformers on FPGA. At the algorithmic level, we propose Fixed-Length Token Pruning. It is a novel pruning method which can maximize hardware efficiency in attention computation, aimed at eliminating unimportant tokens before the first layer. On the hardware side, a token selector is designed for Fixed-Length Token Pruning, which minimizes off-chip memory traffic. In addition, a partitionable Systolic Array (SA) is adopted, which is capable of handling varying input lengths and maximizing Digital Signal Processor (DSP) resource utilization. Furthermore, a scheduling module is designed to optimize hardware resource allocation and enhance pipeline attention throughput. Experimental results reveal that our hardware design on FPGA achieves a speedup of $580 \times$ and $6.39 \times$ in latency compared to Intel Xeon Gold CPU and NVIDIA GeForce RTX 3090.

关键词： Gold Recurrent neural networks Processor scheduling Pipelines Signal processing algorithms Transformers Hardware Natural language processing Resource management field programmable gate arrays

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Leveraging Dual Output LUTs with Pipelining for Efficient BCD to Binary Converter on FPGA

Leveraging Dual Output LUTs with Pipelining for Efficient BC...

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international conference on VLSI Design

作者： Santosh Kumar Ayan Palchaudhuri Department of Electronics & Communication Engineering School of Electrical and Computer Sciences Indian Institute of Technology Bhubaneswar Argul Khordha Odisha India

ISBN: (数字)9798331522445

ISBN: (纸本)9798331522452

Decimal operands expressed in BCD is often the convenient data format used in embedded systems and human-centric applications. For optimized arithmetic computation on hardware where binary arithmetic can be conveniently processed, input BCD operands should first be converted to binary. this paper explores the versatility of FPGA specific logic primitives, namely the dual output Look-Up Tables (LUTs) and carry chain for efficient realization of parallel and pipelined architectures to optimize throughput and resource utilization for BCD to binary conversion architectures. Primitive instantiation was adopted to ensure design optimization, which involved direct configuration of FPGA logic primitives. the utility ratio of the configured FPGA primitives was increased to extract the best performance. Experimental results demonstrate a good trade-off in speed and area for our proposed architectures when compared with existing designs. We have investigated multiple implementation variants for the addition tree, which serves as a crucial functional logic block in the converter design.

关键词： Embedded systems Computer architecture Very large scale integration throughput Table lookup logic field programmable gate arrays Adders Optimization Arithmetic

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Small Area Footprint FPGA Architecture for Approximate atan2(a, b) Algorithm 9

Small Area Footprint FPGA Architecture for Approximate atan2...

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9th IEEE Uttar Pradesh Section international conference on Electrical, Electronics and Computer Engineering, UPCON 2022

作者： Kumar, Bharat Sarawadekar, Kishor Dept. of Electronics Engineering Varanasi India

ISBN: (数字)9798350332506

ISBN: (纸本)9798350332506

Arctangent or inverse tangent function has numerous applications like gradient-based feature extraction, phase noise determination, range rate measurement etc. this paper presents a small area footprint hardware architecture for computing the arctangent of a complex number. the proposed method uses numerical approximation and LUTs used to improve the accuracy of the results obtained. Single-precision floating-point representation is used to implement the proposed design and the results demonstrate very good accuracy with an error of about ±0.0004 radian with 256×32 bits memory size. the proposed architecture is implemented on Nexys4 DDR FPGA board using Verilog and it operates at 19.8 MHz. Integrated logic Analyzer (ILA) is used to debug and validate the proposed design. Further, it is observed that results obtained with the proposed design are in agreement with the Matlab simulation results. © 2022 IEEE.

关键词： field programmable gate arrays (FPGA)

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A Software-programmable Neural Processing Unit for Graph Neural Network Inference on FPGAs

A Software-Programmable Neural Processing Unit for Graph Neu...

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international conference on field programmable logic and applications

作者： Taikun Zhang Andrew Boutros Sergey Gribok Kwadwo Boateng Vaughn Betz Department of Electrical and Computer Engineering University of Toronto Toronto ON Canada Programmable Solutions Group Intel Corporation

ISBN: (数字)9798331530075

ISBN: (纸本)9798331530082

Graph neural networks (GNNs) are a widely-used class of deep learning (DL) models for learning latent representations of graph-structured data for a variety of node/graph-level prediction tasks, some of which require real-time low latency inference. Most existing GNN accelerators rely on preprocessing input graphs on a host/embedded CPU to parallelize computations on different sub-graphs, making them unsuitable for real-time use cases. Others are extremely specialized streaming pipelines for only a specific type of GNN and therefore suffer from long FPGA bitstream compile times when the model is updated and cannot be used in applications that combine GNNs with other classes of DL models. In this work, we enhance the neural processing unit (NPU) FPGA overlay architecture, instruction set, and software stack to support a variety of GNN models. We achieve this without sacrificing the NPU flexibility; our enhanced NPU can be programmed purely through software to accelerate different GNNs or any of its originally supported DL workloads (e.g. MLPs, RNNs, GRUs, LSTMs). In addition, this flexibility enables our NPU software compiler to generate GNN kernels with different performance targets (throughput-optimized vs. latency-optimized) by exploiting different dimensions of compute parallelism on the same overlay architecture. Besides the flexibility benefits, our NPU implemented on an Intel Stratix 10 NX (14 nm) FPGA can process $7.8 \times$ more graphs per second at a similar latency on average compared to a state-of-the-art model-specific FPGA accelerator targeting real-time applications on an AMD Ultrascale+ same-generation FPGA. It also achieves 5.8 $\times$ higher throughput compared to an Nvidia RTX A6000 GPU (8 nm) and $2.6 \times$ lower latency than a state-of-the-art accelerator that combines CPU-based graph preprocessing with AMD Versal (7 nm) fabric and AI engine compute. Finally, we present a case study for using our enhanced NPU in real-time GNNbased multi-input

关键词： Computational modeling Data preprocessing Full stack Computer architecture throughput Graph neural networks Real-time systems Software Vectors field programmable gate arrays

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LORA: A Latency-Oriented Recurrent Architecture for GPT Model on Multi-FPGA Platform with Communication Optimization

LORA: A Latency-Oriented Recurrent Architecture for GPT Mode...

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international conference on field programmable logic and applications

作者： ZhenDong Zheng Qianyu Cheng Teng Wang Lei Gong Xianglan Chen Cheng Tang Chao Wang Xuehai Zhou School of Computer Science and Technology Suzhou Institute for Advanced Research University of Science and Technology of China

ISBN: (数字)9798331530075

ISBN: (纸本)9798331530082

Large Language Models (LLMs) have been widely deployed in data centers to provide various services, among which the most representative is the Generative Pre-trained Transformer (GPT). the GPT model has heavy memory and computing overhead, and its inference process has two stages with distinct computing characteristics: Prefill and Decode. Utilizing existing GPUs and FPGA accelerators to construct a platform for deploying GPT in data centers faces the challenges of needing more effective synchronization schemes or structures with higher computational intensity. this paper proposes LORA, a low latency end-to-end GPT acceleration platform utilizing multiple FPGAs. Firstly, we optimize the synchronization timing of the GPT model to reduce the computation and communication overhead. Secondly, we devise some efficient synchronization steps for specific layers of the GPT model that overlap part of the computation and communication delay to improve the latency of our platform. Finally, we deploy recurrent structures on each FPGA to accelerate the different stages of the GPT model. Implemented on the Xilinx Alveo U280 FPGAs, LORA achieves an average $11.1 \times$ speedup over NVIDIA V100 GPUs on the modern GPT-2 model. Compared to the existing multi-FPGA accelerator appliance, LORA shows performance improvements of up to $4 \times$ and $2.7 \times$ in the Prefill and Decode stages.

关键词： Data centers Computational modeling LoRa Prototypes Transformers Data models Synchronization Low latency communication field programmable gate arrays Optimization

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NeuraLUT: Hiding Neural Network Density in Boolean Synthesizable Functions

NeuraLUT: Hiding Neural Network Density in Boolean Synthesiz...

引用

international conference on field programmable logic and applications

作者： Marta Andronic George A. Constantinides Department of Electrical and Electronic Engineering Imperial College London UK

ISBN: (数字)9798331530075

ISBN: (纸本)9798331530082

field-programmable Gate Array (FPGA) accelerators have proven successful in handling latency- and resource-critical deep neural network (DNN) inference tasks. Among the most computationally intensive operations in a neural network (NN) is the dot product between the feature and weight vectors. thus, some previous FPGA acceleration works have proposed mapping neurons with quantized inputs and outputs directly to lookup tables (LUTs) for hardware implementation. In these works, the boundaries of the neurons coincide with the boundaries of the LUTs. We propose relaxing these boundaries and mapping entire sub-networks to a single LUT. As the sub-networks are absorbed within the LUT, the NN topology and precision within a partition do not affect the size of the lookup tables generated. therefore, we utilize fully connected layers with floating-point precision inside each partition, which benefit from being universal function approximators, but with rigid sparsity and quantization enforced between partitions, where the NN topology becomes exposed to the circuit topology. Although cheap to implement, this approach can lead to very deep NNs, and so to tackle challenges like vanishing gradients, we also introduce skip connections inside the partitions. the resulting methodology can be seen as training DNNs with a specific FPGA hardware-inspired sparsity pattern that allows them to be mapped to much shallower circuit-level networks, thereby significantly improving latency. We validate our proposed method on a known latency-critical task, jet substructure tagging, and on the classical computer vision task, digit classification using MNIST. Our approach allows for greater function expressivity within the LUTs compared to existing work, leading to up to $4.3 \times$ lower latency NNs for the same accuracy.

关键词： Training Quantization (signal) Neurons Artificial neural networks Tagging Vectors Table lookup Topology field programmable gate arrays Biological neural networks

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New FPGA architecture for 8, 16 and 24 bit chaotic interleaver. 5

New FPGA architecture for 8, 16 and 24 bit chaotic interleav...

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5th international conference on Engineering Technology and its applications, IICETA 2022

作者： Humadi, Zeina Abdullah Al-Doori, Qusay F. University of Technology Control and Systems Engineering Department Baghdad Iraq

ISBN: (纸本)9781665472159

In a digital system, the interleaver is essential. It's widely used to enhance the effectiveness of forward error correction codes. A lot of research has shown the efficiency of the chaotic interleaver in correcting the 2d burst error. We used this type of interleaver based on the baker map equation. the problem with using such encoding technique is in adaptive in multi standard systems stream of bit can be 8, 16, and 24 hence there is a need for three types of interleavers which increase the complexity of the system. In this paper, an efficient chaotic interleaver model was presented with a new FPGA architecture that includes 8-, 16- and 24-bit square matrix. this new design makes the system easily deal with more than one size of the matrix input to the system and this is called a multi-standard system instead of having each size separately in its own design. the results were obtained using the Xilinx ISE 14.7 design suite. In the system generator, the generated waveforms are viewed using the scope block of Simulink. © 2022 IEEE.

关键词： field programmable gate arrays (FPGA)

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HASS: Hardware-Aware Sparsity Search for Dataflow DNN Accelerator

HASS: Hardware-Aware Sparsity Search for Dataflow DNN Accele...

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international conference on field programmable logic and applications

作者： Zhewen Yu Sudarshan Sreeram Krish Agrawal Junyi Wu Alexander Montgomerie-Corcoran Cheng Zhang Jianyi Cheng Christos-Savvas Bouganis Yiren Zhao Imperial College London UK University of Cambridge UK

ISBN: (数字)9798331530075

ISBN: (纸本)9798331530082

Deep Neural Networks (DNNs) excel in learning hierarchical representations from raw data, such as images, audio, and text. To compute these DNN models with high performance and energy efficiency, these models are usually deployed onto customized hardware accelerators. Among various accelerator designs, dataflow architecture has shown promising performance due to its layer-pipelined structure and its scalability in data *** weights and activations sparsity can further enhance memory storage and computation efficiency. However, existing approaches focus on exploiting sparsity in non-dataflow accelerators, which cannot be applied onto dataflow accelerators because of the large hardware design space introduced. As such, this could miss opportunities to find an optimal combination of sparsity features and hardware *** this paper, we propose a novel approach to exploit unstructured weights and activations sparsity for dataflow accelerators, using software and hardware co-optimization. We propose a Hardware-Aware Sparsity Search (HASS) to systematically determine an efficient sparsity solution for dataflow accelerators. Over a set of models, we achieve an efficiency improvement ranging from $1.3 \times$ to $4.2 \times$ compared to existing sparse designs, which are either non-dataflow or non-hardware-aware. Particularly, the throughput of MobileNetV3 can be optimized to 4895 images per second. HASS is open-source: https://***/Yu-Zhewen/HASS

关键词： Systematics Computational modeling Scalability Heuristic algorithms Memory management Artificial neural networks throughput Software logic Optimization

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Low Precision Networks for Efficient Inference on FPGAs 20

Low Precision Networks for Efficient Inference on FPGAs

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20th international conference on field-programmable Technology (ICFPT)

作者： Abra, Ruth Denisenko, Dmitry Allen, Richard Vanderhoek, Tim Wolstencroft, Sarah Gibson, Mark Intel Corp Programmable Solut Grp Santa Clara CA 95051 USA Royal Holloway Univ London Egham Surrey England Univ Reading Reading Berks England

ISBN: (纸本)9781665420105

Block Floating Point (BFP) is a type of quantization that combines high dynamic range with low-cost inference. BFP can be implemented efficiently on FPGA hardware and, at low precision, halves the logic footprint versus blocked FP16 while maintaining accuracy. Moving to very low precision halves the logic footprint again and retraining allows the recovery of any accuracy lost in transition. this paper describes our approach to achieving target accuracy and FPGA resource usage in a low-precision end-to-end AI solution. We go on to investigate the effects of retraining with our software model that replicates the low-level implementation of BFP on FPGA. Our solution allows efficacy testing for the quantization of custom networks and provides accuracy indications and resource usage for the final application. Using our solution, we were able to quantize ResNet 50, SSD300 and UNet to int5/4bfp precision without losing accuracy while reducing FPGA resources and improving performance.

关键词： AI Block Floating Point CNNs Low Precision Quantization FPGA

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