咨询与建议

限定检索结果

文献类型

  • 2,085 篇 会议
  • 31 篇 期刊文献
  • 4 册 图书

馆藏范围

  • 2,120 篇 电子文献
  • 0 种 纸本馆藏

日期分布

学科分类号

  • 1,363 篇 工学
    • 1,143 篇 计算机科学与技术...
    • 757 篇 软件工程
    • 452 篇 电气工程
    • 226 篇 电子科学与技术(可...
    • 90 篇 信息与通信工程
    • 79 篇 控制科学与工程
    • 41 篇 机械工程
    • 38 篇 仪器科学与技术
    • 32 篇 动力工程及工程热...
    • 29 篇 建筑学
    • 19 篇 土木工程
    • 19 篇 生物工程
    • 17 篇 核科学与技术
    • 15 篇 光学工程
    • 13 篇 生物医学工程(可授...
    • 9 篇 材料科学与工程(可...
    • 9 篇 安全科学与工程
    • 8 篇 交通运输工程
    • 6 篇 石油与天然气工程
  • 181 篇 理学
    • 104 篇 数学
    • 43 篇 物理学
    • 22 篇 生物学
    • 20 篇 系统科学
    • 13 篇 统计学(可授理学、...
    • 8 篇 化学
  • 53 篇 管理学
    • 41 篇 管理科学与工程(可...
    • 21 篇 工商管理
    • 15 篇 图书情报与档案管...
  • 17 篇 法学
    • 15 篇 社会学
  • 13 篇 医学
  • 11 篇 经济学
    • 11 篇 应用经济学
  • 6 篇 军事学
  • 5 篇 农学
  • 3 篇 教育学

主题

  • 945 篇 field programmab...
  • 735 篇 field programmab...
  • 322 篇 hardware
  • 172 篇 computer archite...
  • 145 篇 logic gates
  • 130 篇 table lookup
  • 115 篇 clocks
  • 96 篇 throughput
  • 94 篇 random access me...
  • 85 篇 routing
  • 82 篇 software
  • 80 篇 acceleration
  • 75 篇 delays
  • 73 篇 optimization
  • 67 篇 kernel
  • 62 篇 switches
  • 61 篇 registers
  • 61 篇 logic
  • 56 篇 algorithm design...
  • 52 篇 parallel process...

机构

  • 17 篇 univ toronto dep...
  • 9 篇 imperial coll lo...
  • 9 篇 ecole polytech f...
  • 8 篇 department of co...
  • 8 篇 tokyo inst techn...
  • 7 篇 univ british col...
  • 7 篇 school of comput...
  • 7 篇 brigham young un...
  • 7 篇 imperial coll lo...
  • 6 篇 univ tsukuba tsu...
  • 6 篇 xilinx inc 2100 ...
  • 6 篇 university of ch...
  • 6 篇 department of el...
  • 6 篇 univ warwick sch...
  • 6 篇 xilinx inc san j...
  • 5 篇 univ manchester ...
  • 5 篇 department of el...
  • 5 篇 univ toronto dep...
  • 5 篇 department of el...
  • 5 篇 fudan univ state...

作者

  • 31 篇 luk wayne
  • 21 篇 maruyama tsutomu
  • 16 篇 koch dirk
  • 13 篇 ienne paolo
  • 12 篇 wayne luk
  • 12 篇 wilton steven j....
  • 12 篇 betz vaughn
  • 11 篇 fahmy suhaib a.
  • 11 篇 cheung peter y. ...
  • 11 篇 chow paul
  • 10 篇 constantinides g...
  • 9 篇 vaughn betz
  • 9 篇 prasanna viktor ...
  • 8 篇 kapre nachiket
  • 8 篇 suhaib a. fahmy
  • 8 篇 alonso gustavo
  • 8 篇 hutchings brad
  • 8 篇 paolo ienne
  • 8 篇 habib mehrez
  • 8 篇 amano hideharu

语言

  • 2,105 篇 英文
  • 9 篇 其他
  • 5 篇 中文
  • 1 篇 俄文
检索条件"任意字段=16th International Conference on Field Programmable Logic and Applications"
2120 条 记 录,以下是121-130 订阅
排序:
Tetracycline Intelligent Target-Inducing logic Gate Based on Triple-Stranded DNA Nanoswitch  16th
Tetracycline Intelligent Target-Inducing Logic Gate Based on...
收藏 引用
16th international conference on Bio-Inspired Computing: theories and applications, BIC-TA 2021
作者: Xi, Sunfan Wang, Yue Hu, Mengyang Wang, Luhui Cheng, Meng Dong, Yafei College of Life Science Shaanxi Normal University Shaanxi Xi’an710119 China School of Computer Science Shaanxi Normal University Shaanxi Xi’an710119 China
A previously unreported three-strand DNA (ts-DNA) non-metal structure with hairpin structure was designed based on a strategy of logic switching and tetracycline (TC) signaling molecule switching. Will target and TC-b... 详细信息
来源: 评论
Fitop-Trans: Maximizing Transformer Pipeline Efficiency through Fixed-Length Token Pruning on FPGA
Fitop-Trans: Maximizing Transformer Pipeline Efficiency thro...
收藏 引用
international conference on field programmable logic and applications
作者: Kejia Shi Manting Zhang Keqing Zhao Xiaoxing Wu Yang Liu Jun Yu Kun Wang School of Microelectronics Fudan University Shanghai China
Recent years have witnessed Transformers emerge as a groundbreaking innovation in the Natural Language Processing (NLP) field. Unlike Recurrent Neural Network (RNN) models, Transformers process sequences in parallel, ... 详细信息
来源: 评论
Leveraging Dual Output LUTs with Pipelining for Efficient BCD to Binary Converter on FPGA
Leveraging Dual Output LUTs with Pipelining for Efficient BC...
收藏 引用
international conference on VLSI Design
作者: Santosh Kumar Ayan Palchaudhuri Department of Electronics & Communication Engineering School of Electrical and Computer Sciences Indian Institute of Technology Bhubaneswar Argul Khordha Odisha India
Decimal operands expressed in BCD is often the convenient data format used in embedded systems and human-centric applications. For optimized arithmetic computation on hardware where binary arithmetic can be convenient... 详细信息
来源: 评论
Small Area Footprint FPGA Architecture for Approximate atan2(a, b) Algorithm  9
Small Area Footprint FPGA Architecture for Approximate atan2...
收藏 引用
9th IEEE Uttar Pradesh Section international conference on Electrical, Electronics and Computer Engineering, UPCON 2022
作者: Kumar, Bharat Sarawadekar, Kishor Dept. of Electronics Engineering Varanasi India
Arctangent or inverse tangent function has numerous applications like gradient-based feature extraction, phase noise determination, range rate measurement etc. this paper presents a small area footprint hardware archi... 详细信息
来源: 评论
A Software-programmable Neural Processing Unit for Graph Neural Network Inference on FPGAs
A Software-Programmable Neural Processing Unit for Graph Neu...
收藏 引用
international conference on field programmable logic and applications
作者: Taikun Zhang Andrew Boutros Sergey Gribok Kwadwo Boateng Vaughn Betz Department of Electrical and Computer Engineering University of Toronto Toronto ON Canada Programmable Solutions Group Intel Corporation
Graph neural networks (GNNs) are a widely-used class of deep learning (DL) models for learning latent representations of graph-structured data for a variety of node/graph-level prediction tasks, some of which require ... 详细信息
来源: 评论
LORA: A Latency-Oriented Recurrent Architecture for GPT Model on Multi-FPGA Platform with Communication Optimization
LORA: A Latency-Oriented Recurrent Architecture for GPT Mode...
收藏 引用
international conference on field programmable logic and applications
作者: ZhenDong Zheng Qianyu Cheng Teng Wang Lei Gong Xianglan Chen Cheng Tang Chao Wang Xuehai Zhou School of Computer Science and Technology Suzhou Institute for Advanced Research University of Science and Technology of China
Large Language Models (LLMs) have been widely deployed in data centers to provide various services, among which the most representative is the Generative Pre-trained Transformer (GPT). the GPT model has heavy memory a... 详细信息
来源: 评论
NeuraLUT: Hiding Neural Network Density in Boolean Synthesizable Functions
NeuraLUT: Hiding Neural Network Density in Boolean Synthesiz...
收藏 引用
international conference on field programmable logic and applications
作者: Marta Andronic George A. Constantinides Department of Electrical and Electronic Engineering Imperial College London UK
field-programmable Gate Array (FPGA) accelerators have proven successful in handling latency- and resource-critical deep neural network (DNN) inference tasks. Among the most computationally intensive operations in a n... 详细信息
来源: 评论
New FPGA architecture for 8, 16 and 24 bit chaotic interleaver.  5
New FPGA architecture for 8, 16 and 24 bit chaotic interleav...
收藏 引用
5th international conference on Engineering Technology and its applications, IICETA 2022
作者: Humadi, Zeina Abdullah Al-Doori, Qusay F. University of Technology Control and Systems Engineering Department Baghdad Iraq
In a digital system, the interleaver is essential. It's widely used to enhance the effectiveness of forward error correction codes. A lot of research has shown the efficiency of the chaotic interleaver in correcti... 详细信息
来源: 评论
HASS: Hardware-Aware Sparsity Search for Dataflow DNN Accelerator
HASS: Hardware-Aware Sparsity Search for Dataflow DNN Accele...
收藏 引用
international conference on field programmable logic and applications
作者: Zhewen Yu Sudarshan Sreeram Krish Agrawal Junyi Wu Alexander Montgomerie-Corcoran Cheng Zhang Jianyi Cheng Christos-Savvas Bouganis Yiren Zhao Imperial College London UK University of Cambridge UK
Deep Neural Networks (DNNs) excel in learning hierarchical representations from raw data, such as images, audio, and text. To compute these DNN models with high performance and energy efficiency, these models are usua... 详细信息
来源: 评论
Low Precision Networks for Efficient Inference on FPGAs  20
Low Precision Networks for Efficient Inference on FPGAs
收藏 引用
20th international conference on field-programmable Technology (ICFPT)
作者: Abra, Ruth Denisenko, Dmitry Allen, Richard Vanderhoek, Tim Wolstencroft, Sarah Gibson, Mark Intel Corp Programmable Solut Grp Santa Clara CA 95051 USA Royal Holloway Univ London Egham Surrey England Univ Reading Reading Berks England
Block Floating Point (BFP) is a type of quantization that combines high dynamic range with low-cost inference. BFP can be implemented efficiently on FPGA hardware and, at low precision, halves the logic footprint vers... 详细信息
来源: 评论